DATA SHEET
www.onsemi.com
PYTHON 5.0/2.0 MegaPixels
Global Shutter CMOS
Image Sensors
NOIP1SN5000A
Features
• Data Output Options
P1−SN/SE/FN: 8 LVDS Data Channels
P3−SN/SE: 4 LVDS Data Channels
• Size Options
♦ PYTHON 2000: 1920 x 1200 Active Pixels, 2/3” Optical Format
Figure 1. PYTHON 5000
♦ PYTHON 5000: 2592 x 2048 Active Pixels, 1” Optical Format
• 4.8 mm x 4.8 mm Low Noise Global Shutter Pixels with
In-pixel CDS
ORDERING INFORMATION
• Monochrome (SN), Color (SE) and NIR (FN)
See detailed ordering and shipping information on page 2 of
this data sheet.
• Zero Row Overhead Time Mode Enabling Higher Frame Rate
• Frame Rate at Full Resolution, 8 LVDS Data Channels
(P1−SN/SE/FN only)
♦ 100/85 frames per second @ 5 MP (Zero ROT/Non−Zero ROT)
♦ 230/180 frames per second @ 2 MP (Zero ROT/Non−Zero ROT)
♦ 255/200 frames per second @ Full HD (Zero ROT/Non−Zero ROT)
• On-chip 10-bit Analog-to-Digital Converter (ADC)
Description
• Eight/Four/Two/One LVDS High Speed Serial Outputs
The PYTHON 2000 and PYTHON 5000 image sensors
• Random Programmable Region of Interest (ROI)
utilize
high sensitivity 4.8 mm x 4.8 mm pixels that support
Readout
low noise “pipelined” and “triggered” global shutter readout
• Serial Peripheral Interface (SPI)
modes. The sensors support correlated double sampling
• Automatic Exposure Control (AEC)
(CDS) readout, reducing noise and increasing dynamic
• Phase Locked Loop (PLL)
range.
The sensor has on-chip programmable gain amplifiers and
• Dual Power Supply (3.3 V and 1.8 V)
10-bit A/D converters. The integration time and gain
• −40°C to +85°C Operational Temperature Range
parameters can be reconfigured without any visible image
• 84-pin LCC and 128−pad LGA
artifact. Optionally the on-chip automatic exposure control
• Power Dissipation
loop (AEC) controls these parameters dynamically. The
♦ 1.45 W (P1−SN/SE/FN, 8 LVDS, NZROT)
image’s black level is either calibrated automatically or can
♦ 915 mW (P1−SN/SE/FN, P3−SN/SE, 4 LVDS,
be adjusted by adding a user programmable offset.
NZROT)
A high level of programmability using a four wire serial
♦ 520 mW (P1−SN/SE/FN, P3−SN/SE, 2 LVDS,
peripheral
interface enables the user to read out specific
NZROT)
regions
of
interest. Up to sixteen regions can be
♦ 370 mW (P1−SN/SE/FN, P3−SN/SE, 1 LVDS,
programmed,
achieving even higher frame rates.
NZROT)
The image data interface of the P1−SN/SE/FN devices
• These Devices are Pb−Free and are RoHS Compliant
consists of eight LVDS lanes, facilitating frame rates up to
100 frames per second in Zero ROT mode for the PYTHON
Applications
5000. Each channel runs at 720 Mbps. A separate
• Machine Vision
synchronization channel containing payload information is
• Motion Monitoring
provided to facilitate the image reconstruction at the
• Security
receiving end.
• Intelligent Traffic Systems (ITS)
♦
♦
© Semiconductor Components Industries, LLC, 2016
August, 2021 − Rev. 6
1
Publication Order Number:
NOIP1SN5000A/D
NOIP1SN5000A
The P3−SN/SE devices are the same as the P1−SN/SE/FN
but with only four of the eight LVDS data channels enabled,
facilitating frame rates of 45 frames per second in Non Zero
ROT (NZROT) for the PYTHON 5000.
ORDERING INFORMATION
Part Number
Description
Package
PYTHON 5000
84−pin LCC
NOIP1SN5000A−QDI
5 MegaPixel, Monochrome
NOIP1SE5000A−QDI
5 MegaPixel, Bayer Color
NOIP1FN5000A−QDI
5 MegaPixel, Monochrome with enhanced NIR
NOIP1SN5000A−QTI
5 MegaPixel, Monochrome, Protective Film
NOIP1SE5000A−QTI
5 MegaPixel, Bayer Color, Protective Film
NOIP1FN5000A−QTI
5 MegaPixel, Monochrome with enhanced NIR, Protective Film
NOIP3SN5000A−QDI
5 MegaPixel, 4 LVDS Outputs, Monochrome
NOIP3SE5000A−QDI
5 MegaPixel, 4 LVDS Outputs, Bayer Color
NOIP3SN5000A−QTI
5 MegaPixel, 4 LVDS Outputs, Monochrome, Protective Film
NOIP3SE5000A−QTI
5 MegaPixel, 4 LVDS Outputs, Bayer Color, Protective Film
NOIP1SN5000A−LTI
5 MegaPixel, Monochrome, Protective Film
NOIP1SE5000A−LTI
5 MegaPixel, Bayer Color, Protective Film
NOIP1FN5000A−LTI
5 MegaPixel, Monochrome with enhanced NIR, Protective Film
NOIP3SN5000A−LTI
5 MegaPixel, 4 LVDS Outputs, Monochrome, Protective Film
NOIP3SE5000A−LTI
5 MegaPixel, 4 LVDS Outputs, Bayer Color, Protective Film
128−pad LGA
PYTHON 2000
84−pin LCC
NOIP1SN2000A−QDI
2 MegaPixel, Monochrome
NOIP1SE2000A−QDI
2 MegaPixel, Bayer Color
NOIP1FN2000A−QDI
2 MegaPixel, Monochrome with enhanced NIR
NOIP1SN2000A−QTI
2 MegaPixel, Monochrome, Protective Film
NOIP1SE2000A−QTI
2 MegaPixel, Bayer Color, Protective Film
NOIP1FN2000A−QTI
2 MegaPixel, Monochrome with enhanced NIR, Protective Film
NOIP1SN2000A−LTI
2 MegaPixel, Monochrome, Protective Film
NOIP1SE2000A−LTI
2 MegaPixel, Bayer Color, Protective Film
NOIP1FN2000A−LTI
2 MegaPixel, Monochrome with enhanced NIR, Protective Film
128−pad LGA
The P1−SN/SE/FN base part references the mono, color and NIR enhanced versions of the 8 LVDS interface; the P3−SN/SE
base part references the mono and color version of the 4 LVDS interface. More details on the part number coding can be found
at http://www.onsemi.com/pub_link/Collateral/TND310−D.PDF
Package Mark for LCC−84 Pin Package
Line 1: NOIPyxx RRRRA where y is either “1” for 8 LVDS Outputs, “3” for 4 LVDS Outputs.
where xx denotes mono micro lens (SN) or color micro lens (SE) or NIR micro lens (FN)
RRRR is the resolution (5000), (2000)
Line 2: −QDI (LCC−84 without protective film), −QTI (LCC−84 with protective film)
Line 3: AWLYYWW where AWL is PRODUCTION lot traceability, YYWW is the 4−digit date code
Package Mark for LGA−128 Pad Package
Package Side 1: NOIPyxxRRRRA−LTI where y is either “1” for 8 LVDS Outputs, “3” for 4 LVDS Outputs.
where xx denotes mono micro lens (SN) or color micro lens (SE)
RRRR is the resolution (5000), (2000)
−LTI (LGA−128 with protective film)
Package Side 2: AWLYYWW where AWL is PRODUCTION lot traceability, YYWW is the 4−digit date code
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2
NOIP1SN5000A
SPECIFICATIONS
Key Specifications
Table 2. NOMINAL ELECTRO−OPTICAL
SPECIFICATIONS
Table 1. GENERAL SPECIFICATIONS (Note 1)
Parameter
Specification
Pixel Type
Parameter
In−pixel CDS. Global shutter pixel architecture
Specification
Active Pixels
PYTHON 5000: 2592 (H) x 2048
(V)
PYTHON 2000: 1984 (H) x 1264
(V)
Pixel Size
4.8 mm x 4.8 mm
Conversion Gain
0.096 LSB10/e-, 140 mV/e-
Shutter Type
Pipelined and triggered global shutter
Frame Rate
Zero ROT/
Non−Zero ROT
Mode
P1−SN/SE/FN:
PYTHON 2000: 230/180 fps
PYTHON 5000: 100/85 fps
P3−SN/SE: NA/45 fps
Master Clock
P1−SN/SE/FN, P3−SN/SE:
72 MHz when PLL is used,
360 MHz (10-bit) / 288 MHz (8-bit)
when
PLL is not used
Temporal Noise
< 10.7 e- (Non−Zero ROT, 1x
gain)
< 9.4 e- (Non−Zero ROT, 2x gain)
Responsivity at 550 nm
7.5 V/lux.s
Windowing
16 Randomly programmable windows.
Normal, sub-sampled readout mode
Parasitic Light
Sensitivity (PLS)
10us
> 10us
> 10us
> 10us
> 10us
Figure 16. Power Up Sequence
Standby (1)
In standby state, the PLL/LVDS clock receiver is running,
but the derived logic clock signal is not enabled.
Enable Clock Management
In the idle state, all internal blocks are enabled, except the
sequencer block. The sensor is ready to start grabbing
images as soon as the sequencer block is enabled.
The ‘Enable Clock Management’ action configures the
clock management blocks and activates the clock generation
and distribution circuits in a pre−defined way. First, a set of
clock settings must be uploaded through the SPI register.
These settings are dependent on the desired operation mode
of the sensor.
All SPI uploads to be executed to configure the sensor are
available to customers under NDA at the onsemi Image
Sensor Portal.
If the PLL is not used, the LVDS clock input must be
running.
Running
Use of Phase Locked Loop
Standby (2)
In standby state, the derived logic clock signal is running.
All SPI registers are active, meaning that all SPI registers
can be accessed for read or write operations. All other blocks
are disabled.
Idle
If PLL is used, the PLL is started after the upload of the
SPI registers. The PLL requires (dependent on the settings)
some time to generate a stable output clock. A lock detect
circuit detects if the clock is stable. When complete, this is
flagged in a status register.
Check the PLL_lock flag 24[0] by reading the SPI
register. When the flag is set, the ‘Enable Clock
Management− Part 2’ action can be continued. When PLL
is not used, this step can be bypassed as shown in Figure 15
on page 15.
In running state, the sensor is enabled and grabbing
images. The sensor can be operated in global master/slave
modes.
User Actions: Power Up Functional Mode Sequences
Power Up Sequence
Figure 16 shows the power up sequence of the sensor. The
figure indicates that the first supply to ramp−up is the
vdd_18 supply, followed by vdd_33 and vdd_pix
respectively. It is important to comply with the described
sequence. Any other supply ramping sequence may lead to
high current peaks and, as consequence, a failure of the
sensor power up.
The clock input should start running when all supplies are
stabilized. When the clock frequency is stable, the reset_n
signal can be de−asserted. After a wait period of 10 ms, the
power up sequence is finished and the first SPI upload can
be initiated.
NOTE: The ‘clock input’ can be the CMOS PLL clock
input (clk_pll), or the LVDS clock input
(lvds_clock_inn/p) in case the PLL is bypassed.
Required Register Upload
In this phase, the ‘reserved’ register settings are uploaded
through the SPI register. Different settings are not allowed
and may cause the sensor to malfunction.
Soft Power Up
During the soft power up action, the internal blocks are
enabled and prepared to start processing the image data
stream. This action exists of a set of SPI uploads.
Enable Sequencer
During the ‘Enable Sequencer’ action, the frame grabbing
sequencer is enabled. The sensor starts grabbing images in
the configured operation mode. Refer to Sensor States on
page 16.
The ‘Enable Sequencer’ action consists of enabling bit
192[0].
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NOIP1SN5000A
User Actions: Functional Modes to Power Down Sequences
Disable Sequencer
first vdd_pix, second vdd_33, and finally vdd_18. Any other
sequence can cause high peak currents.
NOTE: The ‘clock input’ can be the CMOS PLL clock
input (clk_pll), or the LVDS clock input
(lvds_clock_inn/p) in case the PLL is bypassed.
During the ‘Disable Sequencer’ action, the frame
grabbing sequencer is stopped. The sensor stops grabbing
images and returns to the idle mode.
The ‘Disable Sequencer’ action consists of disabling bit
192[0].
Soft Power Down
During the soft power down action, the internal blocks are
disabled and the sensor is put in standby state to reduce the
current dissipation. This action exists of a set of SPI uploads.
clock input
reset_n
Disable Clock Management
The ‘Disable Clock Management’ action stops the
internal clocking to further decrease the power dissipation.
vdd_18
vdd_33
Power Down Sequence
Figure 17 illustrates the timing diagram of the preferred
power down sequence. It is important that the sensor is in
reset before the clock input stops running. Otherwise, the
internal PLL becomes unstable and the sensor gets into an
unknown state. This can cause high peak currents.
The same applies for the ramp down of the power
supplies. The preferred order to ramp down the supplies is
vdd_pix
> 10us
> 10us
> 10us
> 10us
Figure 17. Power Down Sequence
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NOIP1SN5000A
Sensor Reconfiguration
Sensor Configuration
During the standby, idle, or running state several sensor
parameters can be reconfigured.
• Frame Rate and Exposure Time: Frame rate and
exposure time changes can occur during standby, idle,
and running states by modifying registers 199 to 203.
Refer to page 30−32 for more information.
• Signal Path Gain: Signal path gain changes can occur
during standby, idle, and running states by modifying
registers 204/205. Refer to page 37 for more
information.
• Windowing: Changes with respect to windowing can
occur during standby, idle, and running states. Refer to
Multiple Window Readout on page 26 for more
information.
• Subsampling: Changes of the subsampling mode can
occur during standby, idle, and running states by
modifying register 192. Refer to Subsampling on
page 27 for more information.
• Shutter Mode: The shutter mode can only be changed
during standby or idle mode by modifying register 192.
Reconfiguring the shutter mode during running state is
not supported.
This device contains multiple configuration registers.
Some of these registers can only be configured while the
sensor is not acquiring images (while register 192[0] = 0),
while others can be configured while the sensor is acquiring
images. For the latter category of registers, it is possible to
distinguish the register set that can cause corrupted images
(limited number of images containing visible artifacts) from
the set of registers that are not causing corrupted images.
These three categories are described here.
Static Readout Parameters
Some registers are only modified when the sensor is not
acquiring images. reconfiguration of these registers while
images are acquired can cause corrupted frames or even
interrupt the image acquisition. Therefore, it is
recommended to modify these static configurations while
the sequencer is disabled (register 192[0] = 0). The registers
shown in Table 15 should not be reconfigured during image
acquisition. A specific configuration sequence applies for
these registers. Refer to the operation flow and startup
description.
Table 6. STATIC READOUT PARAMETERS
Group
Addresses
Description
Clock generator
32
Configure according to recommendation
Image core
40
Configure according to recommendation
AFE
48
Configure according to recommendation
Bias
64–71
Configure according to recommendation
Charge Pump
72
Configure according to recommendation
LVDS
112
Configure according to recommendation
Sequencer mode selection
192 [6:1]
All reserved registers
Operation modes are:
• triggered_mode
• slave_mode
Keep reserved registers to their default state, unless otherwise described in the
recommendation
Dynamic Configuration Potentially Causing Image
Artifacts
image containing visible artifacts. A typical example of a
corrupted image is an image which is not uniformly
exposed.
The effect is transient in nature and the new configuration
is applied after the transient effect.
The category of registers as shown in Table 16 consists of
configurations that do not interrupt the image acquisition
process, but may lead to one or more corrupted images
during and after the reconfiguration. A corrupted image is an
Table 7. DYNAMIC CONFIGURATION POTENTIALLY CAUSING IMAGE ARTIFACTS
Group
Black level configuration
Addresses
Description
128–129
197[12:8]
Reconfiguration of these registers may have an impact on the black−level
calibration algorithm. The effect is a transient number of images with incorrect black
level
compensation.
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NOIP1SN5000A
Table 7. DYNAMIC CONFIGURATION POTENTIALLY CAUSING IMAGE ARTIFACTS
Sync codes
129[13]
116–126
Datablock test configurations
Incorrect sync codes may be generated during the frame in which these registers
are modified.
144, 146–150
Modification of these registers may generate incorrect test patterns during
a transient frame.
Dynamic Readout Parameters
shown in Table 8. Some reconfiguration may lead to one
frame being blanked. This happens when the modification
requires more than one frame to settle. The image is blanked
out and training patterns are transmitted on the data and sync
channels.
It is possible to reconfigure the sensor while it is acquiring
images. Frame related parameters are internally
resynchronized to frame boundaries, such that the modified
parameter does not affect a frame that has already started.
However, there can be restrictions to some registers as
Table 8. DYNAMIC READOUT PARAMETERS
Group
Addresses
Subsampling
192[7]
Description
Subsampling is synchronized to a new frame start.
ROI configuration
195
256–303
A ROI switch is only detected when a new window is selected as the active window
(reconfiguration of register 195). reconfiguration of the ROI dimension of the active window does not lead to a frame blank and can cause a corrupted image.
Exposure
reconfiguration
199−203
Exposure reconfiguration does not cause artifact. However, a latency of one frame is observed unless reg_seq_exposure_sync_mode is set to ‘1’ in triggered global mode (master).
204
Gains are synchronized at the start of a new frame. Optionally, one frame latency can be
incorporated to align the gain updates to the exposure updates
(refer to register 204[13] − gain_lat_comp).
Gain reconfiguration
Freezing Active Configurations
them for the coming frames. The freezing of the active set
of registers can be programmed in the sync_configuration
registers, which can be found at the SPI address 206.
Figure 18 shows a reconfiguration that does not use the
sync_configuration option. As depicted, new SPI
configurations are synchronized to frame boundaries.
Figure 19 shows the usage of the sync_configuration
settings. Before uploading a set of registers, the
corresponding sync_configuration is de−asserted. After the
upload is completed, the sync_configuration is asserted
again and the sensor resynchronizes its set of registers to the
coming frame boundaries. As seen in the figure, this ensures
that the uploads performed at the end of frame N+2 and the
start of frame N+3 become active in the same frame (frame
N+4).
Though the readout parameters are synchronized to frame
boundaries, an update of multiple registers can still lead to
a transient effect in the subsequent images, as some
configurations require multiple register uploads. For
example, to reconfigure the exposure time in master global
mode, both the fr_length and exposure registers need to be
updated. Internally, the sensor synchronizes these
configurations to frame boundaries, but it is still possible
that the reconfiguration of multiple registers spans over two
or even more frames. To avoid inconsistent combinations,
freeze the active settings while altering the SPI registers by
disabling synchronization for the corresponding
functionality before reconfiguration. When all registers are
uploaded, re−enable the synchronization. The sensor’s
sequencer then updates its active set of registers and uses
Time Line
Frame NFrame N+1 Frame N+2 Frame N+3
Frame N+4
SPI Registers
Active Registers
Figure 18. Frame Synchronization of Configurations (no freezing)
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19
NOIP1SN5000A
Frame NFrame N+1 Frame N+2 Frame N+3 Frame N+4
Time Line
sync_configuration
This configuration is not taken into
account as sync_register is inactive.
SPI Registers
Active Registers
Figure 19. reconfiguration Using Sync_configuration
NOTE: SPI updates are not taken into account while sync_configuration is inactive. The active configuration is frozen
for the sensor. Table 9 lists the several sync_configuration possibilities along with the respective registers being
frozen.
Table 9. ALTERNATE SYNC CONFIGURATIONS
Group
Affected Registers
Description
sync_black_lines
black_lines
Update of black line configuration is not synchronized at start of frame when ‘0’.
The sensor continues with its previous configurations.
sync_exposure
mult_timer
fr_length
exposure
Update of exposure configurations is not synchronized at start of frame when ‘0’.
The sensor continues with its previous configurations.
sync_gain
mux_gainsw
afe_gain
Update of gain configurations is not synchronized at start of frame when ‘0’.
The sensor continues with its previous configurations.
sync_roi
roi_active0[15:0]
subsampling
Update of active ROI configurations is not synchronized at start of frame when ‘0’.
The sensor continues with its previous configurations.
Note: The window configurations themselves are not frozen. reconfiguration of
active windows is not gated by this setting.
Window Configuration
Black Calibration
The sensor automatically calibrates the black level for
each frame. Therefore, the device generates a configurable
number of electrical black lines at the start of each frame.
The desired black level in the resulting output interface can
be configured and is not necessarily targeted to ‘0’.
Configuring the target to a higher level yields some
information on the left side of the black level distribution,
while the other end of the distribution tail is clipped to ‘0’
when setting the black level target to ‘0’.
The black level is calibrated for the 16 columns contained
in one kernel. This implies 16 black level offsets are
generated and applied to the corresponding columns.
Configurable parameters for the black−level algorithm are
listed in Table 19.
Global Shutter Mode
Up to 16 windows can be defined in global shutter mode
(pipelined or triggered). The windows are defined by
registers 256 to 303. Each window can be activated or
deactivated separately using register 195. It is possible to
reconfigure the inactive windows while the sensor is
acquiring images.
Switching between predefined windows is achieved by
activation of the respective windows. This way a minimum
number of registers need to be uploaded when it is necessary
to switch between two or more sets of windows. As an
example of this, scanning the scene at higher frame rates
using multiple windows and switching to full frame capture
when the object is tracked. Switching between the two
modes only requires an upload of one register.
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NOIP1SN5000A
Table 10. CONFIGURABLE PARAMETERS FOR BLACK LEVEL ALGORITHM
Address
Register Name
Description
Black Line Generation
197[7:0]
black_lines
This register configures the number of black lines that are generated at the start of a
frame. At least one black line must be generated. The maximum number is 255.
Note: When the automatic black−level calibration algorithm is enabled, make sure that this
register is configured properly to produce sufficient black pixels for the black−level filtering.
The number of black pixels generated per line is dependent on the operation mode and
window configurations:
Each black line contains 162 kernels.
197[12:8]
gate_first_line
A number of black lines are blanked out when a value different from 0 is configured. These
blanked out lines are not used for black calibration. It is recommended to enable this functionality, because the first line can have a different behavior caused by boundary effects.
When enabling, the number of black lines must be set to at least two in order to have valid
black samples for the calibration algorithm.
Black Value Filtering
129[0]
auto_blackcal_enable
Internal black−level calibration functionality is enabled when set to ‘1’. Required black level
offset compensation is calculated on the black samples and applied to all image pixels.
When set to ‘0’, the automatic black−level calibration functionality is disabled. It is possible
to apply an offset compensation to the image pixels, which is defined by the registers
129[10:1].
Note: Black sample pixels are not compensated; the raw data is sent out to provide
external statistics and, optionally, calibrations.
129[9:1]
blackcal_offset
Black calibration offset that is added or subtracted to each regular pixel value when auto_blackcal_enable is set to ‘0’. The sign of the offset is determined by register 129[10]
(blackcal_offset_dec).
Note: All channels use the same offset compensation when automatic black calibration is
disabled.
129[10]
blackcal_offset_dec
Sign of blackcal_offset. If set to ‘0’, the black calibration offset is added to each pixel. If set
to ‘1’, the black calibration offset is subtracted from each pixel.
This register is not used when auto_blackcal_enable is set to ‘1’.
128[10:8]
black_samples
The black samples are low−pass filtered before being used for black level calculation. The
more samples are taken into account, the more accurate the calibration, but more samples
require more black lines, which in turn affects the frame rate.
The effective number of samples taken into account for filtering is 2^ black_samples.
Note: An error is reported by the device if more samples than available are requested
(refer to register 136).
Black Level Filtering Monitoring
136
blackcal_error0
An error is reported by the device if there are requests for more samples than are available
(each bit corresponding to one data path). The black level is not compensated correctly if
one of the channels indicates an error. There are three possible methods to overcome this
situation and to perform a correct offset compensation:
• Increase the number of black lines such that enough samples are generated at the
cost of increasing frame time (refer to register 197).
• Relax the black calibration filtering at the cost of less accurate black level determination (refer to register 128).
• Disable automatic black level calibration and provide the offset via SPI register upload.
Note that the black level can drift in function of the temperature. It is thus recommended
to perform the offset calibration periodically to avoid this drift.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
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NOIP1SN5000A
Serial Peripheral Interface
first. The sck clock is passed through to the sensor
as indicated in Figure 20. The sensor samples this
address data on a rising edge of the sck clock
(mosi needs to be driven by the system on the
falling edge of the sck clock).
3. The tenth bit sent by the master indicates the type
of transfer: high for a write command, low for a
read command.
4. Data transmission:
- For write commands, the master continues
sending the 16−bit data, most significant bit first.
- For read commands, the sensor returns the data on
the requested address on the miso pin, most
significant bit first. The miso pin must be sampled
by the system on the falling edge of sck (assuming
nominal system clock frequency and maximum
10 MHz SPI frequency).
5. When data transmission is complete, the system
deselects the sensor one clock period after the last
bit transmission by pulling ss_n high.
Note that the maximum frequency for the SPI interface
scales with the input clock frequency, bit depth and LVDS
output multiplexing as described in Table 5.
Consecutive SPI commands can be issued by leaving at
least two SPI clock periods between two register uploads.
Deselect the chip between the SPI uploads by pulling the
ss_n pin high.
The sensor configuration registers are accessed through
an SPI. The SPI consists of four wires:
• sck: Serial Clock
• ss_n: Active Low Slave Select
• mosi: Master Out, Slave In, or Serial Data In
• miso: Master In, Slave Out, or Serial Data Out
The SPI is synchronous to the clock provided by the
master (sck) and asynchronous to the sensor’s system clock.
When the master wants to write or read a sensor’s register,
it selects the chip by pulling down the Slave Select line
(ss_n). When selected, data is sent serially and synchronous
to the SPI clock (sck).
Figure 20 shows the communication protocol for read and
write accesses of the SPI registers. The PYTHON sensor
uses 9−bit addresses and 16−bit data words.
Data driven by the system is colored blue in Figure 16,
while data driven by the sensor is colored yellow. The data
in grey indicates high−Z periods on the miso interface. Red
markers indicate sampling points for the sensor (mosi
sampling); green markers indicate sampling points for the
system (miso sampling during read operations).
The access sequence is:
1. Select the sensor for read or write by pulling down
the ss_n line.
2. One SPI clock cycle after selecting the sensor, the
9−bit address is transferred, most significant bit
SPI − WRITE
ss_n
t_sckss
tsck
t_sssck
sck
ts _mos i
mosi
A8
th_mosi
A7
..
..
..
A1
A0
`1'
D15
D14
..
..
..
..
D1
D0
miso
SPI − READ
ss_n
t_sssck
t_sckss
tsck
sck
ts_mosi
mosi
A8
th_mosi
A7
..
..
..
A1
A0
`0'
ts _miso
miso
D15
th_miso
D14
..
..
Figure 20. SPI Read and Write Timing Diagram
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..
..
D1
D0
NOIP1SN5000A
Table 11. SPI TIMING REQUIREMENTS
Group
Addresses
Description
Units
100 (*)
ns
ss_n low to sck rising edge
tsck
ns
tsckss
sck falling edge to ss_n high
tsck
ns
ts_mosi
Required setup time for mosi
20
ns
th_mosi
Required hold time for mosi
20
ns
ts_miso
Setup time for miso
tsck/2−10
ns
th_miso
Hold time for miso
tsck/2−20
ns
tspi
Minimal time between two consecutive SPI accesses (not shown in figure)
2 x tsck
ns
tsck
sck clock period
tsssck
*Value indicated is for nominal operation. The maximum SPI clock frequency depends on the sensor configuration (operation mode, input clock).
tsck is defined as 1/fSPI. See text for more information on SPI clock frequency restrictions.
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NOIP1SN5000A
IMAGE SENSOR TIMING AND READOUT
Global Shutter Mode
exposure time. The length of the exposure time is defined by
the registers exposure and mult_timer.
NOTE: The start of the exposure time is synchronized to
the start of a new line (during ROT) if the
exposure period starts during a frame readout.
As a consequence, the effective time during
which the image core is in a reset state is
extended to the start of a new line.
• Make sure that the sum of the reset time and exposure
time exceeds the time required to readout all lines. If
this is not the case, the exposure time is extended until
all (active) lines are read out.
• Alternatively, it is possible to specify the frame time
and exposure time. The sensor automatically calculates
the required reset time. This mode is enabled by the
fr_mode register. The frame time is specified in the
register fr_length.
Pipelined Global Shutter (Master)
The integration time is controlled by the registers
fr_length[15:0] and exposure[15:0]. The mult_timer
configuration defines the granularity of the registers
reset_length and exposure and is read as number of system
clock cycles.
The exposure control for (Pipelined) Global Master mode
is depicted in Figure 21.
The pixel values are transferred to the storage node during
FOT, after which all photo diodes are reset. The reset state
remains active for a certain time, defined by the reset_length
and mult_timer registers, as shown in the figure. Note that
meanwhile the image array is read out line by line. After this
reset period, the global photodiode reset condition is
abandoned. This indicates the start of the integration or
Frame N
Exposure State
FOT
Readout
FOT
Reset
Frame N+1
Integrating
FOT
Reset
Integrating
FOT
FOT
FOT
Image Array Global Reset
reset_length
x
mult_timer
exposure
x
mult_timer
= ROT
= Readout
= Readout Dummy Line (blanked)
Figure 21. Integration Control for (Pipelined) Global Shutter Mode (Master)
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NOIP1SN5000A
Triggered Global Shutter (Master)
exposure and mult_timer, as in the master pipelined global
mode. The fr_length configuration is not used. This
operation is graphically shown in Figure 22.
In master triggered global mode, the start of integration
time is controlled by a rising edge on the trigger0 pin. The
exposure or integration time is defined by the registers
Frame N
Exposure State
FOT
Reset
Integrating
FOT
Reset
Integrating
FOT
(No effect on falling edge)
trigger0
Readout
Frame N+1
FOT
FOT
FOT
Image Array Global Reset
exposure x mult_timer
= ROT
= Readout
= Readout Dummy Line (blanked)
Figure 22. Exposure Time Control in Triggered Shutter Mode (Master)
the pixel storage node and readout of the image array. In
other words, the high time of the trigger pin indicates the
integration time, the period of the trigger pin indicates the
frame time.
The use of the trigger during slave mode is shown in
Figure 23.
Notes:
• The falling edge on the trigger pin does not have any
impact. Note however the trigger must be asserted for
at least 100 ns.
• The start of the exposure time is synchronized to the
start of a new line (during ROT) if the exposure period
starts during a frame readout. As a consequence, the
effective time during which the image core is in a reset
state is extended to the start of a new line.
• If the exposure timer expires before the end of readout,
the exposure time is extended until the end of the last
active line.
• The trigger pin needs to be kept low during the FOT.
The monitor pins can be used as a feedback to the
FPGA/controller (eg. use monitor0, indicating the very
first line when monitor_select = 0x5 − a new trigger can
be initiated after a rising edge on monitor0).
Notes:
• The registers exposure, fr_length, and mult_timer are
•
•
•
Triggered Global Shutter (Slave)
Exposure or integration time is fully controlled by means
of the trigger pin in slave mode. The registers fr_length,
exposure and mult_timer are ignored by the sensor.
A rising edge on the trigger pin indicates the start of the
exposure time, while a falling edge initiates the transfer to
not used in this mode.
The start of exposure time is synchronized to the start
of a new line (during ROT) if the exposure period starts
during a frame readout. As a consequence, the effective
time during which the image core is in a reset state is
extended to the start of a new line.
If the trigger is de−asserted before the end of readout,
the exposure time is extended until the end of the last
active line.
The trigger pin needs to be kept low during the FOT.
The monitor pins can be used as a feedback to the
FPGA/controller (eg. use monitor0, indicating the very
first line when monitor_select = 0x5 − a new trigger can
be initiated after a rising edge on monitor0).
Frame N
Exposure State
FOT
Reset
Frame N+1
Integrating
FOT
Reset
Integrating
FOT
trigger0
Readout
FOT
FOT
FOT
Image Array Global Reset
= ROT
= Readout
= Readout Dummy Line (blanked)
Figure 23. Exposure Time Control in Global−Slave Mode
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NOIP1SN5000A
ADDITIONAL FEATURES
Multiple Window Readout
The PYTHON 2000 and PYTHON 5000 sensor supports
multiple window readout, which means that only the
user−selected Regions Of Interest (ROI) are read out. This
allows limiting data output for every frame, which in turn
allows increasing the frame rate. In global shutter mode, up
to eight ROIs can be configured.
y1_end
ROI 1
y0_end
y1_start
ROI 0
Window Configuration
Figure 24 shows the four parameters defining a region of
interest (ROI).
y0_start
y-end
x0_start
x0_end
x1_start
x1_end
Figure 25. Overlapping Multiple Window
Configuration
ROI 0
The sequencer analyses each line that needs to be read out
for multiple windows.
y-start
Restrictions
The following restrictions for each line are assumed for
the user configuration:
• Windows are ordered from left to right, based on their
x−start address:
x-start x-end
Figure 24. Region of Interest Configuration
x_start_roi(i) v x_start_roi(j) AND
• x−start[7:0]
x_end_roi(i) vx_end_roi(j)
x−start defines the x−starting point of the desired window.
The sensor reads out 16 pixels in one single clock cycle. As
a consequence, the granularity for configuring the x−start
position is also 16 pixels for no sub sampling. The value
configured in the x−start register is multiplied by 16 to find
the corresponding column in the pixel array.
• x−end[7:0]
This register defines the window end point on the x−axis.
Similar to x−start, the granularity for this configuration is
one kernel. x−end needs to be larger than x−start.
• y−start[9:0]
The starting line of the readout window. The granularity
of this setting is one line, except with color sensors where it
needs to be an even number.
• y−end[9:0]
The end line of the readout window. y−end must be
configured larger than y−start. This setting has the same
granularity as the y−start configuration.
Up to eight windows can be defined, possibly (partially)
overlapping, as illustrated in Figure 25.
Where j > i
Processing Multiple Windows
The sequencer control block houses two sets of counters
to construct the image frame. As previously described, the
y−counter indicates the line that needs to be read out and is
incremented at the end of each line. For the start of the frame,
it is initialized to the y−start address of the first window and
it runs until the y−end address of the last window to be read
out. The last window is configured by the configuration
registers and it is not necessarily window #15.
The x−counter starts counting from the x−start address of
the window with the lowest ID which is active on the
addressed line. Only windows for which the current
y−address is enclosed are taken into account for scanning.
Other windows are skipped.
Figure 26 illustrates a practical example of a
configuration with five windows. The current position of the
read pointer (ys) is indicated by a red line crossing the image
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26
NOIP1SN5000A
array. For this position of the read pointer, three windows
need to be read out. The initial start position for the x−kernel
pointer is the x−start configuration of ROI1. Kernels are
scanned up to the ROI3 x−end position. From there, the
x−pointer jumps to the next window, which is ROI4 in this
illustration. When reaching ROI4’s x−end position, the read
pointer is incremented to the next line and xs is reinitialized
to the starting position of ROI1.
Notes:
• The starting point for the readout pointer at the start of
a frame is the y−start position of the first active
window.
• The read pointer is not necessarily incremented by one,
but depending on the configuration, it can jump in
y−direction. In Figure 26, this is the case when reaching
the end of ROI0 where the read pointer jumps to the
y−start position of ROI1
• The x−pointer starting position is equal to the x−start
configuration of the first active window on the current
line addressed. This window is not necessarily window
#0.
• The x−pointer is not necessarily incremented by one
each cycle. At the end of a window it can jump to the
start of the next window.
• Each window can be activated separately. There is no
restriction on which window and how many of the 16
windows are active.
ROI 2
ys
ROI 3
ROI 4
ROI 1
ROI 0
Figure 26. Scanning the Image Array with Five
Windows
Subsampling
Subsampling is used to reduce the image resolution. This
allows increasing the frame rate. Two subsampling modes
are supported: for monochrome and NIR enhanced sensors
(P1−SN/FN and P3−SN) and color sensors (P1−SE and
P3−SE).
Monochrome Sensors
For monochrome sensors, the read−1−skip−1
subsampling scheme is used. Subsampling occurs both in x−
and y− direction.
Color Sensors
For color sensors, the read−2−skip−2 subsampling
scheme is used. Subsampling occurs both in x− and y−
direction. Figure 27 shows which pixels are read and which
ones are skipped.
Figure 27. Subsampling Scheme for Monochrome and Color Sensors
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NOIP1SN5000A
Reverse Readout in Y−direction
channels. Using this function, one may for instance use the
device with sync+clock+8 data channels. Enabling the
channel multiplexing is done through register 32[5:4]. The
default value of 0 disables all channel multiplexing. Higher
values sets higher degree of channel multiplexing. The
channels that are used per degree of multiplexing are shown
in Table 5. The unused data channels are powered down and
will not send any data.
Reverse readout in y−direction can be done by asserting
reverse_y (reg 194[8]). The reference for y_start and y_end
pointers is reversed.
Channel Multiplexing
The PYTHON 2000 and PYTHON 5000 image sensors
contains a function for channel multiplexing the output
Table 12. LVDS DATA OUTPUT CHANNELS USED WITH CHANNEL MULTIPLEXING
# outputs
PYTHON 2000 / PYTHON 5000 − LVDS Channels
8 channels
Ch 0
Ch 1
Ch 2
4 channels
Ch 0
Ch 2
2 channels
Ch 0
Ch 2
1 channel
Ch 0
Ch 3
Ch 4
Ch 5
Ch 4
Ch 6
Ch 7
Ch 6
Register
32[5:4] Data
Register 211
Data
0
0x0E49
1
0x0E39
2
0x0E29
3
0x0E19
1. P1−SN/SE/FN supports 8, 4, 2, 1 LVDS outputs while P3−SN/SE supports 4, 2, 1 LVDS outputs.
2. Use P3−SN/SE bias uploads for P1−SN/SE/FN when operating in mux mode.
Black Reference
pixel data is transmitted over the usual output interface,
while the regular image data is compensated (can be
bypassed).
On the output interface, black lines can be seen as a
separate window, however without Frame Start and Ends
(only Line Start/End). The Sync code following the Line
Start and Line End indications (“window ID”) contains the
active window number, which is 0. Black reference data is
classified by a BL code.
The sensor reads out one or more black lines at the start of
every new frame. The number of black lines to be generated
is programmable and is minimal equal to 1. The length of the
black lines depends on the operation mode. The sensor
always reads out the entire line (162 kernels), independent
of window configurations.
The black references are used to perform black calibration
and offset compensation in the data channels. The raw black
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NOIP1SN5000A
Signal Path Gain
Digital Gain Stage
Analog Gain Stages
The digital gain stage allows fine gain adjustments on the
digitized samples. The gain configuration is an absolute 5.7
unsigned number (5 digits before and 7 digits after the
decimal point).
Referring to Table 13, several gain settings are available
in the analog data path to apply gain to the analog signal
before it is digitized.
The moment a gain reconfiguration is applied and
becomes valid can be controlled by the gain_lat_comp
configuration.
With ‘gain_lat_comp’ set to ‘0’, the new gain
configurations are applied from the very next frame.
With ‘gain_lat_comp’ set to ‘1’, the new gain settings are
postponed by one extra frame. This feature is useful when
exposure time and gain are reconfigured together, as an
exposure time update always has one frame latency.
Table 13. SIGNAL PATH GAIN STAGES
Analog Gain Non−
Zero and Zero ROT
Address
Gain Setting
204[12:0]
0x01E1
1
204[12:0]
0x00A1
1.6
204[12:0]
0x0021
2
204[12:0]
0x0083
2.6
204[12:0]
0x0085
3.2
204[12:0]
0x0081
4
204[12:0]
0x0086
5.3
204[12:0]
0x0082
8
NOTE: Device will meet the specifications after thermal
equilibrium has been established when mounted in a test
socket or printed circuit board with maintained transverse
airflow greater than 500 lfpm.
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NOIP1SN5000A
Automatic Exposure Control
AEC
Statistics
Requested Illumination Level
(Target)
Total Gain
Requested Gain
Changes
The exposure control mechanism has the shape of a
general feedback control system. Figure 28 shows the high
level block diagram of the exposure control loop.
AEC
Filter
AEC
Enforcer
Integration Time
Analog Gain (Coarse Steps)
Digital Gain (Fine Steps)
Image Capture
Figure 28. Automatic Exposure Control Loop
Three main blocks can be distinguished:
• The statistics block compares the average of the
current image’s samples to the configured target value
for the average illumination of all pixels
• The relative gain change request from the statistics
block is filtered through the AEC Filter block in the
time domain (low pass filter) before being integrated.
The output of the filter is the total requested gain in the
complete signal path.
• The enforcer block accepts the total requested gain and
distributes this gain over the integration time and gain
stages (both analog and digital)
calculated illumination and the target illumination the
statistics block requests a relative gain change.
Statistics Subsampling and Windowing
For average calculation, the statistics block will
sub−sample the current image or windows by taking every
fourth sample into account. Note that only the pixels read out
through the active windows are visible for the AEC. In the
case where multiple windows are active, the samples will be
selected from the total samples. Samples contained in a
region covered by multiple (overlapping) window will be
taking into account only once.
It is possible to define an AEC specific sub−window on
which the AEC will calculate it’s average. For instance, the
sensor can be configured to read out a larger frame, while the
illumination is measured on a smaller region of interest, e.g.
center weighted as shown in Table 14.
The automatic exposure control loop is enabled by
asserting the aec_enable configuration in register 160.
NOTE: Dual and Triple slope integration is not
supported in conjunction with the AEC.
AEC Statistics Block
The statistics block calculates the average illumination of
the current image. Based on the difference between the
Table 14. AEC SAMPLE SELECTION
Register
Name
Description
192[10]
roi_aec_enable
When 0x0, all active windows are selected for statistics calculation.
When 0x1, the AEC samples are selected from the active pixels contained in the region of interest defined
by roi_aec
253−255
roi_aec
These registers define a window from which the AEC samples will be selected when roi_aec_enable is
asserted.
Configuration is similar to the regular region of interests.
The intersection of this window with the active windows define the selected pixels. It is important that this
window at least overlaps with one or more active windows.
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NOIP1SN5000A
AEC Filter Block
Target Illumination
The target illumination value is configured by means of
register desired_intensity as shown in Table 15.
The filter block low−pass filters the gain change requests
received from the statistics block.
The filter can be restarted by asserting the restart_filter
configuration of register 160.
Table 15. AEC TARGET ILLUMINATION
CONFIGURATION
AEC Enforcer Block
Register
Name
Description
161[9:0]
desired_intensity
Target intensity value, on 10−bit scale.
For 8−bit mode, target value is configured on desired_intensity[9:2]
The enforcer block calculates the four different gain
parameters, based on the required total gain, thereby
respecting a specific hierarchy in those configurations.
Some (digital) hysteresis is added so that the (analog) sensor
settings don’t need to change too often.
Exposure Control Parameters
The several gain parameters are described below, in the
order in which these are controlled by the AEC for large
adjustments. Small adjustments are regulated by digital gain
only.
• Exposure Time
The exposure is the time between the global image array
reset de−assertion and the pixel charge transfer. The
granularity of the integration time steps is configured by the
mult_timer register.
NOTE: The exposure_time register is ignored when the
AEC is enabled. The register fr_length defines
the frame time and needs to be configured
accordingly.
• Analog Gain
The sensor has two analog gain settings. Typically the
AEC shall only regulate the first stage.
• Digital Gain
The last gain stage is a gain applied on the digitized
samples. The digital gain is represented by a 5.7 unsigned
number (i.e. 7 bits after the decimal point). While the analog
gain steps are coarse, the digital gain stage makes it possible
to achieve very fine adjustments.
Color Sensor
The weight of each color can be configured for color
sensors by means of scale factors. Note these scale factor are
only used to calculate the statistics in order to compensate
for (off−chip) white balancing and/or color matrices. The
pixel values itself are not modified.
The scale factors are configured as 3.7 unsigned numbers
(0x80 = unity). Refer to Table 16 for color scale factors. For
mono sensors, configure these factors to their default value.
Table 16. COLOR SCALE FACTORS
Register
Name
Description
162[9:0]
red_scale_factor
Red scale factor for AEC
statistics
163[9:0]
green1_scale_fact
or
Green1 scale factor for AEC
statistics
164[9:0]
green2_scale_fact
or
Green2 scale factor for AEC
statistics
165[9:0]
blue_scale_factor
Blue scale factor for AEC
statistics
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NOIP1SN5000A
AEC Control Range
AEC Update Frequency
The control range for each of the exposure parameters can
be pre−programmed in the sensor. Table 17 lists the relevant
registers.
Table 17. MINIMUM AND MAXIMUM EXPOSURE
CONTROL PARAMETERS
As an integration time update has a latency of one frame,
the exposure control parameters are evaluated and updated
every other frame.
Note: The gain update latency must be postpone to match
the integration time latency. This is done by asserting the
gain_lat_comp register on address 204[13].
Register
Exposure Control Status Registers
Name
Description
168[15:0]
min_exposure
Lower bound for the integration
time applied by the AEC
169[1:0]
min_mux_gain
Lower bound for the first stage
analog amplifier.
This stage has two
configurations with the following
approximative gains:
0x0 = 1x
0x1 = 2x
169[3:2]
min_afe_gain
Lower bound for the second
stage analog amplifier.
This stage has only one
configuration with the following
approximative gain:
0x0 = 1.00x
169[15:4]
170[15:0]
171[1:0]
171[3:2]
171[15:4]
min_digital_gain
max_exposure
max_mux_gain
max_afe_gain
max_digital_
gain
Configured integration and gain parameters are reported
to the user by means of status registers. The sensor provides
two levels of reporting: the status registers reported in the
AEC address space are updated once the parameters are
recalculated and requested to the internal sequencer. The
status registers residing in the sequencer’s address space on
the other hand are updated once these parameters are taking
effect on the image readout. Refer to Table 18 reflecting the
AEC and Sequencer Status registers.
Table 18. EXPOSURE CONTROL STATUS REGISTERS
Register
Name
Description
Lower bound for the digital gain
stage. This configuration
specifies the effective gain in 5.7
AEC Status Registers
184[15:0]
total_pixels
Total number of pixels taken into
account for the AEC statistics.
unsigned format
186[9:0]
average
Upper bound for the integration
time applied by the AEC
Calculated average illumination
level for the current frame.
187[15:0]
exposure
AEC calculated exposure.
Note: this parameter is updated at
the frame end.
188[1:0]
mux_gain
AEC calculated analog gain
(1st stage)
Note: this parameter is updated at
the frame end.
188[3:2]
afe_gain
AEC calculated analog gain
(2nd stage)
Note: this parameter is updated at
the frame end.
188[15:4]
digital_gain
AEC calculated digital gain
(5.7 unsigned format)
Note: this parameter is updated at
the frame end.
Upper bound for the first stage
analog amplifier.
This stage has two
configurations with the following
approximative gains:
0x0 = 1x
0x1 = 2x
Upper bound for the second
stage analog amplifier
This stage has only one
configuration with the following
approximative gain:
0x0 = 1.00x
Upper bound for the digital gain
stage. This configuration
specifies the effective gain in 5.7
unsigned format
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NOIP1SN5000A
Table 18. EXPOSURE CONTROL STATUS REGISTERS
Register
Name
Description
Sequencer Status Registers
242[15:0]
mult_timer
mult_timer for current frame
Note: this parameter is updated
once it takes effect on the image.
243[15:0]
reset_length
Image array reset length for the
current frame.
Note: this parameter is updated
once it takes effect on the image.
244[15:0]
exposure
Exposure for the current frame.
Note: this parameter is updated
once it takes effect on the image.
245[15:0]
exposure_ds
Dual slope exposure for the current
frame. Note this parameter is not
controlled by the AEC.
Note: this parameter is updated
once it takes effect on the image.
246[15:0]
exposure_ts
Triple slope exposure for the
current frame. Note this parameter
is not controlled by the AEC.
Note: this parameter is updated
once it takes effect on the image.
247[4:0]
mux_gainsw
1st stage analog gain for the current
frame.
Note: this parameter is updated
once it takes effect on the image.
247[12:5]
afe_gain
2nd stage analog gain for the current frame.
Note: this parameter is updated
once it takes effect on the image.
248[11:0]
db_gain
Digital gain configuration for the
current frame (5.7 unsigned
format).
Note: this parameter is updated
once it takes effect on the image.
248[12]
dual_slope
Dual slope configuration for the
current frame
Note 1: this parameter is updated
once it takes effect on the image.
Note 2: This parameter is not
controlled by the AEC.
248[13]
triple_slope
Triple slope configuration for the
current frame.
Note 1: this parameter is updated
once it takes effect on the image.
Note 2: This parameter is not
controlled by the AEC.
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NOIP1SN5000A
Mode Changes and Frame Blanking
summarized in the following table for the sensor’s image
related modes.
NOTE: Major mode switching (i.e. switching between
master, triggered or slave mode) must be
performed while the sequencer is disabled
(reg_seq_enable = 0x0).
Dynamically reconfiguring the sensor may lead to
corrupted or non-uniformilly exposed frames. For some
reconfigurations, the sensor automatically blanks out the
image data during one frame. Frame blanking is
Table 19. DYNAMIC SENSOR RECONFIGURATION AND FRAME BLANKING
Configuration
Corrupted
Frame
Blanked Out
Frame
Notes
Shutter Mode and Operation
triggered_mode
Do not reconfigure while the sensor is acquiring images. Disable image acquisition by setting
reg_seq_enable = 0x0.
slave_mode
Do not reconfigure while the sensor is acquiring images. Disable image acquisition by setting
reg_seq_enable = 0x0.
subsampling
Enabling: No
Disabling: Yes
Configurable
No
No
mult_timer
No
No
Latency is 1 frame
fr_length
No
No
Latency is 1 frame
exposure
No
No
Latency is 1 frame
mux_gainsw
No
No
Latency configurable by means of gain_lat_comp register
afe_gain
No
No
Latency configurable by means of gain_lat_comp register.
db_gain
No
No
Latency configurable by means of gain_lat_comp register.
roi_active
See Note
No
Windows containing lines previously not read out may lead to corrupted
frames.
roi*_configuration*
See Note
No
Reconfiguring the windows by means of roi*_configuration* may lead to
corrupted frames when configured close to frame boundaries.
It is recommended to (re)configure an inactive window and switch the
roi_active register.
See Notes on roi_active.
black_samples
No
No
If configured within range of configured black lines
auto_blackal_enable
See Note
No
Manual correction factors become instantly active when
auto_blackcal_enable is deasserted during operation.
blackcal_offset
See Note
No
Manual blackcal_offset updates are instantly active.
No
No
Impacts the transmitted CRC
bl_0
No
No
Impacts the Sync channel information, not the Data channels.
img_0
No
No
Impacts the Sync channel information, not the Data channels.
crc_0
No
No
Impacts the Sync channel information, not the Data channels.
tr_0
No
No
Impacts the Sync channel information, not the Data channels.
Configurable with blank_subsampling_ss register.
Frame Timing
black_lines
Exposure Control
Gain
Window/ROI
Black Calibration
CRC Calculation
crc_seed
Sync Channel
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NOIP1SN5000A
Temperature Sensor
Calibration using one temperature point
The PYTHON has an on−chip temperature sensor which
returns a digital code (Tsensor) of the silicon junction
temperature. The Tsensor output is a 8−bit digital count
between 0 and 255, proportional to the temperature of the
silicon substrate. This reading can be translated directly to
a temperature reading in °C by calibrating the 8−bit readout
at 0°C and 85°C to achieve an output accuracy of ±2°C. The
Tsensor output can also be calibrated using a single
temperature point (example: room temperature or the
ambient temperature of the application), to achieve an
output accuracy of ±5°C.
Note that any process variation will result in an offset in
the bit count and that offset will remain within ±5°C over the
temperature range of 0°C and 85°C. Tsensor output digital
code can be read out through the SPI interface.
The temperature sensor resolution is fixed for a given type
of package for the operating range of 0°C to +85°C and
hence devices can be calibrated at any ambient temperature
of the application, with the device configured in the mode of
operation.
Interpreting the actual temperature for the digital code
readout:
The formula used is
TJ = R (Nread − Ncalib) + Tcalib
TJ = junction die temperature
R = resolution in degrees/LSB (typical 0.75 deg/LSB)
Nread = Tsensor output (LSB count between 0 and 255)
Tcalib = Tsensor calibration temperature
Ncalib = Tsensor output reading at Tcalib
Output of the temperature sensor to the SPI:
Monitor Pins
tempd_reg_temp: This is the 8−bit N count readout
proportional to temperature.
The internal sequencer has two monitor outputs (monitor0
and monitor1) that can be used to communicate the internal
states from the sequencer. A three−bit register configures the
assignment of the pins as shown in Table 20.
Input from the SPI:
The reg_tempd_enable is a global enable and this enables
or disables the temperature sensor when logic high or logic
low respectively. The temperature sensor is reset or disabled
when the input reg_tempd_enable is set to a digital low state.
Table 20. REGISTER SETTING FOR THE MONITOR SELECT PIN
monitor_select [2:0]
192 [13:11]
monitor pin
0x0
monitor0
monitor1
‘0’
‘0’
0x1
monitor0
monitor1
Integration Time
ROT Indication (‘1’ during ROT, ‘0’ outside)
0x2
monitor0
monitor1
Integration Time
Dual/Triple Slope Integration (asserted during DS/TS FOT sequence)
0x3
monitor0
monitor1
Start of x−Readout Indication
Black Line Indication (‘1’ during black lines, ‘0’ outside)
0x4
monitor0
monitor1
Frame Start Indication
Start of ROT Indication
0x5
monitor0
monitor1
First Line Indication (‘1’ during first line, ‘0’ for all others)
Start of ROT Indication
0x6
monitor0
monitor1
ROT Indication (‘1’ during ROT, ‘0’ outside)
Start of X−Readout Indication
0x7
monitor0
monitor1
Start of X−readout Indication for Black Lines
Start of X−readout Indication for Image Lines
Description
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NOIP1SN5000A
DATA OUTPUT FORMAT
The frame format in 10−bit mode is explained by example
of the readout of two (overlapping) windows as shown in
Figure 29(a).
The readout of a frame occurs on a line−by−line basis. The
read pointer goes from left to right, bottom to top.
Figure 29 indicates that, after the FOT is completed, the
sensor reads out a number of black lines for black calibration
purposes. After these black lines, the windows are
processed. First a number of lines which only includes
information of ‘ROI 0’ are sent out, starting at position
y0_start. When the line at position y1_start is reached, a
number of lines containing data of ‘ROI 0’ and ‘ROI 1’ are
sent out, until the line position of y0_end is reached. From
there on, only data of ‘ROI 1’ appears on the data output
channels until line position y1_end is reached
During read out of the image data over the data channels,
the sync channel sends out frame synchronization codes
which give information related to the image data that is sent
over the four data output channels.
Each line of a window starts with a Line Start (LS)
indication and ends with a Line End (LE) indication. The
line start of the first line is replaced by a Frame Start (FS);
the line end of the last line is replaced with a Frame End
indication (FE). Each such frame synchronization code is
followed by a window ID (range 0 to 7). For overlapping
windows, the line synchronization codes of the overlapping
windows with lower IDs are not sent out (as shown in the
illustration: no LE/FE is transmitted for the overlapping part
of window 0).
NOTES: In Figure 29, only Frame Start and Frame End
Sync words are indicated in (b). CRC codes are
also omitted from the figure.
The PYTHON 2000 and PYTHON 5000 image sensors
are available in two LVDS output configuration,
P1−SN/SE/FN and P3−SN/SE. The P1−SN/SE/FN
configuration utilizes eight LVDS output channels together
with an LVDS clock output and an LVDS synchronization
output channel. The P3−SN/SE configuration consists of
four LVDS output channels together with an LVDS clock
output and an LVDS synchronization output channel.
P1−SN/SE/FN, P3−SN/SE: Interface Version
LVDS Output Channels
The image data output occurs through eight LVDS data
channels where a synchronization LVDS channel and an
LVDS output clock signal synchronizes the data.
Referring to Table 21, the eight data channels on the
P1−SN/SE/FN option are used to output the image data only,
while on the P3−SN/SE option, four data channel channels
are utilized. The sync channel transmits information about
the data sent over these data channels (includes codes
indicating black pixels, normal pixels, and CRC codes).
8−bit / 10−bit Mode
The sensor can be used in 8−bit or 10−bit mode.
In 10−bit mode, the words on data and sync channel have
a 10−bit length. The output data rate is 720 Mbps.
In 8−bit mode, the words on data and sync channel have
an 8−bit length, the output data rate is 576 Mbps.
Note that the 8−bit mode can only be used to limit the data
rate at the consequence of image data word depth. It is not
supported to operate the sensor in 8−bit mode at a higher
clock frequency to achieve higher frame rates. The
P1−SN/SE/FN option supports 10−bit/8−bit in
ZROT/NZROT mode, while the P3−SN/SE option supports
10−bit NZROT mode only.
For additional information on the
synchronization codes, please refer to PYTHON
Image Sensor Family Developer’s Guide
AND9362/D.
Frame Format
The frame format in 8−bit mode is identical to the 10−bit
mode with the exception that the Sync and data word depth
is reduced to eight bits.
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NOIP1SN5000A
y1_end
ROI 1
y0_end
y1_start
ROI 0
y0_start
x0_start
x0_end
x1_start
x1_end
(a)
Integration Time
Handling
Readout
Handling
FOT
É
É
B
L
Reset
N
Exposure Time N
FOT
Readout Frame N-1
ROI
1
ROI 0
FS0
FS1
FOT
FE1
Reset
N+1
É
É
B
L
Exposure Time N+1
FOT
Readout Frame N
ROI
1
ROI 0
FS0
FS1
FOT
FE1
(b)
Figure 29. P1−SN/SE/FN, P3−SN/SE: Frame Sync Codes
Figure 30 shows the detail of a black line readout during global or full−frame readout.
Sequencer
Internal State
FOT
ROT
ROT
black
line Ys
ROT
ROT
line Ys+1
line Ye
data channels
sync channel
data channels
sync channel
Training
TR
Training
LS
BL
timeslot
0
timeslot
1
BL
BL
BL
timeslot
157
BL
timeslot
158
BL
LE
timeslot
159
CRC
TR
CRC
timeslot
Figure 30. P1−SN/SE/FN, P3−SN/SE: Time Line for Black Line Readout
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37
NOIP1SN5000A
Figure 31 shows the details of the readout of a number of lines for single window readout, at the beginning of the frame.
Sequencer
Internal State
FOT
ROT
black
ROT
ROT
line Ys
ROT
line Ys+1
line Ye
data channels
sync channel
Training
data channels
TR
sync channel
Training
FS
ID
timeslot
Xstart
IMG
IMG
IMG
timeslot
Xstart + 1
IMG
timeslot
Xend - 2
IMG
IMG
timeslot
Xend - 1
ID
LE
CRC
timeslot
Xend
TR
CRC
timeslot
Figure 31. P1−SN/SE/FN, P3−SN/SE: Time Line for Single Window Readout (at the start of a frame)
Figure 32 shows the detail of the readout of a number of lines for readout of two overlapping windows.
Sequencer
Internal State
FOT
ROT
ROT
black
line Ys
ROT
ROT
line Ys+1
line Ye
data channels
sync channel
data channels
sync channel
Training
Training
TR
LS
IDM
IMG
IMG
LS
timeslot
XstartM
IDN
IMG
IMG
IMG LE
timeslot
XstartN
IDN
CRC
TR
timeslot
XendN
Figure 32. P1−SN/SE/FN, P3−SN/SE: Time Line Showing the Readout of Two Overlapping Windows
Frame Synchronization for 10−bit Mode
active at the same time, the sync channel transmits the frame
synchronization codes of the window with highest index
only.
Table 21 shows the structure of the frame synchronization
code. Note that the table shows the default data word
(configurable) for 10−bit mode. If more than one window is
Table 21. FRAME SYNCHRONIZATION CODE DETAILS FOR 10−BIT MODE
Sync Word Bit
Position
Register
Address
Default
Value
9:7
N/A
0x5
Frame start (FS) indication
9:7
N/A
0x6
Frame end (FE) indication
9:7
N/A
0x1
Line start (LS) indication
9:7
N/A
0x2
Line end (LE) indication
6:0
117[6:0]
0x2A
Description
These bits indicate that the received sync word is a frame synchronization code. The
value is programmable by a register setting
number, ranging from 0 to 7, indicating the active window.
If more than one window is active for the current cycle, the
highest window ID is transmitted.
Window Identification
Frame synchronization codes are always followed by a
3−bit window identification (bits 2:0). This is an integer
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NOIP1SN5000A
(BL), image data (IMG), or training pattern (TR). These
codes are programmable by a register setting. The default
values are listed in Table 22.
Data Classification Codes
For the remaining cycles, the sync channel indicates the
type of data sent through the data links: black pixel data
Table 22. SYNCHRONIZATION CHANNEL DEFAULT IDENTIFICATION CODE VALUES FOR 10−BIT MODE
Sync Word Bit
Position
Register
Address
Default
Value
9:0
118 [9:0]
0x015
Black pixel data (BL). This data is not part of the image. The black pixel data is used
internally to correct channel offsets.
9:0
119 [9:0]
0x035
Valid pixel data (IMG). The data on the data output channels is valid pixel data (part of the
image).
9:0
125 [9:0]
0x059
CRC value. The data on the data output channels is the CRC code of the finished image
data line.
9:0
126 [9:0]
0x3A6
Training pattern (TR). The sync channel sends out the training pattern which can be
programmed by a register setting.
Description
Frame Synchronization in 8−bit Mode
and not sent out. Table 32 shows the structure of the frame
synchronization code, together with the default value, as
specified in SPI registers. The same restriction for
overlapping windows applies in 8−bit mode.
The frame synchronization words are configured using
the same registers as in 10−bit mode. The two least
significant bits of these configuration registers are ignored
Table 23. FRAME SYNCHRONIZATION CODE DETAILS FOR 8−BIT MODE
Sync Word Bit
Position
Register
Address
Default
Value
7:5
N/A
0x5
Frame start (FS) indication
7:5
N/A
0x6
Frame end (FE) indication
7:5
N/A
0x1
Line start (LS) indication
Line end (LE) indication
7:5
N/A
0x2
4:0
117 [6:2]
0x0A
Description
These bits indicate that the received sync word is a frame synchronization code.
The value is programmable by a register setting.
Data Classification Codes
BL, IMG, CRC, and TR codes are defined by the same
registers as in 10−bit mode. Bits 9:2 of the respective
configuration registers are used as classification code with
default values shown in Table 24.
Window Identification
Similar to 10−bit operation mode, the frame
synchronization codes are followed by a window
identification. The window ID is located in bits 5:2 (all other
bit positions are ‘0’). The same restriction for overlapping
windows applies in 8−bit mode.
Table 24. SYNCHRONIZATION CHANNEL DEFAULT IDENTIFICATION CODE VALUES FOR 8−BIT MODE
Sync Word Bit
Position
Register
Address
Default
Value
7:0
118 [9:2]
0x05
Black pixel data (BL). This data is not part of the image. The black pixel data is used
internally to correct channel offsets.
7:0
119 [9:2]
0x0D
Valid pixel data (IMG). The data on the data output channels is valid pixel data (part of
the image).
7:0
125 [9:2]
0x16
CRC value. The data on the data output channels is the CRC code of the finished image
data line.
7:0
126 [9:2]
0xE9
Training Pattern (TR). The sync channel sends out the training pattern which can be
programmed by a register setting.
Description
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NOIP1SN5000A
Training Patterns on Data Channels
In 10−bit mode, during idle periods, the data channels
transmit training patterns, indicated on the sync channel by
a TR code. These training patterns are configurable
independent of the training code on the sync channel as
shown in Table 25.
Table 25. TRAINING CODE ON SYNC CHANNEL IN 10−BIT MODE
Sync Word Bit
Position
Register
Address
Default
Value
[9:0]
116 [9:0]
0x3A6
Description
Data channel training pattern. The data output channels send out the training pattern,
which can be programmed by a register setting. The default value of the training pattern
is 0x3A6, which is identical to the training pattern indication code on the sync channel.
In 8−bit mode, the training pattern for the data channels is
defined by the same register as in 10−bit mode, where the
lower two bits are omitted; see Table 26.
Table 26. TRAINING PATTERN ON DATA CHANNEL IN 8−BIT MODE
Data Word Bit
Position
Register
Address
Default
Value
[7:0]
116 [9:2]
0xE9
Description
Data Channel Training Pattern (Training pattern).
Cyclic Redundancy Code
at the start of a new line and updated for every (valid) data
word received. The CRC seed is configurable using the
crc_seed register. When ‘0’, the CRC is seeded by all−‘0’;
when ‘1’ it is seeded with all−‘1’.
In 8−bit mode, the polynomial is x8 + x6 + x3 + x2 + 1.
The CRC seed is configured by means of the crc_seed
register.
NOTE: The CRC is calculated for every line. This
implies that the CRC code can protect lines from
multiple windows.
At the end of each line, a CRC code is calculated to allow
error detection at the receiving end. Each data channel
transmits a CRC code to protect the data words sent during
the previous cycles. Idle and training patterns are not
included in the calculation.
The sync channel is not protected. A special character
(CRC indication) is transmitted whenever the data channels
send their respective CRC code.
The polynomial in 10−bit operation mode is
x10 + x9 + x6 + x3 + x2 + x + 1. The CRC encoder is seeded
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NOIP1SN5000A
Data Order for P1−SN/SE/FN, P3−SN/SE
Figure 33 indicates how the kernels are organized. The first
kernel (kernel [0, 0]) is located in the bottom left corner
(front view on top of the package). The data order of this
image data on the data output channels depends on the
subsampling mode.
To read out the image data through the output channels,
the pixel array is organized in kernels. The kernel size is
sixteen pixels in x−direction by one pixel in y−direction. The
data order in 8−bit mode is identical to the 10−bit mode.
kernel
(161,2047)
pixel array
ROI
kernel
(x_start,y_start)
kernel
(0,0)
0
1
2
3
13
14
15
Figure 33. Kernel Organization in Pixel Array − Top View
• P1−SN/SE/FN, P3−SN/SE: Subsampling Disabled
Figure 34 shows how a kernel is read out over the eight
output channels. For even positioned kernels, the kernels are
read out ascending, while for odd positioned kernels the data
order is reversed (descending).
♦ 8 LVDS Output Channels (P1−SN/SE/FN only)
The image data is read out in kernels of 16 pixels in
x−direction by one pixel in y−direction. One data channel
output delivers two pixel values of one kernel sequentially.
kernel N−2
kernel N−1
kernel N
kernel N+1
3
4
11
12
13
14
15
pixel # (odd kernel)
15
14
13
12
11
4
3
2
1
0
MSB
LSB
MSB
channel #7
2
channel #6
1
channel #1
0
channel #0
pixel # (even kernel)
LSB
Note: The bit order is always MSB first
10−bit
10−bit
Figure 34. P1−SN/SE/FN: 8 LVDS Data Output Order when Subsampling is Disabled
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NOIP1SN5000A
♦ 4 LVDS Output Channels
Figure 35 shows how a kernel is read out over the four
output channels. For even positioned kernels, the kernels are
kernel N−2
kernel N−1
read out ascending but in pair of even and odd pixels, while
for odd positioned kernels, the data order is reversed
(descending − in pair of even and odd pixels).
kernel N
kernel N+1
3
4
6
5
7
8
10
9
11
12
14
13
15
pixel # (odd kernel)
15
13
14
12
11
9
10
8
7
5
6
4
3
1
2
0
MSB
LSB
MSB
channel #6
1
channel #4
2
channel #2
0
channel #0
pixel # (even kernel)
LSB
Note: The bit order is always MSB first
10−bit
10−bit
Figure 35. P1−SN/SE/FN, P3−SN/SE: 4 LVDS Data Output Order when Subsampling is Disabled
♦ 2 LVDS Output Channels
Figure 36 shows how a kernel is read out over 2 output
channels. Each group of four adjacent channels is
multiplexed on to one channel. For even positioned kernels,
kernel N−2
kernel N−1
the kernels are read out in an ascending order but in sets of
four even and four odd pixels, while for odd positioned
kernels the data order is reversed (descending and in sets of
four odd and four even pixels).
kernel N
kernel N+1
2
4
6
1
3
5
7
8
10
12
14
9
11
13
15
pixel # (odd kernel)
15
13
11
9
14
12
10
8
7
5
3
1
6
4
2
0
MSB
LSB
10−bit
channel #4
0
channel #0
pixel # (even kernel)
MSB
LSB
10−bit
Note: The bit order is always MSB first
Figure 36. P1−SN/SE/FN, P3−SN/SE: 2 LVDS Data Output Order when Subsampling is Disabled
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NOIP1SN5000A
♦ 1 LVDS Output Channel
Figure 37 shows how a kernel is read out over 1 output
channel. Eight adjacent channels are multiplexed into one
channel. For even positioned kernels, the kernels are read
kernel N−2
kernel N−1
out ascending but in sets of 8 even and 8 odd pixels, while
for odd positioned kernels the data order is reversed
(descending − in sets of 8 odd and 8 even pixels).
kernel N
kernel N+1
0
2
4
6
8
10
12
14
1
3
5
7
9
11
13
15
pixel # (odd kernel)
15
13
11
9
7
5
3
1
14
12
10
8
6
4
2
0
channel #0
pixel # (even kernel)
MSB
MSB
LSB
LSB
Note: The bit order is always MSB first
10−bit
10−bit
Figure 37. P1−SN/SE/FN, P3−SN/SE: 1 LVDS Data Output Order when Subsampling is Disabled
• P1−SN/FN, P3−SN: Subsampling on Monochrome
Only the pixels at the even pixel positions inside that kernel
are read out.
♦ 8 LVDS Output Channels (P1−SN/FN only)
Figure 38 shows the data order for 8 LVDS output
channels. Note that there is no difference in data order for
even/odd kernel numbers, as opposed to the
‘no−subsampling’ readout described in previous section.
26
6
24
8
22
10
20
12
18
14
16
channel #7
4
kernel N+1
channel #5
28
channel #4
2
kernel N
channel #3
30
channel #1
0
channel #0
pixel #
kernel N−1
channel #2
kernel N−2
channel #6
Sensor
During subsampling on a monochrome sensor, every
other pixel is read out and the lines are read in a
read-1-skip-1 manner. To read out the image data with
subsampling enabled on a monochrome sensor, two
neighboring kernels are combined to a single kernel of
32 pixels in the x−direction and one pixel in the y−direction.
Figure 38. P1−SN/FN: Data Output Order for 8 LVDS Output Channels in Subsampling Mode on a Monochrome
Sensor
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NOIP1SN5000A
2
30
28
4
6
kernel N
26
24
8
kernel N+1
10
channel #2
0
channel #0
pixel #
kernel N−1
22
20
12
14
channel #4
kernel N−2
even/odd kernel numbers, as opposed to the
‘no−subsampling’ readout described in previous section.
18
16
channel #6
♦ 4 LVDS Output Channels
Figure 39 shows the data order for 4 LVDS output
channels. Note that there is no difference in data order for
Figure 39. P1−SN/FN, P3−SN: Data Output Order for 4 LVDS Output Channels in Subsampling Mode on a
Monochrome Sensor
♦ 2 LVDS Output Channels
Figure 40 shows the data order for 2 LVDS output
channels. Note that there is no difference in data order for
0
2
4
6
30
28
kernel N
26
24
8
kernel N+1
10
12
channel #0
pixel #
kernel N−1
14
22
20
18
16
channel #4
kernel N−2
even/odd kernel numbers, as opposed to the
‘no−subsampling’ readout described in previous section.
Figure 40. P1−SN/FN, P3−SN: Data Output Order for 2 LVDS Output Channels in Subsampling Mode on a
Monochrome Sensor
♦ 1 LVDS Output Channel
Figure 41 shows the data order for 1 LVDS output
channel. Note that there is no difference in data order for
kernel N−2
0
2
kernel N−1
4
6
8
10
kernel N
12
14
30
kernel N+1
28
26
24
22
20
18
16
channel #0
pixel #
even/odd kernel numbers, as opposed to the
‘no−subsampling’ readout described in previous section.
Figure 41. P1−SN/FN, P3−SN: Data Output Order for 1 LVDS Output Channels in Subsampling Mode on a
Monochrome Sensor
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NOIP1SN5000A
• P1−SE, P3−SE: Subsampling on Color Sensor
♦ 8 LVDS Output Channels (P1−SE only)
Figure 42 shows the data order for 8 LVDS output
channels. Note that there is no difference in data order for
even/odd kernel numbers, as opposed to the
‘no−subsampling’ readout described in previous section.
5
25
24
8
9
21
20
12
13
17
16
channel #7
4
channel #5
28
kernel N+1
channel #4
29
kernel N
channel #2
1
channel #1
0
channel #0
pixel #
kernel N−1
channel #3
kernel N−2
channel #6
During subsampling on a color sensor, lines are read in a
read-2-skip−2 manner. To read out the image data with
subsampling enabled on a color sensor, two neighboring
kernels are combined to a single kernel of 16 pixels in the
x−direction and one pixel in the y−direction. Only the pixels
0, 1, 4, 5, 8, 9, … 28, 29 are read out.
Figure 42. P1−SE: Data Output Order for 8 LVDS Output Channels in Subsampling Mode on a Color Sensor
♦ 4 LVDS Output Channels
Figure 43 shows the data order for 4 LVDS output
channels. Note that there is no difference in data order for
29
28
4
5
25
24
8
kernel N+1
9
21
20
12
13
17
16
channel #6
1
kernel N
channel #2
0
channel #0
pixel #
kernel N−1
channel #4
kernel N−2
even/odd kernel numbers, as opposed to the
‘no−subsampling’ readout described in previous section.
Figure 43. P1−SE, P3−SE: Data Output Order for 4 LVDS Output Channels in Subsampling Mode on a Color Sensor
♦ 2 LVDS Output Channels
Figure 44 shows the data order for 2 LVDS output
channels. Note that there is no difference in data order for
0
1
4
5
29
28
kernel N
25
24
8
channel #0
pixel #
kernel N−1
kernel N+1
9
12
13
21
20
17
16
channel #4
kernel N−2
even/odd kernel numbers, as opposed to the
‘no−subsampling’ readout described in previous section.
Figure 44. P1−SE, P3−SE: Data Output Order for 2 LVDS Output Channels in Subsampling Mode on a Color Sensor
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NOIP1SN5000A
♦ 1 LVDS Output Channel
Figure 45 shows the data order for 1 LVDS output
channel. Note that there is no difference in data order for
kernel N−2
0
1
kernel N−1
4
5
8
9
kernel N
12
13
29
kernel N+1
28
25
24
21
20
17
16
channel #0
pixel #
even/odd kernel numbers, as opposed to the
‘no−subsampling’ readout described in previous section.
Figure 45. P1−SE, P3−SE: Data Output Order for 1 LVDS Output Channel in Subsampling Mode on a Color Sensor
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NOIP1SN5000A
REGISTER MAP
The table below represents the register map for the
NOIP1xx5000A part. Deviating default values for the
NOIP1xx2000A sensor are mentioned between brackets
(“[ ]”).
Table 27. REGISTER MAP
Address
Offset
Address
Bit Field
Register Name
Default
(Hex)
Default
Description
Type
Chip ID [Block Offset: 0]
0
0
chip_id
0x5032
20530
Chip ID
id
0x5032
20530
Chip ID
reserved
0x0001
[0x0101]
1
[257]
Reserved
[3:0]
reserved
0x1
1
Reserved
[9:8]
resolution
0x0 [0x1]
0 [1]
Sensor Resolution
‘0’: PYTHON 5000
‘1’: PYTHON 2000
[11:10]
reserved
0x0
0
Reserved
chip_configuration
0x0000
0
Chip General Configuration
color
0x0
0
Colour/Monochrome Configuration
‘0’: Monochrome
‘1’: Color
[3:2]
glob_config
0x0
0
Sensor pinout configuration
[15:4]
reserved
0x000
0
Reserved
soft_reset_pll
0x0099
153
PLL Soft Reset Configuration
[3:0]
pll_soft_reset
0x9
9
PLL Reset
0x9: Soft Reset State
others: Operational
[7:4]
pll_lock_soft_reset
0x9
9
PLL Lock Detect Reset
0x9: Soft Reset State
others: Operational
soft_reset_cgen
0x0009
9
Clock Generator Soft Reset
cgen_soft_reset
0x9
9
Clock Generator Reset
0x9: Soft Reset State
others: Operational
soft_reset_analog
0x0999
2457
Analog Block Soft Reset
[3:0]
mux_soft_reset
0x9
9
Column MUX Reset
0x9: Soft Reset State
others: Operational
[7:4]
afe_soft_reset
0x9
9
AFE Reset
0x9: Soft Reset State
others: Operational
[11:8]
ser_soft_reset
0x9
9
Serializer Reset
0x9: Soft Reset State
others: Operational
power_down
0x0004
4
PLL Configuration
pwd_n
0x0
0
PLL Power Down
‘0’: Power Down,
‘1’: Operational
[15:0]
1
2
1
2
[0]
Status
Status
RW
Reset Generator [Block Offset: 8]
0
1
8
9
[3:0]
2
10
RW
RW
RW
PLL [Block Offset: 16]
0
16
[0]
www.onsemi.com
47
RW
NOIP1SN5000A
Table 27. REGISTER MAP
Address
Offset
1
Address
Bit Field
Register Name
Default
(Hex)
Default
Description
[1]
enable
0x0
0
PLL Enable
‘0’: disabled,
‘1’: enabled
[2]
bypass
0x1
1
PLL Bypass
‘0’: PLL Active,
‘1’: PLL Bypassed
reserved
0x2113
8467
Reserved
[7:0]
reserved
0x13
19
Reserved
[12:8]
reserved
0x1
1
Reserved
[14:13]
reserved
0x1
1
Reserved
config1
0x0000
0
IO Configuration
clock_in_pwd_n
0x0
0
Power down Clock Input
[9:8]
reserved
0x0
0
Reserved
[10]
reserved
0x0
0
Reserved
pll_lock
0x0000
0
PLL Lock Indication
lock
0x0
0
PLL Lock Indication
17
Type
RW
I/O [Block Offset: 20]
0
20
[0]
RW
PLL Lock Detector [Block Offset: 24]
0
24
[0]
2
3
26
reserved
0x2280
8832
Reserved
[7:0]
reserved
0x80
128
Reserved
[10:8]
reserved
0x2
2
Reserved
[14:12]
reserved
0x2
2
Reserved
reserved
0x3D2D
15661
Reserved
[7:0]
reserved
0x2D
45
Reserved
[15:8]
reserved
0x3D
61
Reserved
config0
0x0004
4
Clock Generator Configuration
[0]
enable_analog
0x0
0
Enable analogue clocks
‘0’: disabled,
‘1’: enabled
[1]
enable_log
0x0
0
Enable logic clock
‘0’: disabled,
‘1’: enabled
[2]
select_pll
0x1
1
Input Clock Selection
‘0’: Select LVDS clock input,
‘1’: Select PLL clock input
[3]
adc_mode
0x0
0
Set operation mode of CGEN block
‘0’: divide by 5 mode (10−bit mode),
‘1’: divide by 4 mode (8−bit mode)
[5:4]
mux
0x0
0
Multiplex Mode
[11:8]
reserved
0x0
0
Reserved
[14:12]
reserved
0x0
0
Reserved
config0
0x0000
0
Clock Generator Configuration
27
Status
RW
RW
Clock Generator [Block Offset: 32]
0
32
RW
General Logic [Block Offset: 34]
0
34
www.onsemi.com
48
RW
NOIP1SN5000A
Table 27. REGISTER MAP
Address
Offset
Address
Bit Field
[0]
0
38
1
39
Register Name
Default
(Hex)
Default
Description
enable
0x0
0
Logic General Enable Configuration
‘0’: Disable
‘1’: Enable
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
image_core_config0
0x0000
0
Image Core Configuration
[0]
imc_pwd_n
0x0
0
Image Core Power Down
‘0’: powered down,
‘1’: powered up
[1]
mux_pwd_n
0x0
0
Column Multiplexer Power Down
‘0’: powered down,
‘1’: powered up
[2]
colbias_enable
0x0
0
Bias Enable
‘0’: disabled
‘1’: enabled
image_core_config1
0x0B5A
2906
Image Core Configuration
[3:0]
dac_ds
0xA
10
Double Slope Reset Level
[7:4]
dac_ts
0x5
5
Triple Slope Reset Level
[10:8]
reserved
0x3
3
Reserved
[12:11]
reserved
0x1
1
Reserved
[13]
reserved
0x0
0
Reserved
[14]
reserved
0x0
0
Reserved
[15]
reserved
0x0
0
Reserved
reserved
0x0001
1
Reserved
[0]
reserved
0x1
1
Reserved
[1]
reserved
0x0
0
Reserved
[6:4]
reserved
0x0
0
Reserved
[10:8]
reserved
0x0
0
Reserved
[15:12]
reserved
0x0
0
Reserved
[15:0]
[15:0]
Type
RW
RW
Image Core [Block Offset: 40]
0
1
2
3
40
41
42
43
reserved
0x0000
0
Reserved
[0]
reserved
0x0
0
Reserved
[1]
reserved
0x0
0
Reserved
[2]
reserved
0x0
0
Reserved
[3]
reserved
0x0
0
Reserved
[6:4]
reserved
0x0
0
Reserved
[7]
reserved
0x0
0
Reserved
[15:8]
reserved
0x0
0
Reserved
power_down
0x0000
0
AFE Configuration
RW
RW
RW
RW
AFE [Block Offset: 48]
0
48
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49
RW
NOIP1SN5000A
Table 27. REGISTER MAP
Address
Offset
Address
Bit Field
[0]
Register Name
Default
(Hex)
Default
Description
pwd_n
0x0
0
Power down for AFE’s
‘0’: powered down,
‘1’: powered up
power_down
0x0000
0
Bias Power Down Configuration
pwd_n
0x0
0
Power down bandgap
‘0’: powered down,
‘1’: powered up
configuration
0x888B
34955
Bias Configuration
extres
0x1
1
External Resistor Selection
‘0’: internal resistor,
‘1’: external resistor
[3:1]
reserved
0x5
5
Reserved
[7:4]
reserved
0x8
8
Reserved
[11:8]
reserved
0x8
8
Reserved
[15:12]
reserved
0x8
8
Reserved
reserved
0x53C8
21448
Reserved
[3:0]
reserved
0x8
8
Reserved
[7:4]
reserved
0xC
12
Reserved
[14:8]
reserved
0x53
83
Reserved
reserved
0x8888
34952
Reserved
[3:0]
reserved
0x8
8
Reserved
[7:4]
reserved
0x8
8
Reserved
[11:8]
reserved
0x8
8
Reserved
[15:12]
reserved
0x8
8
Reserved
lvds_bias
0x0088
136
LVDS Bias Configuration
[3:0]
lvds_ibias
0x8
8
LVDS Ibias
[7:4]
lvds_iref
0x8
8
LVDS Iref
reserved
0x0888
2184
Reserved
[3:0]
reserved
0x8
8
Reserved
[7:4]
reserved
0x8
8
Reserved
[11:8]
reserved
0x8
8
Reserved
reserved
0x8888
34952
Reserved
[3:0]
reserved
0x8
8
Reserved
[7:4]
reserved
0x8
8
Reserved
[11:8]
reserved
0x8
8
Reserved
[15:12]
reserved
0x8
8
Reserved
reserved
0x8888
34952
Reserved
reserved
0x8888
34952
Reserved
configuration
0x2220
8736
Charge Pump Configuration
trans_pwd_n
0x0
0
PD Trans Charge Pump Enable
‘0’: disabled,
‘1’: enabled
Type
Bias [Block Offset: 64]
0
64
[0]
1
65
[0]
2
3
4
5
6
7
66
67
68
69
70
71
[15:0]
RW
RW
RW
RW
RW
RW
RW
RW
Charge Pump [Block Offset: 72]
0
72
[0]
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50
RW
NOIP1SN5000A
Table 27. REGISTER MAP
Address
Offset
Address
Default
(Hex)
Default
Bit Field
Register Name
[1]
resfd_calib_pwd_n
0x0
0
FD Charge Pump Enable
‘0’: disabled,
‘1’: enabled
Description
[2]
sel_sample_pwd_n
0x0
0
Select/Sample Charge Pump Enable
‘0’: disabled
‘1’: enabled
[6:4]
reserved
0x2
2
Reserved
[10:8]
reserved
0x2
2
Reserved
[14:12]
reserved
0x2
2
Reserved
Type
Charge Pump [Block Offset: 80]
0
1
80
reserved
0x0000
0
Reserved
[1:0]
reserved
0x0
0
Reserved
[3:2]
reserved
0x0
0
Reserved
[5:4]
reserved
0x0
0
Reserved
[7:6]
reserved
0x0
0
Reserved
[9:8]
reserved
0x0
0
Reserved
reserved
0x8881
34945
Reserved
reserved
0x8881
34945
Reserved
enable
0x0000
0
Temperature Sensor Configuration
[0]
enable
0x0
0
Temperature Diode Enable
‘0’: disabled,
‘1’: enabled
[1]
reserved
0x0
0
Reserved
[2]
reserved
0x0
0
Reserved
[3]
reserved
0x0
0
Reserved
[4]
reserved
0x0
0
Reserved
[5]
reserved
0x0
0
Reserved
offset
0x0
0
Temperature Offset (signed)
temp
0x0000
0
Temperature Sensor Status
temp
0x00
0
Temperature Readout
reserved
0x0000
0
Reserved
reserved
0x0
0
Reserved
reserved
0x0000
0
Reserved
[1:0]
reserved
0x0
0
Reserved
[6:2]
reserved
0x0
0
Reserved
[7]
reserved
0x0
0
Reserved
[9:8]
reserved
0x0
0
Reserved
[14:10]
reserved
0x0
0
Reserved
[15]
reserved
0x0
0
Reserved
reserved
0x0000
0
Reserved
81
[15:0]
RW
RW
Temperature Sensor [Block Offset: 96]
0
96
[13:8]
1
97
[7:0]
RW
Status
Temperature Sensor [Block Offset: 104]
0
104
[15:0]
1
2
105
106
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51
RW
RW
Status
NOIP1SN5000A
Table 27. REGISTER MAP
Address
Offset
Address
Bit Field
[15:0]
3
5
109
6
110
Description
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
power_down
0x0000
0
LVDS Power Down Configuration
[0]
clock_out_pwd_n
0x0
0
Power down for Clock Output.
‘0’: powered down,
‘1’: powered up
[1]
sync_pwd_n
0x0
0
Power down for Sync channel
‘0’: powered down,
‘1’: powered up
[2]
data_pwd_n
0x0
0
Power down for data channels (4 channels)
‘0’: powered down,
‘1’: powered up
trainingpattern
0x03A6
934
Data Formating − Training Pattern
trainingpattern
0x3A6
934
Training pattern sent on Data channels
during idle mode. This data is used to
perform word alignment on the LVDS
data channels.
sync_code0
0x002A
42
LVDS Power Down Configuration
frame_sync_0
0x02A
42
Frame Sync Code LSBs − Even kernels
[15:0]
[15:0]
[15:0]
7
Default
0x0000
[15:0]
108
Default
(Hex)
reserved
107
4
Register Name
111
[15:0]
Type
Status
Status
Status
Status
Status
Serializers / LVDS / IO [Block Offset: 112]
0
112
RW
Sync Words [Block Offset: 116]
4
116
[9:0]
5
117
[6:0]
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52
RW
RW
NOIP1SN5000A
Table 27. REGISTER MAP
Address
Offset
Address
6
118
Bit Field
Data Formating − BL Indication
bl_0
0x015
21
Black Pixel Identification Sync Code −
Even kernels
sync_code2
0x0035
53
Data Formating − IMG Indication
img_0
0x035
53
Valid Pixel Identification Sync Code −
Even kernels
sync_code3
0x0025
37
Data Formating − IMG Indication
ref_0
0x025
37
Reference Pixel Identification Sync
Code − Even kernels
sync_code4
0x002A
42
LVDS Power Down Configuration
frame_sync_1
0x02A
42
Frame Sync Code LSBs − Odd kernels
sync_code5
0x0015
21
Data Formating − BL Indication
bl_1
0x015
21
Black Pixel Identification Sync Code −
Odd kernels
sync_code6
0x0035
53
Data Formating − IMG Indication
img_1
0x035
53
Valid Pixel Identification Sync Code −
Odd kernels
sync_code7
0x0025
37
Data Formating − IMG Indication
ref_1
0x025
37
Reference Pixel Identification Sync
Code − Odd kernels
sync_code8
0x0059
89
Data Formating − CRC Indication
crc
0x059
89
CRC Value Identification Sync Code
sync_code9
0x03A6
934
Data Formating − TR Indication
tr
0x3A6
934
Training Value Identification Sync Code
reserved
0x02AA
682
Reserved
reserved
0x2AA
682
Reserved
blackcal
0x4008
16392
Black Calibration Configuration
[7:0]
black_offset
0x08
8
Desired black level at output
[10:8]
black_samples
0x0
0
Black pixels taken into account for black
calibration.
Total samples = 2**black_samples
[14:11]
reserved
0x8
8
Reserved
[15]
crc_seed
0x0
0
CRC Seed
‘0’: All−0
‘1’: All−1
general_configuration
0x0001
1
Black Calibration and Data Formating
Configuration
auto_blackcal_enable
0x1
1
Automatic blackcalibration is enabled
when 1, bypassed when 0
[9:1]
blackcal_offset
0x00
0
Black Calibration offset used when auto_black_cal_en = ‘0’.
[10]
blackcal_offset_dec
0x0
0
blackcal_offset is added when 0, subtracted when 1
[11]
reserved
0x0
0
Reserved
[12]
reserved
0x0
0
Reserved
119
120
121
[6:0]
10
122
[9:0]
11
123
[9:0]
12
124
[9:0]
13
125
[9:0]
14
126
[9:0]
15
Description
21
[9:0]
9
Default
0x0015
[9:0]
8
Default
(Hex)
sync_code1
[9:0]
7
Register Name
127
[9:0]
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Data Block [Block Offset: 128]
0
1
128
129
[0]
www.onsemi.com
53
RW
RW
NOIP1SN5000A
Table 27. REGISTER MAP
Address
Offset
2
8
Address
Bit Field
0
Shifts window ID indications by 4 cycles.
‘0’: 10 bit mode,
‘1’: 8 bit mode
[14]
ref_mode
0x0
0
Data contained on reference lines:
‘0’: reference pixels
‘1’: black average for the corresponding
data channel
[15]
ref_bcal_enable
0x0
0
Enable black calibration on reference
lines
‘0’: Disabled
‘1’: Enabled
reserved
0x000F
15
Reserved
[0]
reserved
0x1
1
Reserved
[1]
reserved
0x1
1
Reserved
[2]
reserved
0x1
1
Reserved
[3]
reserved
0x1
1
Reserved
[4]
reserved
0x0
0
Reserved
[8]
reserved
0x0
0
Reserved
blackcal_error0
0x0000
0
Black Calibration Status
blackcal_error[15:0]
0x0000
0
Black Calibration Error. This flag is set
when not enough black samples are
available. Black Calibration shall not be
valid. Channels 0−16
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0xFFFF
65535
Reserved
reserved
0xFFFF
65535
Reserved
test_configuration
0x0000
0
Data Formating Test Configuration
[0]
testpattern_en
0x0
0
Insert synthesized testpattern when ‘1’
[1]
inc_testpattern
0x0
0
Incrementing testpattern when ‘1’, constant testpattern when ‘0’
[2]
prbs_en
0x0
0
Insert PRBS when ‘1’
[3]
frame_testpattern
0x0
0
Frame test patterns when ‘1’, unframed
testpatterns when ‘0’
[4]
reserved
0x0
0
Reserved
reserved
0x0000
0
Reserved
0
Reserved
130
136
137
138
139
[15:0]
12
140
[15:0]
13
141
[15:0]
16
17
Description
0x0
[15:0]
11
Default
8bit_mode
[15:0]
10
Default
(Hex)
[13]
[15:0]
9
Register Name
144
145
[15:0]
reserved
www.onsemi.com
54
Type
RW
Status
Status
Status
Status
RW
RW
RW
RW
NOIP1SN5000A
Table 27. REGISTER MAP
Address
Offset
Address
18
146
19
20
21
22
Bit Field
Register Name
Default
(Hex)
Default
Description
test_configuration0
0x0100
256
Data Formating Test Configuration
[7:0]
testpattern0_lsb
0x00
0
Testpattern used on datapath #0 when
testpattern_en = ‘1’.
Note: Most significant bits are configured in register 150.
[15:8]
testpattern1_lsb
0x01
1
Testpattern used on datapath #1 when
testpattern_en = ‘1’.
Note: Most significant bits are configured in register 150.
test_configuration1
0x0302
770
Data Formating Test Configuration
[7:0]
testpattern2_lsb
0x02
2
Testpattern used on datapath #2 when
testpattern_en = ‘1’.
Note: Most significant bits are configured in register 150.
[15:8]
testpattern3_lsb
0x03
3
Testpattern used on datapath #3 when
testpattern_en = ‘1’.
Note: Most significant bits are configured in register 150.
test_configuration2
0x0504
1284
Data Formating Test Configuration
[7:0]
testpattern4_lsb
0x04
4
Testpattern used on datapath #4 when
testpattern_en = ‘1’.
Note: Most significant bits are configured in register 150.
[15:8]
testpattern5_lsb
0x05
5
Testpattern used on datapath #5 when
testpattern_en = ‘1’.
Note: Most significant bits are configured in register 150.
test_configuration3
0x0706
1798
Data Formating Test Configuration
[7:0]
testpattern6_lsb
0x06
6
Testpattern used on datapath #6 when
testpattern_en = ‘1’.
Note: Most significant bits are configured in register 150.
[15:8]
testpattern7_lsb
0x07
7
Testpattern used on datapath #7 when
testpattern_en = ‘1’.
Note: Most significant bits are configured in register 150.
test_configuration16
0x0000
0
Data Formating Test Configuration
[1:0]
testpattern0_msb
0x0
0
Testpattern used when testpattern_en =
‘1’
[3:2]
testpattern1_msb
0x0
0
Testpattern used when testpattern_en =
‘1’
[5:4]
testpattern2_msb
0x0
0
Testpattern used when testpattern_en =
‘1’
[7:6]
testpattern3_msb
0x0
0
Testpattern used when testpattern_en =
‘1’
[9:8]
testpattern4_msb
0x0
0
Testpattern used when testpattern_en =
‘1’
[11:10]
testpattern5_msb
0x0
0
Testpattern used when testpattern_en =
‘1’
[13:12]
testpattern6_msb
0x0
0
Testpattern used when testpattern_en =
‘1’
[15:14]
testpattern7_msb
0x0
0
Testpattern used when testpattern_en =
‘1’
147
148
149
150
www.onsemi.com
55
Type
RW
RW
RW
RW
RW
NOIP1SN5000A
Table 27. REGISTER MAP
Address
Offset
Address
26
154
Bit Field
[15:0]
27
155
[15:0]
Register Name
Default
(Hex)
Default
Description
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
Type
RW
RW
AEC [Block Offset: 160]
0
1
160
configuration
0x0010
16
AEC Configuration
[0]
enable
0x0
0
AEC Enable
[1]
restart_filter
0x0
0
Restart AEC filter
[2]
freeze
0x0
0
Freeze AEC filter and enforcer gains
[3]
pixel_valid
0x0
0
Use every pixel from channel when 0,
every 4th pixel when 1
[4]
amp_pri
0x1
1
Column amplifier gets higher priority
than AFE PGA in gain distribution if 1.
Vice versa if 0
intensity
0x60B8
24760
AEC Configuration
desired_intensity
0xB8
184
Target average intensity
reserved
0x018
24
Reserved
red_scale_factor
0x0080
128
Red Scale Factor
red_scale_factor
0x80
128
Red Scale Factor
3.7 unsigned
161
[9:0]
[15:10]
2
162
[9:0]
www.onsemi.com
56
RW
RW
RW
NOIP1SN5000A
Table 27. REGISTER MAP
Address
Offset
Address
3
163
Bit Field
Green1 Scale Factor
green1_scale_factor
0x80
128
Green1 Scale Factor
3.7 unsigned
green2_scale_factor
0x0080
128
Green2 Scale Factor
green2_scale_factor
0x80
128
Green2 Scale Factor
3.7 unsigned
blue_scale_factor
0x0080
128
Blue Scale Factor
blue_scale_factor
0x80
128
Blue Scale Factor
3.7 unsigned
reserved
0x03FF
1023
Reserved
reserved
0x03FF
1023
Reserved
reserved
0x0800
2048
Reserved
[1:0]
reserved
0x0
0
Reserved
[3:2]
reserved
0x0
0
Reserved
[15:4]
reserved
0x080
128
Reserved
min_exposure
0x0001
1
Minimum Exposure Time
min_exposure
0x0001
1
Minimum Exposure Time
min_gain
0x0800
2048
Minimum Gain
[1:0]
min_mux_gain
0x0
0
Minimum Column Amplifier Gain
[3:2]
min_afe_gain
0x0
0
Minimum AFE PGA Gain
[15:4]
min_digital_gain
0x080
128
Minimum Digital Gain
5.7 unsigned
max_exposure
0x03FF
1023
Maximum Exposure Time
max_exposure
0x03FF
1023
Maximum Exposure Time
164
165
166
[15:0]
7
8
167
168
[15:0]
9
10
169
170
[15:0]
11
12
13
14
Description
128
[9:0]
6
Default
0x0080
[9:0]
5
Default
(Hex)
green1_scale_factor
[9:0]
4
Register Name
171
max_gain
0x100D
4109
Maximum Gain
[1:0]
max_mux_gain
0x1
1
Maximum Column Amplifier Gain
[3:2]
max_afe_gain
0x3
3
Maximum AFE PGA Gain
[15:4]
max_digital_gain
0x100
256
Maximum Digital Gain
5.7 unsigned
reserved
0x0083
131
Reserved
[7:0]
reserved
0x083
131
Reserved
[13:8]
reserved
0x00
0
Reserved
[15:14]
reserved
0x0
0
Reserved
172
173
reserved
0x2824
10276
Reserved
[7:0]
reserved
0x024
36
Reserved
[15:8]
reserved
0x028
40
Reserved
reserved
0x2A96
10902
Reserved
[3:0]
reserved
0x6
6
Reserved
[7:4]
reserved
0x9
9
Reserved
[11:8]
reserved
0xA
10
Reserved
[15:12]
reserved
0x2
2
Reserved
174
www.onsemi.com
57
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
NOIP1SN5000A
Table 27. REGISTER MAP
Address
Offset
Address
15
175
Bit Field
[9:0]
16
176
[9:0]
Register Name
Default
(Hex)
Default
Description
reserved
0x0080
128
Reserved
reserved
0x080
128
Reserved
reserved
0x0100
256
Reserved
reserved
0x100
256
Reserved
www.onsemi.com
58
Type
RW
RW
NOIP1SN5000A
Table 27. REGISTER MAP
Address
Offset
Address
17
177
Bit Field
20
180
Reserved
reserved
0x100
256
Reserved
reserved
0x0080
128
Reserved
reserved
0x080
128
Reserved
reserved
0x00AA
170
Reserved
reserved
0x0AA
170
Reserved
reserved
0x0100
256
Reserved
reserved
0x100
256
Reserved
reserved
0x0155
341
Reserved
reserved
0x155
341
Reserved
total_pixels0
0x0000
0
AEC Status
total_pixels[15:0]
0x0000
0
Total number of pixels sampled for Average, LSB
total_pixels1
0x0000
0
AEC Status
total_pixels[23:16]
0x0
0
Total number of pixels sampled for Average, MSB
average_status
0x0000
0
ASE Status
[9:0]
average
0x000
0
AEC Average Status
[12]
avg_locked
0x0
0
AEC Average Lock Status
exposure_status
0x0000
0
ASE Status
exposure
0x0000
0
AEC Expsosure Status
gain_status
0x0000
0
ASE Status
[1:0]
mux_gain
0x0
0
AEC MUX Gain Status
[3:2]
afe_gain
0x0
0
AEC AFE Gain Status
[15:4]
digital_gain
0x000
0
AEC Digital Gain Status
5.7 unsigned
reserved
0x0000
0
Reserved
[12:0]
reserved
0x000
0
Reserved
[13]
reserved
0x0
0
Reserved
general_configuration
0x0000
0
Sequencer General Cofniguration
[0]
enable
0x0
0
Enable sequencer
‘0’: Idle,
‘1’: enabled
[1]
reserved
0x0
0
Reserved
[2]
zero_rot_enable
0x0
0
Zero ROT mode Selection.
‘0’: Non−Zero ROT,
‘1’: Zero ROT’
[3]
reserved
0x0
0
Reserved
[9:0]
[9:0]
21
181
[9:0]
24
184
[15:0]
25
185
[7:0]
26
27
186
187
[15:0]
28
29
Description
256
[9:0]
179
Default
0x0100
178
19
Default
(Hex)
reserved
[9:0]
18
Register Name
188
189
Type
RW
RW
RW
RW
RW
Status
Status
Status
Status
Status
Status
Sequencer [Block Offset: 192]
0
192
www.onsemi.com
59
RW
NOIP1SN5000A
Table 27. REGISTER MAP
Address
Offset
1
2
Address
Bit Field
Register Name
Default
(Hex)
Default
Description
[4]
triggered_mode
0x0
0
Triggered Mode Selection (Snapshot
Shutter only)
‘0’: Normal Mode,
‘1’: Triggered Mode
[5]
slave_mode
0x0
0
Master/Slave Selection (Snapshot Shutter
only)
‘0’: master,
‘1’: slave
[6]
nzrot_xsm_delay_
enable
0x0
0
Insert delay between end of ROT and
start of readout in Non−Zero ROT readout mode if ‘1’. ROT delay is defined by
register xsm_delay
[7]
subsampling
0x0
0
Subsampling mode selection
‘0’: no subsampling,
‘1’: subsampling
[8]
reserved
0x0
0
Reserved
[10]
roi_aec_enable
0x0
0
Enable windowing for AEC Statistics.
‘0’: Subsample all windows
‘1’: Subsample configured window
[13:11]
monitor_select
0x0
0
Control of the monitor pins
[14]
reserved
0x0
0
Reserved
[15]
sequence
0x0
0
Enable a sequenced readout with different parameters for even and odd
frames.
delay_configuration
0x0000
0
Sequencer delay configuration
[7:0]
reserved
0x00
0
Reserved
[15:8]
xsm_delay
0x00
0
Delay between ROT end and X−readout
(Non−Zero ROT and Zero ROT mode)
Delay between ROT end and X−readout
(Normal ROT mode with
nzrot_xsm_delay_enable = ‘1’)
integration_control
0x00E4
228
Integration Control
[0]
dual_slope_enable
0x0
0
Enable Dual Slope
[1]
triple_slope_enable
0x0
0
Enable Triple Slope
[2]
fr_mode
0x1
1
Representation of fr_length.
‘0’: reset length
‘1’: frame length
[3]
reserved
0x0
0
Reserved
[4]
int_priority
0x0
0
Integration Priority
‘0’: Frame readout has priority over integration
‘1’: Integration End has priority over
frame readout
[5]
halt_mode
0x1
1
The current frame will be completed
when the sequencer is disabled and
halt_mode = ‘1’. When ‘0’, the sensor
stops immediately when disabled, without finishing the current frame.
[6]
fss_enable
0x1
1
Generation of Frame Sequence Start
Sync code (FSS)
‘0’: No generation of FSS
‘1’: Generation of FSS
193
194
www.onsemi.com
60
Type
RW
RW
NOIP1SN5000A
Table 27. REGISTER MAP
Address
Offset
Address
Bit Field
Register Name
Default
(Hex)
Default
Description
[7]
fse_enable
0x1
1
Generation of Frame Sequence End
Sync code (FSE)
‘0’: No generation of FSE
‘1’: Generation of FSE
[8]
reverse_y
0x0
0
Reverse readout
‘0’: bottom to top readout
‘1’: top to bottom readout
[9]
reserved
0x0
0
Reserved
[11:10]
subsampling_mode
0x0
0
Subsampling mode
0x0: Subsampling in x and y (VITA
compatible)
0x1: Subsampling in x, not y
0x2: Subsampling in y, not x
0x3: Subsampling in x an y
[13:12]
reserved
0x0
0
Reserved
[14]
reserved
0x0
0
Reserved
[15]
reserved
0x0
0
Reserved
www.onsemi.com
61
Type
NOIP1SN5000A
Table 27. REGISTER MAP
Address
Offset
Address
3
195
Bit Field
[15:0]
4
196
[15:0]
5
6
197
1
Active ROI Selection
[0] Roi0 Active
[1] Roi1 Active
...
[15] Roi15 Active
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
Number of black lines. Minimum is 1.
Range 1−255
[12:8]
gate_first_line
0x1
1
Blank out first lines
0: no blank
1−31: blank 1−31 lines
reserved
0x0000
0
Reserved
reserved
0x000
0
Reserved
mult_timer0
0x0001
1
Exposure/Frame Rate Configuration
mult_timer0
0x0001
1
Mult Timer
Defines granularity (unit = 1/PLL clock)
of
exposure and reset_length
fr_length0
0x0000
0
Exposure/Frame Rate Configuration
fr_length0
0x0000
0
Frame/Reset length
Reset length when fr_mode = ‘0’,
Frame Length when fr_mode = ‘1’
Granularity defined by mult_timer
exposure0
0x0000
0
Exposure/Frame Rate Configuration
exposure0
0x0000
0
Exposure Time
Granularity defined by mult_timer
exposure_ds0
0x0000
0
Exposure/Frame Rate Configuration
exposure_ds0
0x0000
0
Exposure Time (Dual Slope)
Granularity defined by mult_timer
exposure_ts0
0x0000
0
Exposure/Frame Rate Configuration
exposure_ts0
0x0000
0
Exposure Time (Triple Slope)
Granularity defined by mult_timer
gain_configuration0
0x01E3
483
Gain Configuration
[4:0]
mux_gainsw0
0x03
3
Column Gain Setting
[12:5]
afe_gain0
0xF
15
AFE Programmable Gain Setting
gain_lat_comp
0x0
0
Postpone gain update by 1 frame when
‘1’ to compensate for exposure time updates
latency.
Gain is applied at start of next frame if
‘0’
digital_gain_
configuration0
0x0080
128
Gain Configuration
db_gain0
0x080
128
Digital Gain
sync_configuration
0x037F
895
Synchronization Configuration
198
199
200
201
202
203
204
205
206
0x01
Black Line Configuration
[11:0]
14
roi_active0
2
[13]
13
Active ROI Selection
258
[15:0]
12
1
0x02
[15:0]
11
0x0001
0x0102
[15:0]
10
Description
roi_active0_0
black_lines
[15:0]
9
Default
black_lines
[15:0]
8
Default
(Hex)
[7:0]
[11:0]
7
Register Name
www.onsemi.com
62
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
NOIP1SN5000A
Table 27. REGISTER MAP
Address
Offset
15
Address
[0]
sync_rs_x_length
0x1
1
Update of rs_x_length will not be
sync’ed at start of frame when ‘0’
[1]
sync_black_lines
0x1
1
Update of black_lines will not be
sync’ed at start of frame when ‘0’
[2]
sync_dummy_lines
0x1
1
Update of dummy_lines will not be
sync’ed at start of frame when ‘0’
[3]
sync_exposure
0x1
1
Update of exposure will not be sync’ed
at start of frame when ‘0’
[4]
sync_gain
0x1
1
Update of gain settings (gain_sw,
afe_gain) will not be sync’ed at start of
frame when ‘0’
[5]
sync_roi
0x1
1
Update of roi updates (active_roi) will
not be sync’ed at start of frame when ‘0’
[6]
sync_ref_lines
0x1
1
Update of ref_lines will not be sync’ed
at start of frame when ‘0’
[8]
blank_roi_switch
0x1
1
Blank first frame after ROI switching
[9]
blank_
subsampling_ss
0x1
1
Blank first frame after subsampling
mode switching
‘0’: No blanking
‘1’: Blanking
[10]
exposure_sync_
mode
0x0
0
When ‘0’, exposure configurations are
sync’ed at the start of FOT. When ‘1’,
exposure configurations sync is disabled (continuously syncing). This mode
is only relevant for
Triggered snapshot − master mode,
where the exposure configurations are
sync’ed at the start of exposure rather
than the start of FOT. For all other
modes it should be set to ‘0’.
Note: Sync is still postponed if
sync_exposure=‘0’.
ref_lines
0x0000
0
Reference Line Configuration
ref_lines
0x00
0
Number of Reference Lines
0−255
roi_active0_1
0x0001
1
Active ROI Selection
roi_active1
0x01
1
Active ROI Selection
[0] Roi0 Active
[1] Roi1 Active
...
[15] Roi15 Active
x_resolution
0x00A2
[0x007C]
162
[124]
Sequencer Status
x_resolution
0x000A2
[0x007C]
162
[124]
Sensor x resolution
y_resolution
0x0800
[0x04F0]
2048
[1264]
Sequencer Status
y_resolution
0x0800
[0x04F0]
2048
[1264]
Sensor y resolution
mult_timer_status
0x0000
0
Sequencer Status
mult_timer
0x0000
0
Mult Timer Status (Master Snapshot
Shutter only)
207
228
[7:0]
48
240
[7:0]
49
241
[12:0]
50
Default
Register Name
[7:0]
36
Default
(Hex)
Bit Field
242
[15:0]
www.onsemi.com
63
Description
Type
RW
RW
Status
Status
Status
NOIP1SN5000A
Table 27. REGISTER MAP
Address
Offset
Address
51
243
Bit Field
Sequencer Status
reset_length
0x0000
0
Current Reset Length (not in Slave
mode)
exposure_status
0x0000
0
Sequencer Status
exposure
0x0000
0
Current Exposure Time (not in Slave
mode)
exposure_ds_status
0x0000
0
Sequencer Status
exposure_ds
0x0000
0
Current Exposure Time (not in Slave
mode)
exposure_ts_status
0x0000
0
Sequencer Status
exposure_ts
0x0000
0
Current Exposure Time (not in Slave
mode)
gain_status
0x0000
0
Sequencer Status
[4:0]
mux_gainsw
0x00
0
Current Column Gain Setting
[12:5]
afe_gain
0x00
0
Current AFE Programmable Gain
digital_gain_status
0x0000
0
Sequencer Status
db_gain
0x000
0
Digital Gain
[12]
dual_slope
0x0
0
Dual Slope Enabled
[13]
triple_slope
0x0
0
Triple Slope Enabled
roi_aec_
configuration0
0x0000
0
AEC ROI Configuration
[7:0]
x_start
0x00
0
AEC ROI X Start Configuration (used
for AEC statistics when roi_aec_enable=‘1’)
[15:8]
x_end
0x00
0
AEC ROI X End Configuration (used for
AEC statistics when roi_aec_enable=‘1’)
roi_aec_
configuration1
0x0000
0
AEC ROI Configuration
y_start
0x0000
0
AEC ROI Y Start Configuration (used
for AEC statistics when roi_aec_enable=‘1’)
roi_aec_
configuration2
0x0000
0
AEC ROI Configuration
y_end
0x0000
0
AEC ROI Y End Configuration (used for
AEC statistics when roi_aec_enable=‘1’)
roi0_configuration0
0xA100
41216
ROI Configuration
[7:0]
x_start
0x00
0
X Start Configuration
[15:8]
x_end
0xA1
161
X End Configuration
roi0_configuration1
0x0000
0
ROI Configuration
244
245
246
[15:0]
55
56
247
248
[11:0]
61
62
253
254
[12:0]
63
Description
0
[15:0]
54
Default
0x0000
[15:0]
53
Default
(Hex)
reset_length_status
[15:0]
52
Register Name
255
[12:0]
Type
Status
Status
Status
Status
Status
Status
RW
RW
RW
Sequencer ROI [Block Offset: 256]
0
1
256
257
www.onsemi.com
64
RW
RW
NOIP1SN5000A
Table 27. REGISTER MAP
Address
Offset
Address
Bit Field
[12:0]
2
4
Y Start Configuration
roi0_configuration2
0x07FF
2047
ROI Configuration
y_end
0x7FF
2047
Y End Configuration
roi1_configuration0
0xA100
41216
ROI Configuration
[7:0]
x_start
0x00
0
X Start Configuration
[15:8]
x_end
0xA1
161
X End Configuration
roi1_configuration1
0x0000
0
ROI Configuration
y_start
0x0000
0
Y Start Configuration
roi1_configuration2
0x07FF
2047
ROI Configuration
y_end
0x7FF
2047
Y End Configuration
roi2_configuration0
0xA100
41216
ROI Configuration
[7:0]
x_start
0x00
0
X Start Configuration
[15:8]
x_end
0xA1
161
X End Configuration
roi2_configuration1
0x0000
0
ROI Configuration
y_start
0x0000
0
Y Start Configuration
roi2_configuration2
0x07FF
2047
ROI Configuration
y_end
0x7FF
2047
Y End Configuration
roi3_configuration0
0xA100
41216
ROI Configuration
[7:0]
x_start
0x00
0
X Start Configuration
[15:8]
x_end
0xA1
161
X End Configuration
roi3_configuration1
0x0000
0
ROI Configuration
y_start
0x0000
0
Y Start Configuration
roi3_configuration2
0x07FF
2047
ROI Configuration
y_end
0x7FF
2047
Y End Configuration
roi4_configuration0
0xA100
41216
ROI Configuration
[7:0]
x_start
0x00
0
X Start Configuration
[15:8]
x_end
0xA1
161
X End Configuration
roi4_configuration1
0x0000
0
ROI Configuration
y_start
0x0000
0
Y Start Configuration
roi4_configuration2
0x07FF
2047
ROI Configuration
y_end
0x7FF
2047
Y End Configuration
roi5_configuration0
0xA100
41216
ROI Configuration
260
[12:0]
6
262
[12:0]
7
263
8
264
9
265
[12:0]
[12:0]
10
266
11
267
12
268
[12:0]
[12:0]
13
269
14
270
[12:0]
[12:0]
15
271
Description
0
259
261
Default
0x0000
258
5
Default
(Hex)
y_start
[12:0]
3
Register Name
www.onsemi.com
65
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
NOIP1SN5000A
Table 27. REGISTER MAP
Address
Offset
16
Address
Bit Field
19
0
X Start Configuration
[15:8]
x_end
0xA1
161
X End Configuration
roi5_configuration1
0x0000
0
ROI Configuration
y_start
0x0000
0
Y Start Configuration
roi5_configuration2
0x07FF
2047
ROI Configuration
y_end
0x7FF
2047
Y End Configuration
roi6_configuration0
0xA100
41216
ROI Configuration
[7:0]
x_start
0x00
0
X Start Configuration
[15:8]
x_end
0xA1
161
X End Configuration
roi6_configuration1
0x0000
0
ROI Configuration
y_start
0x0000
0
Y Start Configuration
roi6_configuration2
0x07FF
2047
ROI Configuration
y_end
0x7FF
2047
Y End Configuration
roi7_configuration0
0xA100
41216
ROI Configuration
[7:0]
x_start
0x00
0
X Start Configuration
[15:8]
x_end
0xA1
161
X End Configuration
roi7_configuration1
0x0000
0
ROI Configuration
y_start
0x0000
0
Y Start Configuration
roi7_configuration2
0x07FF
2047
ROI Configuration
y_end
0x7FF
2047
Y End Configuration
roi8_configuration0
0xA100
41216
ROI Configuration
[7:0]
x_start
0x00
0
X Start Configuration
[15:8]
x_end
0xA1
161
X End Configuration
roi8_configuration1
0x0000
0
ROI Configuration
y_start
0x0000
0
Y Start Configuration
roi8_configuration2
0x07FF
2047
ROI Configuration
y_end
0x7FF
2047
Y End Configuration
roi9_configuration0
0xA100
41216
ROI Configuration
[7:0]
x_start
0x00
0
X Start Configuration
[15:8]
x_end
0xA1
161
X End Configuration
roi9_configuration1
0x0000
0
ROI Configuration
y_start
0x0000
0
Y Start Configuration
272
273
274
275
276
[12:0]
21
22
277
278
[12:0]
23
279
[12:0]
24
25
280
281
[12:0]
26
282
27
283
[12:0]
28
Description
0x00
[12:0]
20
Default
x_start
[12:0]
18
Default
(Hex)
[7:0]
[12:0]
17
Register Name
284
[12:0]
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66
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
NOIP1SN5000A
Table 27. REGISTER MAP
Address
Offset
Address
29
285
30
286
Bit Field
Default
(Hex)
Default
Description
roi9_configuration2
0x07FF
2047
ROI Configuration
y_end
0x7FF
2047
Y End Configuration
roi10_configuration0
0xA100
41216
ROI Configuration
[7:0]
x_start
0x00
0
X Start Configuration
[15:8]
x_end
0xA1
161
X End Configuration
roi10_configuration1
0x0000
0
ROI Configuration
y_start
0x0000
0
Y Start Configuration
[12:0]
31
Register Name
287
[12:0]
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67
Type
RW
RW
RW
NOIP1SN5000A
Table 27. REGISTER MAP
Address
Offset
Address
32
288
33
289
Bit Field
290
35
291
ROI Configuration
y_end
0x7FF
2047
Y End Configuration
roi11_configuration0
0xA100
41216
ROI Configuration
[7:0]
x_start
0x00
0
X Start Configuration
[15:8]
x_end
0xA1
161
X End Configuration
roi11_configuration1
0x0000
0
ROI Configuration
y_start
0x0000
0
Y Start Configuration
roi11_configuration2
0x07FF
2047
ROI Configuration
y_end
0x7FF
2047
Y End Configuration
roi12_configuration0
0xA100
41216
ROI Configuration
[7:0]
x_start
0x00
0
X Start Configuration
[15:8]
x_end
0xA1
161
X End Configuration
roi12_configuration1
0x0000
0
ROI Configuration
y_start
0x0000
0
Y Start Configuration
roi12_configuration2
0x07FF
2047
ROI Configuration
y_end
0x7FF
2047
Y End Configuration
roi13_configuration0
0xA100
41216
ROI Configuration
[7:0]
x_start
0x00
0
X Start Configuration
[15:8]
x_end
0xA1
161
X End Configuration
roi13_configuration1
0x0000
0
ROI Configuration
y_start
0x0000
0
Y Start Configuration
roi13_configuration2
0x07FF
2047
ROI Configuration
y_end
0x7FF
2047
Y End Configuration
roi14_configuration0
0xA100
41216
ROI Configuration
[7:0]
x_start
0x00
0
X Start Configuration
[15:8]
x_end
0xA1
161
X End Configuration
roi14_configuration1
0x0000
0
ROI Configuration
y_start
0x0000
0
Y Start Configuration
roi14_configuration2
0x07FF
2047
ROI Configuration
y_end
0x7FF
2047
Y End Configuration
roi15_configuration0
0xA100
41216
ROI Configuration
x_start
0x00
0
X Start Configuration
292
293
[12:0]
38
294
[12:0]
39
40
295
296
[12:0]
41
297
[12:0]
42
43
298
299
[12:0]
44
300
[12:0]
45
Description
2047
[12:0]
37
Default
0x07FF
[12:0]
36
Default
(Hex)
roi10_configuration2
[12:0]
34
Register Name
301
[7:0]
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68
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
NOIP1SN5000A
Table 27. REGISTER MAP
Address
Offset
Address
Bit Field
[15:8]
46
302
[12:0]
47
303
[12:0]
Register Name
Default
(Hex)
Default
Description
x_end
0xA1
161
X End Configuration
roi15_configuration1
0x0000
0
ROI Configuration
y_start
0x0000
0
Y Start Configuration
roi15_configuration2
0x07FF
2047
ROI Configuration
y_end
0x7FF
2047
Y End Configuration
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69
Type
RW
RW
NOIP1SN5000A
Selectable Pin−Out
Table 28. ALTERNATIVE PIN OUT OPTIONS
The PYTHON sensor has a built−in possibility to route
some of the internal signals to different pads at the side of the
chip.
The pin−out is controlled by glob_config in the
chip_configuration register, located at address 2. The two
possible pin outs in the 84 pin package are listed in Table 28.
By default, 0x3 setting is selected.
glob_config =
0x3
84−pin
LCC
128−pad
LGA
doutn1
clock_outn
8
D4
doutp1
clock_outp
9
D5
clock_outn
doutn1
14
G4
clock_outp
doutp1
15
G5
syncn
doutn6
29
H4
syncp
doutp6
30
H5
doutn6
syncn
35
L4
doutp6
syncp
36
L5
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70
glob_config =
0x1
NOIP1SN5000A
Pin List
TIA/EIA−644−A Standard and the CMOS I/Os have 3.3 V
signal level. Table 29 and Table 30 show the pin list for the
LCC−84 and LGA−128 packages respectively.
The PYTHON 2000 and PYTHON 5000 image sensors
are available in LVDS output configuration (P1−SN/SE/FN,
P3−SN/SE). The LVDS I/Os comply to the
Table 29. PIN LIST FOR P1−SN/SE/FN, P3−SN/SE FOR LCC−84 PINS
Package Pin
No.
Pin Name
I/O Type
1
vdd_33
Supply
2
nc
3
mosi
CMOS
Input
SPI Master Out − Slave In
4
miso
CMOS
Output
SPI Master In − Slave Out
5
sck
CMOS
Input
6
gnd_18
Supply
7
vdd_18
Supply
8
doutn1
LVDS
Output
LVDS Data Output Channel #1 (Negative), Not connected for
P3−SN/SE
9
doutp1
LVDS
Output
LVDS Data Output Channel #1 (Positive), Not connected for
P3−SN/SE
10
doutn0
LVDS
Output
LVDS Data Output Channel #0 (Negative)
11
doutp0
LVDS
Output
LVDS Data Output Channel #0 (Positive)
12
nc
For test purposes only. Do not connect
13
nc
For test purposes only. Do not connect
14
clock_outn
LVDS
Output
LVDS Clock Output (Negative)
15
clock_outp
LVDS
Output
LVDS Clock Output (Positive)
16
doutn2
LVDS
Output
LVDS Data Output Channel #2 (Negative)
17
doutp2
LVDS
Output
LVDS Data Output Channel #2 (Positive)
18
doutn3
LVDS
Output
LVDS Data Output Channel #3 (Negative), Not connected for
P3−SN/SE
19
doutp3
LVDS
Output
LVDS Data Output Channel #3 (Positive), Not connected for
P3−SN/SE
20
gnd_18
Supply
Supply 1.8 V Ground
21
vdd_18
Supply
Supply 1.8 V Supply
22
nc
Direction
Description
3.3 V Supply
For test purposes only. Do not connect
SPI Input Clock
1.8 V Ground
1.8 V Supply
For test purposes only. Do not connect
23
vdd_33
Supply
Supply 3.3 V Supply
24
gnd_33
Supply
Supply 3.3 V Ground
25
doutn4
LVDS
Output
LVDS Data Output Channel #4 (Negative)
26
doutp4
LVDS
Output
LVDS Data Output Channel #4 (Positive)
27
doutn5
LVDS
Output
LVDS Data Output Channel #5 (Negative), Not connected for
P3−SN/SE
28
doutp5
LVDS
Output
LVDS Data Output Channel #5 (Positive), Not connected for
P3−SN/SE
29
syncn
LVDS
Output
LVDS Sync Channel Output (Negative)
30
syncp
LVDS
Output
LVDS Sync Channel Output (Positive)
31
nc
For test purposes only. Do not connect
32
nc
For test purposes only. Do not connect
33
doutn7
LVDS
Output
LVDS Data Output Channel #7 (Negative), Not connected for
P3−SN/SE
34
doutp7
LVDS
Output
LVDS Data Output Channel #7 (Positive), Not connected for
P3−SN/SE
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71
NOIP1SN5000A
Table 29. PIN LIST FOR P1−SN/SE/FN, P3−SN/SE FOR LCC−84 PINS
Package Pin
No.
Pin Name
I/O Type
Direction
35
doutn6
LVDS
Output
LVDS Data Output Channel #6 (Negative)
36
doutp6
LVDS
Output
LVDS Data Output Channel #6 (Positive)
37
vdd_33
Supply
Supply 3.3 V Supply
38
gnd_33
Supply
Supply 3.3 V Ground
39
gnd_18
Supply
Supply 1.8 V Ground
40
vdd_18
Supply
41
lvds_clock_in
n
LVDS
Input
LVDS Clock Input (Negative)
42
lvds_clock_in
p
LVDS
Input
LVDS Clock Input (Positive)
43
nc
44
clk_pll
CMOS
45
vdd_18
Supply
1.8 V Supply
46
gnd_18
Supply
Supply 1.8 V Ground
47
ibias_master
Analog
Master Bias Reference
Description
Supply 1.8 V Supply
For test purposes only. Do not connect
Input
Reference Clock Input for PLL
48
nc
49
vdd_33
Supply
For test purposes only. Do not connect
3.3 V Supply
50
gnd_33
Supply
3.3 V Ground
51
nc
For test purposes only. Do not connect
52
nc
For test purposes only. Do not connect
53
nc
For test purposes only. Do not connect
54
nc
For test purposes only. Do not connect
55
nc
For test purposes only. Do not connect
56
nc
For test purposes only. Do not connect
57
vdd_pix
Supply
Pixel Array Supply
58
gnd_colpc
Supply
Pixel Array Ground
59
nc
For test purposes only. Do not connect
60
vdd_pix
Supply
Pixel Array Supply
61
gnd_colpc
Supply
Pixel Array Ground
62
gnd_33
Supply
3.3 V Ground
63
vdd_33
Supply
3.3 V Supply
64
nc
65
gnd_colpc
Supply
Pixel Array Ground
66
vdd_pix
Supply
Pixel Array Supply
67
gnd_colpc
Supply
Pixel Array Ground
68
vdd_pix
Supply
Pixel Array Supply
For test purposes only. Do not connect
69
nc
70
trigger0
CMOS
Input
For test purposes only. Do not connect
Trigger Input #0
71
trigger1
CMOS
Input
Trigger Input #1
72
nc
For test purposes only. Do not connect
73
nc
For test purposes only. Do not connect
74
nc
For test purposes only. Do not connect
75
nc
For test purposes only. Do not connect
76
nc
For test purposes only. Do not connect
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72
NOIP1SN5000A
Table 29. PIN LIST FOR P1−SN/SE/FN, P3−SN/SE FOR LCC−84 PINS
Package Pin
No.
Pin Name
I/O Type
Direction
77
trigger2
CMOS
Input
78
monitor0
CMOS
Output
79
vdd_33
Supply
Supply 3.3 V supply
80
gnd_33
Supply
Supply 3.3 V Ground
81
monitor1
CMOS
Output
82
reset_n
CMOS
Input
Sensor Reset (Active Low)
83
ss_n
CMOS
Input
SPI Slave Select.
84
gnd_33
Supply
Description
Trigger Input #2
Monitor Output #0
Monitor Output #1
Supply 3.3 V Ground
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73
NOIP1SN5000A
Table 30. PIN LIST FOR P1−SN/SE/FN, P3−SN/SE FOR LGA−128 PADS
Package Pad
No
Pin Name
I/O Type
Direction
Description
A1
gnd
Supply
Supply Ground
A2
gnd
Supply
Supply Ground
A3
nc
For test purposes only. Do not connect
A4
nc
For test purposes only. Do not connect
A5
nc
For test purposes only. Do not connect
A6
nc
For test purposes only. Do not connect
A7
nc
For test purposes only. Do not connect
A8
nc
For test purposes only. Do not connect
A9
nc
For test purposes only. Do not connect
A10
nc
For test purposes only. Do not connect
A11
nc
For test purposes only. Do not connect
A12
nc
For test purposes only. Do not connect
A13
gnd
Supply
Supply Ground
A14
gnd
Supply
Supply Ground
B1
gnd
Supply
Supply Ground
B2
gnd
Supply
Supply Ground
B3
gnd
Supply
Supply Ground
B4
gnd
Supply
Supply Ground
B5
gnd
Supply
Supply Ground
B6
gnd
Supply
Supply Ground
B7
gnd
Supply
Supply Ground
B8
gnd
Supply
Supply Ground
B9
gnd
Supply
Supply Ground
B10
gnd
Supply
Supply Ground
B11
gnd
Supply
Supply Ground
B12
gnd
Supply
Supply Ground
B13
gnd
Supply
Supply Ground
B14
gnd
Supply
Supply Ground
C1
nc
C2
gnd
Supply
Supply Ground
C3
gnd
Supply
Supply Ground
C4
doutn0
LVDS
Output
LVDS Data Output Channel #0 (Negative)
C5
doutp0
LVDS
Output
LVDS Data Output Channel #0 (Positive)
C6
sck
CMOS
Input
SPI Input Clock
C7
mosi
CMOS
Input
SPI Master Out − Slave In
C8
ss_n
CMOS
Input
SPI Slave Select.
C9
reset_n
CMOS
Input
Sensor Reset (Active Low)
C10
monitor1
CMOS
Output
Monitor Output #1
C11
monitor0
CMOS
Output
Monitor Output #0
C12
gnd
Supply
Supply Ground
C13
gnd
Supply
Supply Ground
For test purposes only. Do not connect
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74
NOIP1SN5000A
Table 30. PIN LIST FOR P1−SN/SE/FN, P3−SN/SE FOR LGA−128 PADS
Package Pad
No
Pin Name
I/O Type
Direction
Description
C14
nc
For test purposes only. Do not connect
D1
nc
For test purposes only. Do not connect
D2
gnd
Supply
D3
vdd_18
Supply
D4
doutn1
LVDS
Output
LVDS Data Output Channel #1 (Negative), Not connected for
P3−SN/SE
D5
doutp1
LVDS
Output
LVDS Data Output Channel #1 (Positive), Not connected for
P3−SN/SE
D6
vdd_18
Supply
D7
miso
CMOS
D8
gnd
Supply
Supply Ground
D9
vdd_33
Supply
Supply 3.3 V Supply
D10
vdd_33
Supply
Supply 3.3 V Supply
D11
trigger2
CMOS
Input
Trigger Input #2
D12
trigger1
CMOS
Input
Trigger Input #1
D13
gnd
Supply
D14
nc
For test purposes only. Do not connect
E1
nc
For test purposes only. Do not connect
E2
gnd
Supply
Supply Ground
E3
vdd_18
Supply
Supply 1.8 V Supply
E4
doutn2
LVDS
Output
LVDS Data Output Channel #2 (Negative)
E5
doutp2
LVDS
Output
LVDS Data Output Channel #2 (Positive)
E6
gnd
Supply
Supply Ground
E7
gnd
Supply
Supply Ground
E8
gnd
Supply
Supply Ground
E9
gnd
Supply
Supply Ground
E10
gnd
Supply
Supply Ground
E11
gnd
Supply
Supply Ground
E12
trigger0
CMOS
E13
gnd
Supply
E14
nc
For test purposes only. Do not connect
F1
nc
For test purposes only. Do not connect
F2
gnd
Supply
Supply Ground
F3
vdd_18
Supply
Supply 1.8 V Supply
F4
doutn3
LVDS
Output
LVDS Data Output Channel #3 (Negative), Not connected for
P3−SN/SE
F5
doutp3
LVDS
Output
LVDS Data Output Channel #3 (Positive), Not connected for
P3−SN/SE
F6
nc
For test purposes only. Do not connect
F7
nc
For test purposes only. Do not connect
F8
nc
For test purposes only. Do not connect
F9
nc
For test purposes only. Do not connect
Supply Ground
Supply 1.8 V Supply
Supply 1.8 V Supply
Output
SPI Master In − Slave Out
Supply Ground
Input
Trigger Input #0
Supply Ground
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75
NOIP1SN5000A
Table 30. PIN LIST FOR P1−SN/SE/FN, P3−SN/SE FOR LGA−128 PADS
Package Pad
No
Pin Name
I/O Type
Direction
Description
F10
gnd
Supply
Supply Ground
F11
gnd_colpc
Supply
pc Supply Pixel Array Ground
F12
vdd_pix
Supply
Supply Pixel Array Supply
F13
gnd
Supply
Supply Ground
F14
nc
For test purposes only. Do not connect
G1
nc
For test purposes only. Do not connect
G2
gnd
Supply
Supply Ground
G3
vdd_18
Supply
Supply 1.8 V Supply
G4
clock_outn
LVDS
Output
LVDS Clock Output (Negative)
G5
clock_outp
LVDS
Output
LVDS Clock Output (Positive)
G6
nc
For test purposes only. Do not connect
G7
nc
For test purposes only. Do not connect
G8
nc
For test purposes only. Do not connect
G9
nc
For test purposes only. Do not connect
G10
gnd
Supply
Supply Ground
G11
gnd_colpc
Supply
pc Supply Pixel Array Ground
G12
vdd_pix
Supply
Supply Pixel Array Supply
G13
gnd
Supply
Supply Ground
G14
nc
For test purposes only. Do not connect
H1
nc
For test purposes only. Do not connect
H2
gnd
Supply
H3
vdd_33
Supply
H4
syncn
LVDS
Output
LVDS Sync Channel Output (Negative)
H5
syncp
LVDS
Output
LVDS Sync Channel Output (Positive)
H6
nc
For test purposes only. Do not connect
H7
nc
For test purposes only. Do not connect
H8
nc
For test purposes only. Do not connect
Supply Ground
Supply 3.3 V Supply
H9
nc
H10
gnd
Supply
For test purposes only. Do not connect
Supply Ground
H11
gnd
Supply
Supply Ground
H12
vdd_33
Supply
Supply 3.3 V Supply
H13
gnd
Supply
Supply Ground
H14
nc
For test purposes only. Do not connect
J1
nc
J2
gnd
Supply
For test purposes only. Do not connect
Supply Ground
J3
vdd_18
Supply
Supply 1.8 V Supply
J4
doutn4
LVDS
Output
LVDS Data Output Channel #4 (Negative)
J5
doutp4
LVDS
Output
LVDS Data Output Channel #4 (Positive)
J6
nc
For test purposes only. Do not connect
J7
nc
For test purposes only. Do not connect
J8
nc
For test purposes only. Do not connect
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76
NOIP1SN5000A
Table 30. PIN LIST FOR P1−SN/SE/FN, P3−SN/SE FOR LGA−128 PADS
Package Pad
No
Pin Name
I/O Type
Direction
Description
J9
nc
J10
gnd
Supply
Supply Ground
J11
gnd_colpc
Supply
pc Supply Pixel Array Ground
J12
vdd_pix
Supply
Supply Pixel Array Supply
J13
gnd
Supply
Supply Ground
J14
nc
For test purposes only. Do not connect
K1
nc
For test purposes only. Do not connect
K2
gnd
Supply
Supply Ground
K3
vdd_18
Supply
Supply 1.8 V Supply
K4
doutn5
LVDS
Output
LVDS Data Output Channel #5 (Negative), Not connected for
P3−SN/SE
K5
doutp5
LVDS
Output
LVDS Data Output Channel #5 (Positive), Not connected for
P3−SN/SE
K6
gnd
Supply
Supply Ground
K7
gnd
Supply
Supply Ground
K8
gnd
Supply
Supply Ground
K9
gnd
Supply
Supply Ground
K10
gnd
Supply
Supply Ground
K11
gnd_colpc
Supply
pc Supply Pixel Array Ground
K12
vdd_pix
Supply
Supply Pixel Array Supply
K13
gnd
Supply
Supply Ground
K14
nc
For test purposes only. Do not connect
For test purposes only. Do not connect
L1
nc
L2
gnd
Supply
For test purposes only. Do not connect
Supply Ground
L3
vdd_18
Supply
Supply 1.8 V Supply
L4
doutn6
LVDS
Output
LVDS Data Output Channel #6 (Negative)
L5
doutp6
LVDS
Output
LVDS Data Output Channel #6 (Positive)
L6
vdd_18
Supply
L7
lvds_clock_in
p
LVDS
L8
gnd
Supply
Supply Ground
Supply 1.8 V Supply
Input
LVDS Clock Input (Positive)
L9
gnd
Supply
Supply Ground
L10
gnd
Supply
Supply Ground
L11
vdd_33
Supply
Supply 3.3 V Supply
L12
gnd
Supply
Supply Ground
L13
gnd
Supply
Supply Ground
L14
nc
For test purposes only. Do not connect
M1
nc
M2
gnd
Supply
For test purposes only. Do not connect
Supply Ground
M3
gnd
Supply
Supply Ground
M4
doutn7
LVDS
Output
LVDS Data Output Channel #7 (Negative), Not connected for
P3−SN/SE
www.onsemi.com
77
NOIP1SN5000A
Table 30. PIN LIST FOR P1−SN/SE/FN, P3−SN/SE FOR LGA−128 PADS
Package Pad
No
Pin Name
I/O Type
Direction
Description
M5
doutp7
LVDS
Output
M6
vdd_33
Supply
M7
lvds_clock_in
n
LVDS
Input
LVDS Clock Input (Negative)
M8
clk_pll
CMOS
Input
Reference Clock Input for PLL
M9
vdd_18
Supply
Supply 1.8 V Supply
M10
gnd
Supply
Supply Ground
M11
ibias_master
Analog
Master Analog Master Bias Reference
M12
gnd
Supply
Supply Ground
M13
gnd
Supply
Supply Ground
M14
nc
N1
gnd
Supply
Supply Ground
N2
gnd
Supply
Supply Ground
N3
gnd
Supply
Supply Ground
N4
gnd
Supply
Supply Ground
N5
gnd
Supply
Supply Ground
N6
gnd
Supply
Supply Ground
N7
gnd
Supply
Supply Ground
N8
gnd
Supply
Supply Ground
N9
gnd
Supply
Supply Ground
N10
gnd
Supply
Supply Ground
LVDS Data Output Channel #7 (Positive), Not connected for
P3−SN/SE
Supply 3.3 V Supply
For test purposes only. Do not connect
N11
gnd
Supply
Supply Ground
N12
gnd
Supply
Supply Ground
N13
gnd
Supply
Supply Ground
N14
gnd
Supply
Supply Ground
P1
gnd
Supply
Supply Ground
P2
gnd
Supply
Supply Ground
P3
nc
For test purposes only. Do not connect
P4
nc
For test purposes only. Do not connect
P5
nc
For test purposes only. Do not connect
P6
nc
For test purposes only. Do not connect
P7
nc
For test purposes only. Do not connect
P8
nc
For test purposes only. Do not connect
P9
nc
For test purposes only. Do not connect
P10
nc
For test purposes only. Do not connect
P11
nc
For test purposes only. Do not connect
P12
nc
For test purposes only. Do not connect
P13
gnd
Supply
Supply Ground
P14
gnd
Supply
Supply Ground
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78
NOIP1SN5000A
Table 31. MECHANICAL SPECIFICATION FOR LCC−84 PINS AND LGA−128 PADS
Parameter
Die
(with Pin 1 to the left
center)
Glass Lid Specification
Description
Min
Die thickness
Die Size
Typ
Max
Units
725
mm
14.7 x 14.25
mm2
Die center, X offset to the center of package
−50
0
50
mm
Die center, Y offset to the center of the package
−50
0
50
mm
Die position, tilt to the Die Attach Plane
−1
0
1
deg
Die rotation accuracy (referenced to die scribe and lead
fingers on package on all four sides)
−1
0
1
deg
Optical center referenced from die/package center (X−dir)
PYTHON 5 MP
−231.38
mm
Optical center referenced from die/package center (X−dir)
PYTHON 2 MP
−154.58
mm
Optical center referenced from die/package center (Y−dir)
PYTHON 5 MP / 2 MP
1697.17
mm
Distance from bottom of the package to top of the die surface
1.145
1.25
1.405
mm
Distance from top of the die surface to top of the glass lid
0.745
1.13
1.495
mm
XY size
19 x 19
Thickness
0.45
Spectral response range
400
Transmission of glass lid (refer to Figure 48)
0.55
mm
0.65
mm
1000
nm
92
%
Glass Lid Material
D263 Teco
Mechanical Shock
JESD22−B104C; Condition G
2000
g
Vibration
JESD22−B103B; Condition 1
2000
Hz
Mounting Profile
Reflow profile according to J−STD−020D.1
260
°C
CTE
Coefficient of Thermal expansion of the LCC Package
Coefficient of Thermal expansion of the LGA Package
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79
7.6
7.1
mm/°C
NOIP1SN5000A
Table 32. OPTICAL CENTER INFORMATION FOR THE PYTHON 5000/2000 IN LCC−84 PINS AND LGA−128 PADS
PYTHON5000
References*
Die Outer Coordinates
PYTHON2000
X (mm)
Y (mm)
X (mm)
Y (mm)
D1
0
14250
0
14250
D2
14700
14250
14700
14250
D3
14700
0
14700
0
D4
0
0
0
0
Die Center
CD
7350
7125
7350
7125
Active Area Coordinates
A1
878.63
13756.57
878.63
13756.57
A2
13358.63
13756.57
13358.63
13756.57
A3
13358.63
3887.77
13358.63
3887.77
A4
878.63
3887.77
878.63
3887.77
AA
7118.63
8822.17
7195.43
8822.17
Active Area Center
Pitch
4.8
4.8
4.8
4.8
2600
2056
2600
2056
8
8
616
792
2592
2048
1984
1264
Act_A1
897.83
13737.37
2433.83
11855.77
Act_A2
13339.43
13737.37
11957.03
11855.77
Act_A3
13339.43
3906.97
11957.03
5788.57
Act_A4
897.83
3906.97
2433.83
5788.57
# Pixels
# Dummy
# Active Pixels
*Refer to Figure 46 below.
Figure 46. Optical Center Information for PYTHON 5000/2000 for LCC−84 Pins and LGA−128 Pads
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80
NOIP1SN5000A
Packing and Tray Specification
The PYTHON packing specification with onsemi packing labels is packed as follows:
Table 33. PACKING AND TRAY INFORMATION FOR P1−SN/SE/FN, P3−SN/SE
Package Size (mm)
Tray
Restraint
Box
Package
Length
Width
Thickness*
Tray
Quantity / Tray
Strap
Bag
Tray Quantity
LCC−84
pin
19
19
2.58
KS−87054
1
42
Rubbe
rband
Double bagged using
MBB and pink ESD
bag
5 trays + 1
cover tray
LGA−128
pin
*Includes package, glass and glue attach thickness.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
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81
NOIP1SN5000A
Figure 47. Packing and Tray Configuration
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82
NOIP1SN5000A
Glass Lid
As shown in Figure 48, no infrared attenuating color filter
glass is used. A filter must be provided in the optical path
when
color
devices
are
used
(source:
http://www.pgo−online.com).
The PYTHON 2000 and PYTHON 5000 sensor uses a
glass lid without any coatings. Figure 48 shows the
transmission characteristics of the glass lid.
Figure 48. Transmission Characteristics of the Glass Lid
Protective Film Option (−QTI Versions)
For certain size and speed options, the sensor can be
delivered with a protective foil that is intended to be
removed after assembly. The dimensions of the foil are as
illustrated in Figure 49 with the tab aligned towards one
corner of the package as illustrated in Figure 50.
Figure 50. Location of the Pull Tab in Reference to
LCC−Pin 1 and LGA−Pad A1
Figure 49. Dimensions of the Tape
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83
NOIP1SN5000A
SPECIFICATIONS AND USEFUL REFERENCES
Useful References
The following references are available to customers under
NDA at the onsemi Image Sensor Portal:
• Product Acceptance Criteria
• Product Qualification Report
• PYTHON Developer’s Guide AND9362/D
For information on ESD and cover glass care and
cleanliness, please download the Image Sensor Handling
and Best Practices Application Note (AN52561/D) from
www.onsemi.com.
For quality and reliability information, please download
the Quality & Reliability Handbook (HBD851/D) from
www.onsemi.com.
For information on Standard terms and Conditions of
Sale, please download Terms and Conditions from
www.onsemi.com.
For information on acronyms and a glossary of terms
used, please download Image Sensor Terminology
(TND6116/D) from www.onsemi.com.
Material Composition is available at:
http://www.onsemi.com/PowerSolutions/MaterialCompos
ition.do?searchParts=PYTHON5000
Return Material Authorization (RMA)
Refer to the onsemi RMA policy procedure at
http://www.onsemi.com/site/pdf/CAT_Returns_FailureAn
alysis.pdf
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84
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
LCC84, 19x19
CASE 115BC
ISSUE A
DATE 26 JUN 2015
GENERIC
MARKING DIAGRAM
XXXXXXXXXXXX
XXXX
AWLYYWW
XXXXX
A
WL
YY
WW
DOCUMENT NUMBER:
DESCRIPTION:
98AON82963F
LCC84, 19.00 X 19.00
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
LBGA128 19x19
CASE 715AB
ISSUE O
DOCUMENT NUMBER:
DESCRIPTION:
98AON13079G
LBGA128 19X19
DATE 05 JUL 2016
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
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