PYTHON480
PYTHON 0.48 Megapixel
Global Shutter CMOS
Image Sensor
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FEATURES
• 808 x 608 Active Pixels, 1/3.6” Optical Format
• 4.8 mm x 4.8 mm Low Noise Global Shutter Pixels with
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In-pixel CDS
Monochrome (SN, SP), Color (SE, SF)
Wide CRA Options (SP, SF)
Frame Rate up to 120 fps at Full Resolution
On−chip 10−bit Analog−to−Digital Converter (ADC)
10−bit Output Mode
One Low Voltage Differential Signaling (LVDS)
High Speed Serial Output or Parallel CMOS Output
Random Programmable Region of Interest (ROI)
Readout
Serial Peripheral Interface (SPI)
Automatic Exposure Control (AEC)
Phase Locked Loop (PLL)
Dual Power Supply (3.3 V and 1.8 V)
−40°C to +85°C Operational Temperature Range
67 pin CSP
265 mW / 226 mW Power Dissipation (LVDS 120 fps /
60 fps)
These Devices are Pb−Free and are RoHS Compliant
DESCRIPTION
The PYTHON 480 image sensor utilizes high sensitivity
4.8 mm x 4.8 mm pixels that support low noise “pipelined”
and “triggered” global shutter readout modes. In global
shutter mode, the sensors support correlated double
sampling (CDS) readout, reducing noise and increasing
dynamic range.
The image sensors have on−chip programmable gain
amplifiers and 10−bit A/D converters. The integration time
and gain parameters can be reconfigured without any visible
image artifact. Optionally the on−chip automatic exposure
control loop (AEC) controls these parameters dynamically.
The image’s black level is either calibrated automatically or
can be adjusted by a user programmable offset.
A high level of programmability using a four wire serial
peripheral interface enables the user to read out specific
regions of interest. Up to four regions can be programmed,
achieving even higher frame rates.
The image data interface consists of one LVDS data lane,
facilitating frame rate up to 120 frames per second.
A separate synchronization channel containing payload
information is provided to facilitate the image
reconstruction at the receiving end. The device also provides
a parallel CMOS output interface at the same frame rate.
The PYTHON 480 is packaged in a 67−pin CSP package
and is available in monochrome and Bayer color
configurations with standard and wide CRA options.
APPLICATIONS
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Machine Vision
Motion Monitoring
Security
Bar Code Scanning
© Semiconductor Components Industries, LLC, 2016
May, 2018 − Rev. 3
1
Publication Order Number:
NOIP1SN0480A/D
PYTHON 480
ORDERING INFORMATION
Part Number
Description
NOIP1SN0480A−STI
0.48 MegaPixel, Monochrome, CRA 1.65
NOIP1SE0480A−STI
0.48 MegaPixel, Bayer Color, CRA 1.65
NOIP1SP0480A−STI
0.48 MegaPixel, Monochrome, CRA 23.59
NOIP1SF0480A−STI
0.48 MegaPixel, Bayer Color, CRA 23.59
NOIP1SN0480A−STI1
0.48 MegaPixel, Monochrome, CRA 1.65
NOIP1SE0480A−STI1
0.48 MegaPixel, Bayer Color, CRA 1.65
NOIP1SP0480A−STI1
0.48 MegaPixel, Monochrome, CRA 23.59
NOIP1SF0480A−STI1
0.48 MegaPixel, Bayer Color, CRA 23.59
MPQ
Package
100
67−ball CSP
10
NOTE: More details on the part coding can be found at http://www.onsemi.com/pub_link/Collateral/TND310−D.PDF
PRODUCTION MARK
Part Number
10−Digit Package Mark
NOIP1SN0480A−STI/STI1
SN480 YM NNN
NOIP1SE0480A−STI/STI1
SE480 YM NNN
NOIP1SP0480A−STI/STI1
SP480 YM NNN
NOIP1SF0480A−STI/STI1
SF480 YM NNN
where Y is 1−digit year, M is the 1−digit month, NNN is the 3−digit serial number for wafer identification
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PYTHON 480
SPECIFICATIONS
Key Specifications
Table 2. ELECTRO−OPTICAL SPECIFICATIONS
Table 1. GENERAL SPECIFICATIONS
Parameter
Specification
Parameter
Pixel type
In−pixel CDS. Global shutter pixel
architecture
Shutter type
Pipelined and triggered global shutter
Frame rate
up to 120fps (Full Frame readout)
Master clock
Specification
Active pixels
808 (H) x 608 (V)
Pixel size
4.8 mm x 4.8 mm
Conversion gain
0.096 LSB10/e−
140 mV/e−
LVDS Mode:
68 MHz when PLL is used,
340 MHz (10−bit) / 272 MHz (8−bit)
when PLL is not used
CMOS Mode: 68 MHz
Dark temporal noise
< 11 e−
Responsivity at 550 nm
7.7 V/lux.s
Parasitic Light
Sensitivity (PLS)
59 dB
67−pin CSP
Signal to Noise Ratio
(SNR max)
40 dB
Package type
Windowing
ADC resolution
10−bit
LVDS outputs
data + sync + clock
CMOS outputs
10−bit parallel output, frame_valid,
line_valid, clock
Data rate
NOTE: All numbers listed are for 1x analog gain condition unless
otherwise noted.
NOTE: All numbers listed are for 1x gain condition unless
otherwise noted.
Table 3. RECOMMENDED OPERATING RATINGS (Note 1)
Symbol
TJ
Description
Operating temperature range
Min
Max
Unit
−40
85
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
1. Performance parameters may degrade above 60°C.
Table 4. ABSOLUTE MAXIMUM RATINGS (Note 4)
Min
Max
Unit
ABS (1.8 V supply group)
ABS rating for 1.8 V supply group
Parameter
–0.5
2.2
V
ABS (3.3 V supply group)
ABS rating for 3.3 V supply group
–0.5
3.8
V
ABS storage temperature range
−40
150
°C
85
%RH
Symbol
TS
ABS storage humidity range at 85°C
Electrostatic discharge (ESD)
LU
Human Body Model (HBM): JS−001
2000
Charged Device Model (CDM): JESD22−C101
500
Latch−up: JESD−78
100
V
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. The ADC is 11−bit, down−scaled to 10−bit. The PYTHON uses a larger word−length internally to provide 10−bit on the output.
3. Operating ratings are conditions in which operation of the device is intended to be functional.
4. ON Semiconductor recommends that customers become familiar with, and follow the procedures in JEDEC Standard JESD625−A. Refer
to Application Note AN52561. Long term exposure toward the maximum storage temperature will accelerate color filter degradation.
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PYTHON 480
Table 5. ELECTRICAL SPECIFICATIONS
Boldface limits apply for TJ = TMIN to TMAX, all other limits TJ = +30°C. (Notes 5, 6, 7, 8)
Description
Parameter
Min
Typ
Max
Unit
3.4
V
Power Supply Parameters − LVDS
(NOTE: All ground pins (gnd_18, gnd_33, gnd_colpc) should be connected to an external 0 V ground reference.)
vdd_33
Supply voltage, 3.3 V
3.3
Idd_33
Current consumption 3.3 V supply
vdd_18
Supply voltage, 1.8 V
Idd_18
Current consumption 1.8 V supply
vdd_pix
Supply voltage, pixel
Idd_pix
Current consumption pixel supply
0.04
mA
Ptot
Total power consumption at vdd_33 = 3.3 V, vdd_18 = 1.8 V
265
mW
Pstby_lp
Power consumption in low power standby mode
10us
> 10us
> 10us
> 10us
Figure 17. Power Up Sequence
Enable Clock Management
In the serial modes, if the PLL is not used, the LVDS clock
input must be running.
The ‘Enable Clock Management’ action configures the
clock management blocks and activates the clock generation
and distribution circuits in a pre−defined way. First, a set of
clock settings must be uploaded through the SPI register.
These settings are dependent on the desired operation mode
of the sensor.
The SPI uploads that need to be executed to configure the
sensor for LVDS 10−bit serial mode, with the PLL, as well
as all other supported modes are available to customers
under NDA at the ON Semiconductor Image Sensor Portal:
https://www.onsemi.com/PowerSolutions/myon/erCispFol
der.do
Use of Phase Locked Loop
If PLL is used, the PLL is started after the upload of the
SPI registers. The PLL requires (dependent on the settings)
some time to generate a stable output clock. A lock detect
circuit detects if the clock is stable. When complete, this is
flagged in a status register.
Check the PLL_lock flag 24[0] by reading the SPI
register. When the flag is set, the ‘Enable Clock
Management’ action can be continued. When PLL is not
used, this step can be bypassed as shown in Figure 16 on
page 16.
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PYTHON 480
Required Register Upload
Disable Clock Management
In this phase, the ‘reserved’ register settings are uploaded
through the SPI register. Different settings are not allowed
and may cause the sensor to malfunction. The required
uploads can be downloaded from the MyON website.
The ‘Disable Clock Management’ action stops the
internal clocking to further decrease the power dissipation.
Power Down Sequence
Figure 18 illustrates the timing diagram of the preferred
power down sequence. It is important that the sensor is in
reset before the clock input stops running. Otherwise, the
internal PLL becomes unstable and the sensor gets into an
unknown state. This can cause high peak currents.
The same applies for the ramp down of the power
supplies. The preferred order to ramp down the supplies is
first vdd_pix, second vdd_33, and finally vdd_18. Any other
sequence can cause high peak currents.
NOTE: The ‘clock input’ can be the LVDS clock input
(lvds_clock_inn/p) in case the PLL is bypassed.
Soft Power Up
During the soft power up action, the internal blocks are
enabled and prepared to start processing the image data
stream. This action exists of a set of SPI uploads.
Enable Sequencer
During the ‘Enable Sequencer’ action, the frame grabbing
sequencer is enabled. The sensor starts grabbing images in
the configured operation mode. Refer to Sensor States on
page 17.
The ‘Enable Sequencer’ action consists of enabling bit
192[0].
clock input
User Actions: Functional Modes to Power Down
Sequences
reset_n
Disable Sequencer
During the ‘Disable Sequencer’ action, the frame
grabbing sequencer is stopped. The sensor stops grabbing
images and returns to the idle mode.
The ‘Disable Sequencer’ action consists of disabling bit
192[0].
vdd_18
vdd_33
vdd_pix
Soft Power Down
During the soft power down action, the internal blocks are
disabled and the sensor is put in standby state to reduce the
current dissipation. This action exists of a set of SPI uploads.
> 10us
> 10us
> 10us
> 10us
Figure 18. Power Down Sequence
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PYTHON 480
Sensor Reconfiguration
Sensor Configuration
During the standby, idle, or running state several sensor
parameters can be reconfigured.
• Frame Rate and Exposure Time: Frame rate and
exposure time changes can occur during standby, idle,
and running states by modifying registers 199 to 203.
Refer to page 30−32 for more information.
• Signal Path Gain: Signal path gain changes can occur
during standby, idle, and running states by modifying
registers 204/205. Refer to page 37 for more
information.
• Windowing: Changes with respect to windowing can
occur during standby, idle, and running states. Refer to
Multiple Window Readout on page 26 for more
information.
• Subsampling: Changes of the subsampling mode can
occur during standby, idle, and running states by
modifying register 192. Refer to Subsampling on
page 27 for more information.
• Shutter Mode: The shutter mode can only be changed
during standby or idle mode by modifying register 192.
Reconfiguring the shutter mode during running state is
not supported.
This device contains multiple configuration registers.
Some of these registers can only be configured while the
sensor is not acquiring images (while register 192[0] = 0),
while others can be configured while the sensor is acquiring
images. For the latter category of registers, it is possible to
distinguish the register set that can cause corrupted images
(limited number of images containing visible artifacts) from
the set of registers that are not causing corrupted images.
These three categories are described here.
Static Readout Parameters
Some registers are only modified when the sensor is not
acquiring images. Reconfiguration of these registers while
images are acquired can cause corrupted frames or even
interrupt the image acquisition. Therefore, it is
recommended to modify these static configurations while
the sequencer is disabled (register 192[0] = 0). The registers
shown in Table 6 should not be reconfigured during image
acquisition. A specific configuration sequence applies for
these registers. Refer to the operation flow and startup
description.
Table 6. STATIC READOUT PARAMETERS
Group
Addresses
Description
Clock generator
32
Configure according to recommendation
Image core
40
Configure according to recommendation
AFE
48
Configure according to recommendation
Bias
64–71
Configure according to recommendation
LVDS
112
Configure according to recommendation
192 [5:4]
Operation modes are: • triggered_mode
• slave_mode
Sequencer mode selection
All reserved registers
Keep reserved registers to their default state, unless otherwise described in the
recommendation
Dynamic Configuration Potentially Causing Image
Artifacts
image containing visible artifacts. A typical example of a
corrupted image is an image which is not uniformly
exposed.
The effect is transient in nature and the new configuration
is applied after the transient effect.
The category of registers as shown in Table 7 consists of
configurations that do not interrupt the image acquisition
process, but may lead to one or more corrupted images
during and after the reconfiguration. A corrupted image is an
Table 7. DYNAMIC CONFIGURATION POTENTIALLY CAUSING IMAGE ARTIFACTS
Group
Addresses
Description
Black level configuration
128–129
197[12:8]
reconfiguration of these registers may have an impact on the black−level
calibration algorithm. The effect is a transient number of images with incorrect black
level compensation.
Sync codes
129[13]
116–126
Incorrect sync codes may be generated during the frame in which these registers
are modified.
Datablock test configurations
144
Modification of these registers may generate incorrect test patterns during
a transient frame.
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PYTHON 480
Dynamic Readout Parameters
shown in Table 8. Some reconfiguration may lead to one
frame being blanked. This happens when the modification
requires more than one frame to settle. The image is blanked
out and training patterns are transmitted on the data and sync
channels.
It is possible to reconfigure the sensor while it is acquiring
images. Frame related parameters are internally
resynchronized to frame boundaries, such that the modified
parameter does not affect a frame that has already started.
However, there can be restrictions to some registers as
Table 8. DYNAMIC READOUT PARAMETERS
Group
Addresses
Subsampling
192[7]
Description
Subsampling is synchronized to a new frame start.
ROI configuration
195
256–265
A ROI switch is only detected when a new window is selected as the active window
(reconfiguration of register 195). reconfiguration of the ROI dimension of the active window does not lead to a frame blank and can cause a corrupted image.
Exposure
reconfiguration
199−203
Exposure reconfiguration does not cause artifact. However, a latency of one frame is observed unless reg_seq_exposure_sync_mode is set to ‘1’ in triggered global mode (master).
Gain reconfiguration
204−205
Gains are synchronized at the start of a new frame. Optionally, one frame latency can be
incorporated to align the gain updates to the exposure updates
(refer to register 204[13] − gain_lat_comp).
Freezing Active Configurations
registers and uses them for the coming frames. Freezing of
the active set of registers can be programmed in the
sync_configuration registers, which can be found at the SPI
address 206.
Figure 19 shows a reconfiguration that does not use the
sync_configuration option. As depicted, new SPI
configurations are synchronized to frame boundaries.
Figure 20 shows the usage of the sync_configuration
settings. Before uploading a set of registers, the
corresponding sync_configuration is de−asserted. After the
upload is completed, the sync_configuration is asserted
again and the sensor resynchronizes its set of registers to the
coming frame boundaries. As seen in the figure, this ensures
that the uploads performed at the end of frame N+2 and the
start of frame N+3 become active in the same frame (frame
N+4).
Though the readout parameters are synchronized to frame
boundaries, an update of multiple registers can still lead to
a transient effect in the subsequent images, as some
configurations require multiple register uploads. For
example, to reconfigure the exposure time in master global
mode, both the fr_length and exposure registers need to be
updated. Internally, the sensor synchronizes these
configurations to frame boundaries, but it is still possible
that the reconfiguration of multiple registers spans over two
or even more frames. To avoid inconsistent combinations,
the active configurations can be frozen while altering the
SPI registers by disabling synchronization for the
corresponding functionality before reconfiguration. When
all registers are uploaded, re−enable the synchronization.
The sensor’s sequencer then updates its active set of
Time Line
Frame NFrame N+1 Frame N+2 Frame N+3
Frame N+4
SPI Registers
Active Registers
Figure 19. Frame Synchronization of Configurations (no freezing)
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PYTHON 480
Frame NFrame N+1 Frame N+2 Frame N+3 Frame N+4
Time Line
sync_configuration
This configuration is not taken into
account as sync_register is inactive.
SPI Registers
Active Registers
Figure 20. reconfiguration Using Sync_configuration
NOTE: SPI updates are not taken into account while sync_configuration is inactive. The active configuration is frozen
for the sensor. Table 9 lists the several sync_configuration possibilities along with the respective registers being
frozen.
Table 9. ALTERNATE SYNC CONFIGURATIONS
Group
sync_black_lines
sync_dummy_lines
sync_exposure
sync_gain
sync_roi
Affected Registers
black_lines
Description
Update of black line configuration is not synchronized at start of frame when ‘0’.
The sensor continues with its previous configurations.
dummy_lines
Update of dummy line configuration is not synchronized at start of frame when ‘0’.
The sensor continues with its previous configurations.
mult_timer
fr_length
exposure
Update of exposure configurations is not synchronized at start of frame when ‘0’.
The sensor continues with its previous configurations.
mux_gainsw
afe_gain
db_gain
roi_active0[3:0]
subsampling
Update of gain configurations is not synchronized at start of frame when ‘0’.
The sensor continues with its previous configurations.
Update of active ROI configurations is not synchronized at start of frame when ‘0’.
The sensor continues with its previous configurations.
Note: The window configurations themselves are not frozen. reconfiguration of
active windows is not gated by this setting.
Window Configuration
Black Calibration
Up to 4 windows can be defined in global shutter mode
(pipelined or triggered). The windows are defined by
registers 256 to 265. Each window can be activated or
deactivated separately using register 195. It is possible to
reconfigure the inactive windows while the sensor is
acquiring images.
Switching between predefined windows is achieved by
activation of the respective windows. This way a minimum
number of registers need to be uploaded when it is necessary
to switch between two or more sets of windows. As an
example of this, scanning the scene at higher frame rates
using multiple windows and switching to full frame capture
when the object is tracked. Switching between the two
modes only requires an upload of one register.
The sensor automatically calibrates the black level for
each frame. Therefore, the device generates a configurable
number of electrical black lines at the start of each frame.
The desired black level in the resulting output interface can
be configured and is not necessarily targeted to ‘0’.
Configuring the target to a higher level yields some
information on the left side of the black level distribution,
while the other end of the distribution tail is clipped to ‘0’
when setting the black level target to ‘0’.
The black level is calibrated for the 2 columns contained
in one kernel. This implies 2 black level offsets are generated
and applied to the corresponding columns. Configurable
parameters for the black−level algorithm are listed in
Table 10.
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PYTHON 480
Table 10. CONFIGURABLE PARAMETERS FOR BLACK LEVEL ALGORITHM
Group
Addresses
Description
197[7:0]
black_lines
This register configures the number of black lines that are generated at the start of a
frame. At least one black line must be generated. The maximum number is 255.
Note: When the automatic black−level calibration algorithm is enabled, make sure that this
register is configured properly to produce sufficient black pixels for the black−level filtering.
The number of black pixels generated per line is dependent on the operation mode and
window configurations:
Each black line contains 404 kernels.
197[12:8]
gate_first_line
A number of black lines are blanked out when a value different from 0 is configured. These
blanked out lines are not used for black calibration. It is recommended to enable this functionality, because the first line can have a different behavior caused by boundary effects.
auto_blackcal_enable
Internal black−level calibration functionality is enabled when set to ‘1’. Required black level
offset compensation is calculated on the black samples and applied to all image pixels.
When set to ‘0’, the automatic black−level calibration functionality is disabled. It is possible
to apply an offset compensation to the image pixels, which is defined by the registers
129[10:1].
Note: Black sample pixels are not compensated; the raw data is sent out to provide
external statistics and, optionally, calibrations.
129[9:1]
blackcal_offset
Black calibration offset that is added or subtracted to each regular pixel value when auto_blackcal_enable is set to ‘0’. The sign of the offset is determined by register 129[10]
(blackcal_offset_dec).
Note: All channels use the same offset compensation when automatic black calibration is
disabled. The calculated black calibration factors are frozen when this register is set to
0x1FF (all−‘1’) in auto calibration mode. Any value different from 0x1FF re−enables the
black calibration algorithm. This freezing option can be used to prevent eventual frame to
frame jitter on the black level as the correction factors are recalculated every frame. It is
recommended to enable the black calibration regularly to compensate for temperature
changes.
129[10]
blackcal_offset_dec
Sign of blackcal_offset. If set to ‘0’, the black calibration offset is added to each pixel. If set
to ‘1’, the black calibration offset is subtracted from each pixel.
This register is not used when auto_blackcal_enable is set to ‘1’.
black_samples
The black samples are low−pass filtered before being used for black level calculation. The
more samples are taken into account, the more accurate the calibration, but more samples
require more black lines, which in turn affects the frame rate.
The effective number of samples taken into account for filtering is 2^black_samples.
Note: An error is reported by the device if more samples than available are requested
(refer to register 136).
Black Line Generation
Black Value Filtering
129[0]
128[10:8]
Black Level Filtering Monitoring
136
blackcal_error0
An error is reported by the device if there are requests for more samples than are available
(each bit corresponding to one data path). The black level is not compensated correctly if
one of the channels indicates an error. There are three possible methods to overcome this
situation and to perform a correct offset compensation:
• Increase the number of black lines such that enough samples are generated at the
cost of increasing frame time (refer to register 197).
• Relax the black calibration filtering at the cost of less accurate black level determination (refer to register 128).
• Disable automatic black level calibration and provide the offset via SPI register upload.
Note that the black level can drift in function of the temperature. It is thus recommended
to perform the offset calibration periodically to avoid this drift.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
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PYTHON 480
Serial Peripheral Interface
The sck clock is passed through to the sensor as
indicated in Figure 21. The sensor samples this
data on a rising edge of the sck clock (mosi needs
to be driven by the system on the falling edge of
the sck clock).
5. The tenth bit sent by the master indicates the type
of transfer: high for a write command, low for a
read command.
6. Data transmission:
- For write commands, the master continues
sending the 16−bit data, most significant bit first.
- For read commands, the sensor returns the
requested address on the miso pin, most significant
bit first. The miso pin must be sampled by the
system on the falling edge of sck (assuming
nominal system clock frequency and maximum
10 MHz SPI frequency).
7. When data transmission is complete, the system
deselects the sensor one clock period after the last
bit transmission by pulling ss_n high.
Note that the maximum frequency for the SPI interface
scales with the input clock frequency, bit depth and LVDS
output multiplexing as described in Table 5.
Consecutive SPI commands can be issued by leaving at
least two SPI clock periods between two register uploads.
Deselect the chip between the SPI uploads by pulling the
ss_n pin high.
The sensor configuration registers are accessed through
an SPI. The SPI consists of four wires:
• sck: Serial Clock
• ss_n: Active Low Slave Select
• mosi: Master Out, Slave In, or Serial Data In
• miso: Master In, Slave Out, or Serial Data Out
The SPI is synchronous to the clock provided by the
master (sck) and asynchronous to the sensor’s system clock.
When the master wants to write or read a sensor’s register,
it selects the chip by pulling down the Slave Select line
(ss_n). When selected, data is sent serially and synchronous
to the SPI clock (sck).
Figure 21 shows the communication protocol for read and
write accesses of the SPI registers. The PYTHON 480 image
sensors use 9−bit addresses and 16−bit data words.
Data driven by the system is colored blue in Figure 21,
while data driven by the sensor is colored yellow. The data
in grey indicates high−Z periods on the miso interface. Red
markers indicate sampling points for the sensor (mosi
sampling); green markers indicate sampling points for the
system (miso sampling during read operations).
The access sequence is:
3. Select the sensor for read or write by pulling down
the ss_n line.
4. One SPI clock cycle after selecting the sensor, the
9−bit data is transferred, most significant bit first.
SPI − WRITE
ss_n
t_sckss
tsck
t_sssck
sck
ts _mos i
mosi
A8
th_mosi
A7
..
..
..
A1
A0
`1'
D15
D14
..
..
..
..
D1
D0
miso
SPI − READ
ss_n
t_sssck
t_sckss
tsck
sck
ts_mosi
mosi
A8
th_mosi
A7
..
..
..
A1
A0
`0'
ts _miso
miso
D15
th_miso
D14
..
..
Figure 21. SPI Read and Write Timing Diagram
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..
..
D1
D0
PYTHON 480
Table 11. SPI TIMING REQUIREMENTS
Group
Addresses
Description
Units
100 (*)
ns
ss_n low to sck rising edge
tsck
ns
tsckss
sck falling edge to ss_n high
tsck
ns
ts_mosi
Required setup time for mosi
20
ns
th_mosi
Required hold time for mosi
20
ns
ts_miso
Setup time for miso
tsck/2−10
ns
th_miso
Hold time for miso
tsck/2−20
ns
tspi
Minimal time between two consecutive SPI accesses (not shown in figure)
2 x tsck
ns
tsck
sck clock period
tsssck
*Value indicated is for nominal operation. The maximum SPI clock frequency depends on the sensor configuration (operation mode, input clock).
tsck is defined as 1/fSPI. See text for more information on SPI clock frequency restrictions.
IMAGE SENSOR TIMING AND READOUT
exposure time. The length of the exposure time is defined by
the registers exposure and mult_timer.
NOTE: The start of the exposure time is synchronized to
the start of a new line (during ROT) if the
exposure period starts during a frame readout.
As a consequence, the effective time during
which the image core is in a reset state is
extended to the start of a new line.
• Make sure that the sum of the reset time and exposure
time exceeds the time required to readout all lines. If
this is not the case, the exposure time is extended until
all (active) lines are read out.
• Alternatively, it is possible to specify the frame time
and exposure time. The sensor automatically calculates
the required reset time. This mode is enabled by the
fr_mode register. The frame time is specified in the
register fr_length.
The following sections describe the configurations for
single slope reset mechanism. Extra integration time
registers are available.
Pipelined Global Shutter (Master)
The integration time is controlled by the registers
fr_length[15:0] and exposure[15:0]. The mult_timer
configuration defines the granularity of the registers
reset_length and exposure. It is read as number of system
clock cycles (14.706 ns nominal at 68 MHz).
The exposure control for (Pipelined) Global Master mode
is depicted in Figure 22.
The pixel values are transferred to the storage node during
FOT, after which all photo diodes are reset. The reset state
remains active for a certain time, defined by the reset_length
and mult_timer registers, as shown in the figure. Note that
meanwhile the image array is read out line by line. After this
reset period, the global photodiode reset condition is
abandoned. This indicates the start of the integration or
Frame N
Exposure State
FOT
Readout
FOT
Reset
Frame N+1
Integrating
FOT
Reset
Integrating
FOT
FOT
FOT
Image Array Global Reset
reset_length
x
mult_timer
exposure
x
mult_timer
= ROT
= Readout
= Readout Dummy Line (blanked)
Figure 22. Integration Control for (Pipelined) Global Shutter Mode (Master)
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24
PYTHON 480
Triggered Global Shutter (Master)
exposure and mult_timer, as in the master pipelined global
mode. The fr_length configuration is not used. This
operation is graphically shown in Figure 23.
In master triggered global mode, the start of integration
time is controlled by a rising edge on the trigger0 pin. The
exposure or integration time is defined by the registers
Frame N
Exposure State
FOT
Reset
Integrating
FOT
Reset
Integrating
FOT
(No effect on falling edge)
trigger0
Readout
Frame N+1
FOT
FOT
FOT
Image Array Global Reset
exposure x mult_timer
= ROT
= Readout
= Readout Dummy Line (blanked)
Figure 23. Exposure Time Control in Triggered Shutter Mode (Master)
the pixel storage node and readout of the image array. In
other words, the high time of the trigger pin indicates the
integration time, the period of the trigger pin indicates the
frame time.
The use of the trigger during slave mode is shown in
Figure 24.
Notes:
• The falling edge on the trigger pin does not have any
impact. Note however the trigger must be asserted for
at least 100 ns.
• The start of the exposure time is synchronized to the
start of a new line (during ROT) if the exposure period
starts during a frame readout. As a consequence, the
effective time during which the image core is in a reset
state is extended to the start of a new line.
• If the exposure timer expires before the end of readout,
the exposure time is extended until the end of the last
active line.
• The trigger pin needs to be kept low during the FOT.
The monitor pins can be used as a feedback to the
FPGA/controller (eg. use monitor0, indicating the very
first line when monitor_select = 0x5 − a new trigger can
be initiated after a rising edge on monitor0).
Notes:
• The registers exposure, fr_length, and mult_timer are
•
•
•
Triggered Global Shutter (Slave)
Exposure or integration time is fully controlled by means
of the trigger pin in slave mode. The registers fr_length,
exposure and mult_timer are ignored by the sensor.
A rising edge on the trigger pin indicates the start of the
exposure time, while a falling edge initiates the transfer to
not used in this mode.
The start of exposure time is synchronized to the start
of a new line (during ROT) if the exposure period starts
during a frame readout. As a consequence, the effective
time during which the image core is in a reset state is
extended to the start of a new line.
If the trigger is de−asserted before the end of readout,
the exposure time is extended until the end of the last
active line.
The trigger pin needs to be kept low during the FOT.
The monitor pins can be used as a feedback to the
FPGA/controller (eg. use monitor0, indicating the very
first line when monitor_select = 0x5 − a new trigger can
be initiated after a rising edge on monitor0).
Frame N
Exposure State
FOT
Reset
Frame N+1
Integrating
FOT
Reset
Integrating
FOT
trigger0
Readout
FOT
FOT
FOT
Image Array Global Reset
= ROT
= Readout
= Readout Dummy Line (blanked)
Figure 24. Exposure Time Control in Global−Slave Mode
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PYTHON 480
ADDITIONAL FEATURES
Multiple Window Readout
The PYTHON 480 image sensors support multiple
window readout, which means that only the user−selected
Regions Of Interest (ROI) are read out. This allows limiting
data output for every frame, which in turn allows increasing
the frame rate. Up to four ROIs can be configured.
y1_end
ROI 1
y0_end
y1_start
ROI 0
Window Configuration
Figure 25 shows the four parameters defining a region of
interest (ROI).
y0_start
y-end
x0_start
x0_end
x1_start
ROI 0
x1_end
Figure 26. Overlapping Multiple Window
Configuration
y-start
The sequencer analyses each line that need to be read out
for multiple windows.
Restrictions
The following restrictions for each line are assumed for
the user configuration:
• Windows are ordered from left to right, based on their
x−start address:
x-start x-end
Figure 25. Region of Interest Configuration
x_start_roi(i) v x_start_roi(j) AND
• x−start[8:0]
x−start defines the x−starting point of the desired window.
The sensor reads out 2 pixels in one single clock cycle. As
a consequence, the granularity for configuring the x−start
position is also 2 pixels for no sub sampling. The value
configured in the x−start register is multiplied by 2 to find
the corresponding column in the pixel array.
• x−end[8:0]
This register defines the window end point on the x−axis.
Similar to x−start, the granularity for this configuration is
one kernel. x−end needs to be larger than x−start.
• y−start[9:0]
The starting line of the readout window. The granularity
of this setting is one line, except with color sensors where it
needs to be an even number.
• y−end[9:0]
The end line of the readout window. y−end must be
configured larger than y−start. This setting has the same
granularity as the y−start configuration.
Up to four windows can be defined, possibly (partially)
overlapping, as illustrated in Figure 26.
NOTE: The least significant configuration bits for x and
y parameters are located in separate registers
(refer to registers 264−265). One may decide not
to reconfigure these bits, in which case the
configuration granularity becomes 4 pixels for
both x− and y−configurations.
x_end_roi(i) vx_end_roi(j)
Where j > i
Processing Multiple Windows
The sequencer control block houses two sets of counters
to construct the image frame. As previously described, the
y−counter indicates the line that needs to be read out and is
incremented at the end of each line. For the start of the frame,
it is initialized to the y−start address of the first window and
it runs until the y−end address of the last window to be read
out. The last window is configured by the configuration
registers and it is not necessarily window #3.
The x−counter starts counting from the x−start address of
the window with the lowest ID which is active on the
addressed line. Only windows for which the current
y−address is enclosed are taken into account for scanning.
Other windows are skipped.
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PYTHON 480
Figure 27 illustrates a practical example of a
configuration with four windows. The current position of
the read pointer (ys) is indicated by a red line crossing the
image array. For this position of the read pointer, three
windows need to be read out. The initial start position for the
x−kernel pointer is the x−start configuration of ROI0.
Kernels are scanned up to the ROI2 x−end position. From
there, the x−pointer jumps to the next window, which is
ROI3 in this illustration. When reaching ROI3’s x−end
position, the read pointer is incremented to the next line and
xs is reinitialized to the starting position of ROI0.
Notes:
• The starting point for the readout pointer at the start of
a frame is the y−start position of the first active
window.
• The read pointer is not necessarily incremented by one,
but depending on the configuration, it can jump in
y−direction. In Figure 27, this is the case when reaching
the end of ROI0 where the read pointer jumps to the
y−start position of ROI1
• The x−pointer starting position is equal to the x−start
configuration of the first active window on the current
line addressed. This window is not necessarily window
#0.
• The x−pointer is not necessarily incremented by one
each cycle. At the end of a window it can jump to the
start of the next window.
• Each window can be activated separately. There is no
restriction on which window and how many of the 4
windows are active.
ROI 1
ROI 2
ROI 3
ys
ROI 0
Figure 27. Scanning the Image Array with
Four Windows
Subsampling
Subsampling is used to reduce the image resolution. This
allows increasing the frame rate. Two subsampling modes
are supported: for monochrome sensors (LVDS/CMOS) and
color sensors (LVDS/CMOS).
Monochrome Sensors
For monochrome sensors, the read−1−skip−1
subsampling scheme is used. Subsampling occurs both in x−
and y− direction.
Color Sensors
For color sensors, the read−2−skip−2 subsampling
scheme is used. Subsampling occurs both in x− and y−
direction. Figure 28 shows which pixels are read and which
ones are skipped.
Figure 28. Subsampling Scheme for Monochrome and Color Sensors
Reverse Readout
Reverse readout in x−direction can be done by toggling
reverse_x (reg 194[9]).
Reverse readout in y−direction can be done by toggling
reverse_y (reg 194[8]). The reference for y_start and y_end
pointers is reversed.
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27
PYTHON 480
Black Reference
lines are indicated on the output interface by means of a
dedicated Sync pattern (REF).
The black calibration block can be configured to either
perform black level correction and compression or not. In
the latter case, the LSB is discarded from the ADC word.
Optionally, the black level calibration processor can be
configured to transmit the average black level on the
reference lines. In this mode, the reference pixel data are
replaced by the average black level, as calculated by the
black calibration block. Channel differences can easily be
observed
in
this
mode
(See
register
reg_db_ref_bcal_enable).
The sensor reads out one or more black lines at the start of
every new frame. The number of black lines to be generated
is programmable and is minimal equal to 1. The length of the
black lines depends on the operation mode. The sensor
always reads out the entire line (404 kernels), independent
of window configurations.
The black references are used to perform black calibration
and offset compensation in the data channels. The raw black
pixel data is transmitted over the usual output interface,
while the regular image data is compensated (can be
bypassed).
On the output interface, black lines can be seen as a
separate window, however without Frame Start and Ends
(only Line Start/End). The Sync code following the Line
Start and Line End indications (“window ID”) contains the
active window number, which is 0. Black reference data is
classified by a BL code.
Signal Path Gain
Analog Gain Stages
Referring to Table 12, three gain settings are available in
the analog data path to apply gain to the analog signal before
it is digitized. The gain amplifier can apply a gain of
approximately 1x to 3.5x to the analog signal.
The moment a gain reconfiguration is applied and
becomes valid can be controlled by the gain_lat_comp
configuration.
With ‘gain_lat_comp’ set to ‘0’, the new gain
configurations are applied from the very next frame.
With ‘gain_lat_comp’ set to ‘1’, the new gain settings are
postponed by one extra frame. This feature is useful when
exposure time and gain are reconfigured together, as an
exposure time update always has one frame latency.
Reference Lines
The sensor optionally reads out one or more reference
lines after the black lines. The number of reference lines to
be generated is programmable. No reference lines shall be
generated when set to 0. As for the black lines, the length of
the reference lines depends on the operation mode.
The reference lines are not used internally in the sensor.
The ROT for these lines can be configured such that these
lines contain particular reference data, such as a grey level,
in order to perform PRNU correction off−chip. Reference
Table 12. SIGNAL PATH GAIN STAGES
Address
Gain Setting
Gain Stage 1 (204[4:0])
Gain Stage 2 (204[12:5])
Overall Gain
204[12:0]
0x00E1
1
1
1
204[12:0]
0x00E4
2
1
2
204[12:0]
0x0024
2
1.75
3.5
NOTE:
The sensor performance specifications are tested at unity gain. Analog gain above 2x affects noise performance. All other gains
settings shown in this table are tested for sensor functionality only.
Digital Gain Stage
The digital gain stage allows fine gain adjustments on the
digitized samples. The gain configuration is an absolute 5.7
unsigned number (5 digits before and 7 digits after the
decimal point).
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PYTHON 480
Automatic Exposure Control
AEC
Statistics
Requested Illumination Level
(Target)
Total Gain
Requested Gain
Changes
The exposure control mechanism has the shape of a
general feedback control system. Figure 29 shows the high
level block diagram of the exposure control loop.
AEC
Filter
AEC
Enforcer
Integration Time
Analog Gain (Coarse Steps)
Digital Gain (Fine Steps)
Image Capture
Figure 29. Automatic Exposure Control Loop
AEC Statistics Block
Three main blocks can be distinguished:
• The statistics block compares the average of the
current image’s samples to the configured target value
for the average illumination of all pixels
• The relative gain change request from the statistics
block is filtered through the AEC Filter block in the
time domain (low pass filter) before being integrated.
The output of the filter is the total requested gain in the
complete signal path.
• The enforcer block accepts the total requested gain and
distributes this gain over the integration time and gain
stages (both analog and digital)
The statistics block calculates the average illumination of
the current image. Based on the difference between the
calculated illumination and the target illumination the
statistics block requests a relative gain change.
Statistics Subsampling and Windowing
For average calculation, the statistics block will
sub−sample the current image or windows by taking every
fourth sample into account. Note that only the pixels read out
through the active windows are visible for the AEC. In the
case where multiple windows are active, the samples will be
selected from the total samples. Samples contained in a
region covered by multiple (overlapping) window will be
taking into account only once.
It is possible to define an AEC specific sub−window on
which the AEC will calculate it’s average. For instance, the
sensor can be configured to read out a larger frame, while the
illumination is measured on a smaller region of interest, e.g.
center weighted as shown in Table 13.
The automatic exposure control loop is enabled by asserting
the aec_enable configuration in register 160.
Table 13. AEC SAMPLE SELECTION
Register
Name
192[10]
roi_aec_enable
When 0x0, all active windows are selected for statistics calculation.
When 0x1, the AEC samples are selected from the active pixels contained in the region of interest defined
by roi_aec
Description
253−255
roi_aec
These registers define a window from which the AEC samples will be selected when roi_aec_enable is
asserted. Configuration is similar to the regular region of interests.
The intersection of this window with the active windows define the selected pixels. It is important that this
window at least overlaps with one or more active windows.
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29
PYTHON 480
AEC Filter Block
Target Illumination
The target illumination value is configured by means of
register desired_intensity as shown in Table 14.
The filter block low−pass filters the gain change requests
received from the statistics block.
The filter can be restarted by asserting the restart_filter
configuration of register 160.
Table 14. AEC TARGET ILLUMINATION
CONFIGURATION
AEC Enforcer Block
Register
Name
Description
161[9:0]
desired_intensity
Target intensity value, on 10−bit scale.
The enforcer block calculates the four different gain
parameters, based on the required total gain, thereby
respecting a specific hierarchy in those configurations.
Some (digital) hysteresis is added so that the (analog) sensor
settings don’t need to change too often.
Exposure Control Parameters
The several gain parameters are described below, in the
order in which these are controlled by the AEC for large
adjustments. Small adjustments are regulated by digital gain
only.
• Exposure Time
The exposure is the time between the global image array
reset de−assertion and the pixel charge transfer. The
granularity of the integration time steps is configured by the
mult_timer register.
NOTE: The exposure_time register is ignored when the
AEC is enabled. The register fr_length defines
the frame time and needs to be configured
accordingly.
• Analog Gain
The sensor has two analog gain stages, configurable
independently from each other. Typically the AEC shall only
regulate the first stage.
• Digital Gain
The last gain stage is a gain applied on the digitized
samples. The digital gain is represented by a 5.7 unsigned
number (i.e. 7 bits after the decimal point). While the analog
gain steps are coarse, the digital gain stage makes it possible
to achieve very fine adjustments.
Color Sensor
The weight of each color can be configured for color
sensors by means of scale factors. Note these scale factor are
only used to calculate the statistics in order to compensate
for (off−chip) white balancing and/or color matrices. The
pixel values itself are not modified.
The scale factors are configured as 3.7 unsigned numbers
(0x80 = unity). Refer to Table 15 for color scale factors. For
mono sensors, configure these factors to their default value.
Table 15. COLOR SCALE FACTORS
Register
Name
Description
162[9:0]
red_scale_factor
Red scale factor for AEC
statistics
163[9:0]
green1_scale_fa
ctor
Green1 scale factor for AEC
statistics
164[9:0]
green2_scale_fa
ctor
Green2 scale factor for AEC
statistics
165[9:0]
blue_scale_factor
Blue scale factor for AEC
statistics
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PYTHON 480
AEC Control Range
AEC Update Frequency
The control range for each of the exposure parameters can
be pre−programmed in the sensor. Table 16 lists the relevant
registers.
Table 16. MINIMUM AND MAXIMUM EXPOSURE
CONTROL PARAMETERS
As an integration time update has a latency of one frame,
the exposure control parameters are evaluated and updated
every other frame.
Note: The gain update latency must be postpone to match
the integration time latency. This is done by asserting the
gain_lat_comp register on address 204[13].
Register
Exposure Control Status Registers
Name
Description
168[15:0]
min_exposure
Lower bound for the integration
time applied by the AEC
169[1:0]
min_mux_gain
Lower bound for the first stage
analog amplifier.
This stage has two
configurations with the following
approximative gains:
0x1 = 1x
0x4 = 2x
169[3:2]
min_afe_gain
Lower bound for the second
stage analog amplifier.
This stage has two
configurations with the following
approximative gain settings:
0x7 = 1x
0x1 = 1.75x
169[15:4]
min_digital_gain
Lower bound for the digital gain
stage. This configuration
specifies the effective gain in 5.7
unsigned format
170[15:0]
max_exposure
Upper bound for the integration
time applied by the AEC
171[1:0]
171[3:2]
171[15:4]
max_mux_gain
max_afe_gain
max_digital_gain
Configured integration and gain parameters are reported
to the user by means of status registers. The sensor provides
two levels of reporting: the status registers reported in the
AEC address space are updated once the parameters are
recalculated and requested to the internal sequencer. The
status registers residing in the sequencer’s address space on
the other hand are updated once these parameters are taking
effect on the image readout. Refer to Table 17 reflecting the
AEC and Sequencer Status registers.
Table 17. EXPOSURE CONTROL STATUS REGISTERS
Register
Name
Description
AEC Status Registers
Upper bound for the first stage
analog amplifier.
This stage has two
configurations with the following
approximative gains:
0x1 = 1x
0x4 = 2x
Upper bound for the second
stage analog amplifier
This stage has two
configurations with the following
approximative gain settings:
0x7 = 1x
0x1 = 1.75x
184[15:0]
total_pixels
Total number of pixels taken into
account for the AEC statistics.
186[9:0]
average
Calculated average illumination
level for the current frame.
187[15:0]
exposure
AEC calculated exposure.
Note: this parameter is updated at
the frame end.
188[1:0]
mux_gain
AEC calculated analog gain
(1st stage)
Note: this parameter is updated at
the frame end.
188[3:2]
afe_gain
AEC calculated analog gain
(2nd stage)
Note: this parameter is updated at
the frame end.
188[15:4]
digital_gain
AEC calculated digital gain
(5.7 unsigned format)
Note: this parameter is updated at
the frame end.
Upper bound for the digital gain
stage. This configuration
specifies the effective gain in 5.7
unsigned format
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PYTHON 480
Mode Changes and Frame Blanking
summarized in the following table for the sensor’s image
related modes.
NOTE: Major mode switching (i.e. switching between
master, triggered or slave mode) must be
performed while the sequencer is disabled
(reg_seq_enable = 0x0).
Dynamically reconfiguring the sensor may lead to
corrupted or non-uniformilly exposed frames. For some
reconfigurations, the sensor automatically blanks out the
image data during one frame. Frame blanking is
Table 18. DYNAMIC SENSOR RECONFIGURATION AND FRAME BLANKING
Configuration
Corrupted
Frame
Blanked Out
Frame
Notes
Shutter Mode and Operation
triggered_mode
Do not reconfigure while the sensor is acquiring images. Disable image acquisition by setting
reg_seq_enable = 0x0.
slave_mode
Do not reconfigure while the sensor is acquiring images. Disable image acquisition by setting
reg_seq_enable = 0x0.
subsampling
Enabling: No
Disabling: Yes
Configurable
No
No
mult_timer
No
No
Latency is 1 frame
fr_length
No
No
Latency is 1 frame
exposure
No
No
Latency is 1 frame
mux_gainsw
No
No
Latency configurable by means of gain_lat_comp register
afe_gain
No
No
Latency configurable by means of gain_lat_comp register.
db_gain
No
No
Latency configurable by means of gain_lat_comp register.
roi_active
See Note
No
Windows containing lines previously not read out may lead to corrupted
frames.
roi*_configuration*
See Note
No
Reconfiguring the windows by means of roi*_configuration* may lead to
corrupted frames when configured close to frame boundaries.
It is recommended to (re)configure an inactive window and switch the
roi_active register.
See Notes on roi_active.
black_samples
No
No
If configured within range of configured black lines
auto_blackal_enable
See Note
No
Manual correction factors become instantly active when
auto_blackcal_enable is deasserted during operation.
blackcal_offset
See Note
No
Manual blackcal_offset updates are instantly active.
No
No
Impacts the transmitted CRC
bl_0
No
No
Impacts the Sync channel information, not the Data channels.
img_0
No
No
Impacts the Sync channel information, not the Data channels.
crc_0
No
No
Impacts the Sync channel information, not the Data channels.
tr_0
No
No
Impacts the Sync channel information, not the Data channels.
Configurable with blank_subsampling_ss register.
Frame Timing
black_lines
Exposure Control
Gain
Window/ROI
Black Calibration
CRC Calculation
crc_seed
Sync Channel
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PYTHON 480
Monitor Pins
states from the sequencer. A three−bit register configures the
assignment of the pins as shown in Table 19.
The internal sequencer has two monitor outputs (Pin 44
and Pin 45) that can be used to communicate the internal
Table 19. MONITOR SELECT
Monitor Select
0x0
Monitor Output
Description
No information is provided on the output pins. All outputs are
driven to logic ‘0’
monitor0: ‘0’
monitor1: ‘0’
monitor2: ‘0’
0x1
0x2
0x3
0x4
0x5
0x6
0x7
monitor0: Integration time indication
High during integration
monitor1: ROT indication
High when ROT is active, low outside ROT
monitor2: Dummy line indication
High during dummy lines, low during all other lines
monitor0: Integration time indication
High during integration
monitor1: N/A
N/A
monitor2: N/A
N/A
monitor0: Start of X-readout
Pulse indicating the start of X-readout
monitor1: Black line indication
High during black lines, low during all other lines
monitor2: Dummy line indication
High during dummy lines, low during all other lines
monitor0: Frame start
Pulse indicating the start of a new frame
monitor1: Start of ROT
Pulse indicating the start of ROT
monitor2: Start of X-readout
Pulse indicating the start of X-readout
monitor0: First line indication
High during the first line of each frame, low for all others
monitor1: Start of ROT indication
Pulse indicating the start of ROT
monitor2: ROT inactive
Low when ROT is active, high outside ROT
monitor0: ROT indication
High when ROT is active, low outside ROT
monitor1: Start of X-readout
Pulse indicating the start of X-readout
monitor2: X-readout inactive
Low during X-readout, high outside X-readout
monitor0: Start of X-readout for black lines
Pulse indicating the start of X-readout for black lines
monitor1: Start of X-readout for image lines
Pulse indicating the start of X-readout for image lines
monitor2: Start of X-readout for dummy lines
Pulse indicating the start of X-readout for dummy lines
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PYTHON 480
Sequences of Frame Acquisition with Different
Configurations
When the sequenced readout is not enabled, the first set of
configurations (‘Even configurations’) is applicable. The
second set (‘Odd configurations’) is ignored by the
sequencer.
Frame dependent configurations require multiple
contexts, which are sync’ed upon a start of a new frame. The
following configurations are context switchable:
• FOT program
• ROT programs (only for regular ROT in Global Shutter
Mode (no muxing for black reference ROT programs))
• Integration Time
• Gain (both digital and analog)
• Active ROI Configuration (not the window
configuration themselves)
When enabled, the sequencer shall automatically select
one set of parameters for the even frames and the other set
of parameters for the odd frames.
This operation mode is enabled by means of the
reg_seq_sequence register and can be used in global shutter
modes.
The configurations used for even odd frames are
summarized in Table 20.
Table 20. ODD/EVEN CONFIGURATION
Configuration
Odd Frames
Integration
Time
reg_seq_exposure0
reg_seq_exposure1
FR Length
reg_seq_fr_length0
reg_seq_fr_length1
Mult Timer
reg_seq_mult_timer0
reg_seq_mult_timer1
Gain Stage 1
reg_seq_mux_gains
w0
reg_seq_mux_gainsw1
Gain Stage 2
reg_seq_afe_gain0
reg_seq_afe_gain1
Digital Gain
reg_seq_db_gain0
reg_seq_db_gain1
ROI Active
Configuration
reg_seq_roi_active0
reg_seq_roi_active1
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Even Frames
PYTHON 480
DATA OUTPUT FORMAT
information of ‘ROI 0’ are sent out, starting at position
y0_start. When the line at position y1_start is reached, a
number of lines containing data of ‘ROI 0’ and ‘ROI 1’ are
sent out, until the line position of y0_end is reached. From
there on, only data of ‘ROI 1’ appears on the data output
channels until line position y1_end is reached
During read out of the image data over the data channels,
the sync channel sends out frame synchronization codes
which give information related to the image data that is sent
over the four data output channels.
Each line of a window starts with a Line Start (LS)
indication and ends with a Line End (LE) indication. The
line start of the first line is replaced by a Frame Start (FS);
the line end of the last line is replaced with a Frame End
indication (FE). Each such frame synchronization code is
followed by a window ID (range 0 to 7). For overlapping
windows, the line synchronization codes of the overlapping
windows with lower IDs are not sent out (as shown in the
illustration: no LE/FE is transmitted for the overlapping part
of window 0).
NOTE: In Figure 30, only Frame Start and Frame End
Sync words are indicated in (b). CRC codes are
also omitted from the figure.
The PYTHON 480 image sensor can be configured in LVDS
output mode, which includes one LVDS output channel
together with an LVDS clock output and an LVDS
synchronization output channel. The PYTHON 480 is also
configurable in a CMOS output configuration, which
includes a 10−bit parallel CMOS output together with a
CMOS clock output and ‘frame valid’ and ‘line valid’
CMOS output signals.
LVDS Interface Mode
LVDS Output Channels
The image data output occurs through one LVDS data
channel where a synchronization LVDS channel and an
LVDS output clock signal synchronizes the data.
The one data channel is used to output the image data only.
The sync channel transmits information about the data sent
over the data channel (includes codes indicating black
pixels, normal pixels, and CRC codes).
Frame Format
The frame format is explained by example of the readout
of two (overlapping) windows as shown in Figure 30(a).
The readout of a frame occurs on a line−by−line basis. The
read pointer goes from left to right, bottom to top.
Figure 30 indicates that, after the FOT is completed, the
sensor reads out a number of black lines for black calibration
purposes. After these black lines, the windows are
processed. First a number of lines which only includes
For additional information on the
synchronization codes, refer to
Application Note AND5001.
www.onsemi.com
35
PYTHON 480
y1_end
ROI 1
y0_end
y1_start
ROI 0
y0_start
x0_start
x0_end
x1_start
x1_end
(a)
Integration Time
Handling
Readout
Handling
FOT
É
É
B
L
Reset
N
Exposure Time N
FOT
Readout Frame N-1
ROI
1
ROI 0
FS0
FS1
FOT
FE1
Reset
N+1
É
É
B
L
Exposure Time N+1
FOT
Readout Frame N
ROI
1
ROI 0
FS0
FS1
FOT
FE1
(b)
Figure 30. LVDS Mode: Frame Sync Codes
Figure 31 shows the detail of a black line readout during global or full−frame readout.
Sequencer
Internal State
FOT
ROT
ROT
black
line Ys
ROT
ROT
line Ys+1
line Ye
data channels
sync channel
data channels
sync channel
Training
TR
Training
LS
BL
timeslot
0
timeslot
1
BL
BL
BL
timeslot
157
BL
timeslot
158
BL
LE
timeslot
159
CRC
CRC
timeslot
Figure 31. LVDS Mode: Time Line for Black Line Readout
www.onsemi.com
36
TR
PYTHON 480
Figure 32 shows shows the details of the readout of a number of lines for single window readout, at the beginning of the frame.
Sequencer
Internal State
FOT
ROT
black
ROT
line Ys+1
ROT
line Ys
line Ye
ROT
data channels
sync channel
Training
data channels
TR
sync channel
Training
FS
ID
timeslot
Xstart
IMG
IMG
IMG
timeslot
Xstart + 1
IMG
timeslot
Xend - 2
IMG
IMG
timeslot
Xend - 1
ID
LE
CRC
timeslot
Xend
TR
CRC
timeslot
Figure 32. LVDS Mode: Time Line for Single Window Readout (at the start of a frame)
Figure 33 shows the detail of the readout of a number of lines for readout of two overlapping windows.
Sequencer
Internal State
FOT
ROT
ROT
black
line Ys
ROT
ROT
line Ys+1
line Ye
data channels
sync channel
data channels
sync channel
Training
Training
TR
LS
IDM
IMG
IMG
LS
timeslot
XstartM
IDN
IMG
IMG
IMG LE
timeslot
XstartN
IDN
CRC
TR
timeslot
XendN
Figure 33. LVDS Mode: Time Line Showing the Readout of Two Overlapping Windows
Frame Synchronization
Table 21 shows the structure of the frame synchronization
code. Note that the table shows the default data word
(configurable). If more than one window is active at the
same time, the sync channel transmits the frame
synchronization codes of the window with highest index
only.
Table 21. FRAME SYNCHRONIZATION CODE DETAILS
Sync Word Bit
Position
Register
Address
Default
Value
9:7
N/A
0x4
Frame Sequence Start (FSS). Only sent out when reg_seq_fss_enable is asserted.
9:7
N/A
0x7
Frame Sequence End (FSE). Only sent out when reg_seq_fse_enable is asserted.
9:7
N/A
0x5
Frame start indication
9:7
N/A
0x6
Frame end indication
9:7
N/A
0x1
Line start indication
9:7
N/A
0x2
Line end indication
6:0
117[6:0]
0x2A
Description
These bits indicate that the received sync word is a frame synchronization code. The
value is programmable by a register setting
www.onsemi.com
37
PYTHON 480
• Window Identification
• Data Classification Codes
Frame synchronization codes are always followed by a
3−bit window identification (bits 2:0). This is an integer
number, ranging from 0 to 7, indicating the active window.
If more than one window is active for the current cycle, the
highest window ID is transmitted.
For the remaining cycles, the sync channel indicates the
type of data sent through the data links: black pixel data
(BL), image data (IMG), or training pattern (TR). These
codes are programmable by a register setting. The default
values are listed in Table 22.
Table 22. SYNCHRONIZATION CHANNEL DEFAULT IDENTIFICATION CODE VALUES
Sync Word Bit
Position
Register
Address
Default
Value
9:0
118 [9:0]
0x015
Black pixel data (BL). This data is not part of the image. The black pixel data is used
internally to correct channel offsets.
9:0
119 [9:0]
0x035
Valid pixel data (IMG). The data on the data output channels is valid pixel data (part of the
image).
9:0
125 [9:0]
0x059
CRC value. The data on the data output channels is the CRC code of the finished image
data line.
9:0
126 [9:0]
0x3A6
Training pattern (TR). The sync channel sends out the training pattern which can be
programmed by a register setting.
Description
Training Patterns on Data Channels
training patterns are configurable independent of the
training code on the sync channel as shown in Table 23.
During idle periods, the data channels transmit training
patterns, indicated on the sync channel by a TR code. These
Table 23. TRAINING CODE ON SYNC CHANNEL IN
Sync Word Bit
Position
Register
Address
Default
Value
[9:0]
116 [9:0]
0x3A6
Description
Data channel training pattern. The data output channels send out the training pattern,
which can be programmed by a register setting. The default value of the training pattern
is 0x3A6, which is identical to the training pattern indication code on the sync channel.
Cyclic Redundancy Code
indicates how the kernels are organized. The first kernel
(kernel [0, 0]) is located in the bottom left corner. The pixel
data is transmitted in order. The figures in the following
paragraphs represent the data order for a non−mirrored
readout (i.e. left−to−right readout).
At the end of each line, a CRC code is calculated to allow
error detection at the receiving end. Each data channel
transmits a CRC code to protect the data words sent during
the previous cycles. Idle and training patterns are not
included in the calculation.
The sync channel is not protected. A special character
(CRC indication) is transmitted whenever the data channels
send their respective CRC code.
The polynomial is x10 + x9 + x6 + x3 + x2 + x + 1. The
CRC encoder is seeded at the start of a new line and updated
for every (valid) data word received. The CRC seed is
configurable using the crc_seed register. When ‘0’, the CRC
is seeded by all−‘0’; when ‘1’ it is seeded with all−‘1’.
NOTE: The CRC is calculated for every line. This
implies that the CRC code can protect lines from
multiple windows.
kernel
(403,607)
pixel array
ROI
kernel (x_start,y_start)
kernel
(0,0)
0
1
Data Order: LVDS Interface Version
Figure 34. Kernel Organization in Pixel Array
(Top View)
To read out the image data through the output channel, the
pixel array is organized in kernels. The kernel size is two
pixels in x−direction by one pixel in y−direction. Figure 34
www.onsemi.com
38
PYTHON 480
• Subsampling disabled
Figure 35 shows how a kernel is read out. The pixels are
transferred in order, or in ascending order for normal readout
and descending order for mirrored readout.
kernel N−2
kernel N−1
0
1
pixel # (odd kernel)
3
2
kernel N+1
channel
pixel # (even kernel)
kernel N
MSB
LSB
MSB
LSB
Note: The bit order is always MSB first
10−bit
10−bit
Figure 35. P1−SN/SE/FN: Data Output Order when Subsampling is Disabled
• Subsampling on Monochrome Sensor
neighboring kernels are combined to a single kernel of
4 pixels in the x−direction and one pixel in the y−direction.
Only the pixels at the even pixel positions inside that kernel
are read out.
During subsampling on a monochrome sensor, every
other pixel is read out and the lines are read in a
read-1-skip-1 manner. To read out the image data with
subsampling enabled on a monochrome sensor, two
kernel N−2
0
kernel N
kernel N+1
2
channel
pixel #
kernel N−1
Figure 36. Data Output Order in Subsampling Mode on a Monochrome Sensor
www.onsemi.com
39
PYTHON 480
• Subsampling on Color Sensor
kernels are combined to a single kernel of 4 pixels in the
x−direction and one pixel in the y−direction. Only the pixels
0 and 1 are read out.
During subsampling on a color sensor, lines are read in a
read-2-skip−2 manner. To read out the image data with
subsampling enabled on a color sensor, two neighboring
kernel N−4
kernel N−2
0
kernel N+2
1
channel
pixel #
kernel N
Figure 37. Data Output Order for the LVDS Output Channel in Subsampling Mode on a Color Sensor
• The line_valid indication serves the following needs:
CMOS Interface Mode
♦
CMOS Output Signals
The image data output occurs through a single 10−bit
parallel CMOS data output. A CMOS clock output, ‘frame
valid’ and ‘line valid’ signal synchronizes the output data.
No windowing information is sent out by the sensor.
♦
Frame Format
♦
Frame timing is indicated by means of two signals:
frame_valid and line_valid.
• The frame_valid indication is asserted at the start of a
new frame and remains asserted until the last line of the
frame is completely transmitted.
Sequencer
Internal State
FOT
ROT
black
ROT
line Ys
ROT
While the line_valid indication is asserted, the data
channels contain valid pixel data.
The line valid communicates frame timing as it is
asserted at the start of each line and it is de−asserted
at the end of the line. Low periods indicate the idle
time between lines (ROT).
The data channels transmit the calculated CRC code
after each line. This can be detected as the data
words right after the falling edge of the line valid.
line Ys+1
ROT
line Ye
data channels
frame_valid
line_valid
Figure 38. CMOS Mode: Frame Timing Indication
www.onsemi.com
40
FOT
ROT
black
PYTHON 480
starting at position y0_start. When the line at position
y1_start is reached, a number of lines containing data of
‘ROI 0’ and ‘ROI 1’ are sent out, until the line position of
y0_end is reached. Then, only data of ‘ROI 1’ appears on the
data output until line position y1_end is reached. The
line_valid strobe is not shown in Figure 39.
The frame format is explained with an example of the
readout of two (overlapping) windows as shown in
Figure 39 (a).
The readout of a frame occurs on a line−by−line basis. The
read pointer goes from left to right, bottom to top. Figure 39
(a) and (b) indicate that, after the FOT is finished, a number
of lines which include information of ‘ROI 0’ are sent out,
1280 pixels
1024 pixels
y1_end
ROI1
y0_end
y1_start
ROI0
y0_start
x0_start
x0_end
x1_start
x1_end
(a)
Reset
Exposure Time N
N
Readout Frame N -1
Integration Time
Handling
Readout
Handling
FOT
ROI1
ROI0
Reset
Exposure Time N +1
N+1
Readout Frame N
FOT
FOT
ROI0
ROI1
FOT
FOT
Frame valid
(b)
Figure 39. CMOS Mode: Frame Format to Read Out Image Data
Black Lines
possible to ‘mute’ the frame and/or line valid indications for
the black lines. Refer to Table 24 for black line, frame_valid
and line_valid settings.
Black pixel data is also sent through the data channels. To
distinguish these pixels from the regular image data, it is
Table 24. BLACK LINE FRAME_VALID AND LINE_VALID SETTINGS
bl_frame
_valid_enable
bl_line
_valid_enable
0x1
0x1
The black lines are handled similar to normal image lines. The frame valid indication is asserted
before the first black line and the line valid indication is asserted for every valid (black) pixel.
0x1
0x0
The frame valid indication is asserted before the first black line, but the line valid indication is not
asserted for the black lines. The line valid indication indicates the valid image pixels only. This
mode is useful when one does not use the black pixels and when the frame valid indication needs
to be asserted some time before the first image lines (for example, to precondition ISP pipelines).
0x0
0x1
In this mode, the black pixel data is clearly unambiguously indicated by the line valid indication,
while the decoding of the real image data is simplified.
0x0
0x0
Black lines are not indicated and frame and line valid strobes remain de−asserted. Note however
that the data channels contains the black pixel data and CRC codes (Training patterns are
interrupted).
Description
www.onsemi.com
41
PYTHON 480
• No Subsampling
Data order: CMOS Interface Mode
To read out the image data through the parallel CMOS
output, the pixel array is divided in kernels. The kernel size
is two pixels in x−direction by one pixel in y−direction.
Figure 34 on page 38 indicates how the kernels are
organized.
The pixel data is transmitted in order. The figures in the
following paragraphs represent the data order for a
non−mirrored readout (i.e. left−to−right readout).
kernel N−2
Figure 40 shows the pixel sequence of a kernel which is
read out over the single CMOS output channel. The pixels
are transmitted in order or ascending for a normal readout
and descending for a mirrored readout.
kernel N−1
kernel N
pixel #
0
kernel N+1
1
Figure 40. CMOS Mode: Data Output Order without Subsampling
• Subsampling On Monochrome Sensor
one pixel in the y−direction. Only the pixels at the even pixel
positions inside that kernel are read out. Figure 41 shows the
data order.
To read out the image data with subsampling enabled on
a monochrome sensor, two neighboring kernels are
combined to a single kernel of 4 pixels in the x−direction and
kernel N−2
0
kernel N
kernel N+1
2
channel
pixel #
kernel N−1
Figure 41. CMOS Mode: Data Output Order with Subsampling on a Monochrome Sensor
• Subsampling On Color Sensor
single kernel of 4 pixels in the x−direction and one pixel in
the y−direction. Figure 42 shows the data order.
To read out the image data with subsampling enabled on
a color sensor, two neighboring kernels are combined to a
kernel N−4
0
kernel N
kernel N+2
1
channel
pixel #
kernel N−2
Figure 42. CMOS Mode: Data Output Order with Subsampling on a Color Sensor
www.onsemi.com
42
PYTHON 480
REGISTER MAP
Table 25. REGISTER MAP
Address
Offset
Address
Default
(Hex)
Default
chip_id
0x5004
20484
Chip ID
id
0x5004
20484
Chip ID
reserved
0x0000
0
Reserved
[3:0]
reserved
0x0
0
Reserved
[9:8]
Resolution
0x0
0
Chip Resolution
reserved
0x0
0
Reserved
chip_configuration
0x0000
0
Chip General Configuration
[0]
color
0x0
0
Color/Monochrome Configuration
‘0’: Monochrome
‘1’: Color
[1]
reserved
0x0
0
Reserved
[15:2]
reserved
0x0
0
Reserved
Bit Field
Register Name
Description
Type
Chip ID [Block Offset: 0]
0
0
[15:0]
1
1
[11:10]
2
2
Status
Status
RW
Reset Generator [Block Offset: 8]
0
1
8
soft_reset_pll
0x0099
153
PLL Soft Reset Configuration
[3:0]
pll_soft_reset
0x9
9
PLL Reset
0x9: Soft Reset State
others: Operational
[7:4]
pll_lock_soft_reset
0x9
9
PLL Lock Detect Reset
0x9: Soft Reset State
others: Operational
soft_reset_cgen
0x0009
9
Clock Generator Soft Reset
cgen_soft_reset
0x9
9
Clock Generator Reset
0x9: Soft Reset State
others: Operational
soft_reset_analog
0x0999
2457
Analog Block Soft Reset
[3:0]
mux_soft_reset
0x9
9
Column MUX Reset
0x9: Soft Reset State
others: Operational
[7:4]
afe_soft_reset
0x9
9
AFE Reset
0x9: Soft Reset State
others: Operational
[11:8]
ser_soft_reset
0x9
9
Serializer Reset
0x9: Soft Reset State
others: Operational
9
[3:0]
2
10
RW
RW
RW
PLL [Block Offset: 16]
0
1
16
power_down
0x0004
4
PLL Configuration
[0]
pwd_n
0x0
0
PLL Power Down
’0’: Power Down,
’1’: Operational
[1]
enable
0x0
0
PLL Enable
’0’: disabled,
’1’: enabled
[2]
bypass
0x1
1
PLL Bypass
’0’: PLL Active,
’1’: PLL Bypassed
17
reserved
0x2113
8467
Reserved
[7:0]
reserved
0x13
19
Reserved
[12:8]
reserved
0x1
1
Reserved
[14:13]
reserved
0x1
1
Reserved
www.onsemi.com
43
RW
RW
PYTHON 480
Table 25. REGISTER MAP (continued)
Address
Offset
Address
Bit Field
Default
(Hex)
Default
config1
0x0000
0
IO Configuration
Register Name
Description
Type
I/O [Block Offset: 20]
0
20
clock_in_pwd_n
0x0
0
Power down Clock Input
[9:8]
[0]
reserved
0x0
0
Reserved
[10]
reserved
0x0
0
Reserved
pll_lock
0x0000
0
PLL Lock Indication
lock
0x0
0
PLL Lock Indication
reserved
0x2280
8832
Reserved
[7:0]
reserved
0x80
128
Reserved
[10:8]
reserved
0x2
2
Reserved
[14:12]
reserved
0x2
2
Reserved
RW
PLL Lock Detector [Block Offset: 24]
0
24
2
26
[0]
3
27
reserved
0x3D2D
15661
Reserved
[7:0]
reserved
0x2D
45
Reserved
[15:8]
reserved
0x3D
61
Reserved
config0
0x2014
8212
Clock Generator Configuration
[0]
enable_analog
0x0
0
Enable analogue clocks
‘0’: disabled,
‘1’: enabled
[1]
enable_log
0x0
0
Enable logic clock
‘0’: disabled,
‘1’: enabled
[2]
select_pll
0x1
1
Input Clock Selection
‘0’: Select LVDS clock input,
‘1’: Select PLL clock input
[3]
adc_mode
0x0
0
Set operation mode of CGEN block
‘0’: divide by 5 mode (10-bit mode)
[4]
enable_clkgate
0x1
1
Clock gate on master distribution
‘0’: Clock active
‘1’: Clock inactive (gated)
[11:8]
reserved
0x0
0
Reserved
[14:12]
reserved
0x2
2
Reserved
config0
0x0000
0
Clock Generator Configuration
enable
0x0
0
Logic General Enable Configuration
‘0’: Disable
‘1’: Enable
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
image_core_config0
0x0000
0
Image Core Configuration
[0]
imc_pwd_n
0x0
0
Image Core Power Down
‘0’: powered down,
‘1’: powered up
[1]
mux_pwd_n
0x0
0
Column Multiplexer Power Down
‘0’: powered down,
‘1’: powered up
[2]
colbias_enable
0x0
0
Bias Enable
‘0’: disabled
‘1’: enabled
image_core_config1
0x085A
2138
Image Core Configuration
Status
RW
RW
Clock Generator [Block Offset: 32]
0
32
RW
General Logic [Block Offset: 34]
0
34
[0]
0
38
[15:0]
RW
RW
Image Core [Block Offset: 40]
0
1
40
41
www.onsemi.com
44
RW
RW
PYTHON 480
Table 25. REGISTER MAP (continued)
Address
Offset
2
3
Address
Bit Field
Register Name
Default
(Hex)
Default
Description
[3:0]
reserved
0xA
10
Reserved
[7:4]
reserved
0x5
5
Reserved
[10:8]
reserved
0x0
0
Reserved
[12:11]
reserved
0x1
1
Reserved
[13]
reserved
0x0
0
Reserved
[14]
reserved
0x0
0
Reserved
[15]
reserved
0x0
0
Reserved
reserved
0x0003
3
Reserved
[0]
reserved
0x1
1
Reserved
[1]
reserved
0x1
1
Reserved
[6:4]
reserved
0x0
0
Reserved
[10:8]
reserved
0x0
0
Reserved
[15:12]
reserved
0x0
0
Reserved
42
43
reserved
0x0508
1288
Reserved
[0]
reserved
0x0
0
Reserved
[1]
reserved
0x0
0
Reserved
[2]
reserved
0x0
0
Reserved
[3]
reserved
0x1
1
Reserved
[6:4]
reserved
0x0
0
Reserved
[7]
reserved
0x0
0
Reserved
[11:8]
reserved
0x5
5
Reserved
[15:12]
reserved
0x0
0
Reserved
power_down
0x0000
0
AFE Configuration
pwd_n
0x0
0
Power down for AFE’s
‘0’: powered down,
‘1’: powered up
power_down
0x0000
0
Bias Power Down Configuration
pwd_n
0x0
0
Power down bandgap
‘0’: powered down,
‘1’: powered up
configuration
0xF8CB
63691
Bias Configuration
extres
0x1
1
External Resistor Selection
‘0’: internal resistor,
‘1’: external resistor
[3:1]
reserved
0x5
5
Reserved
Type
RW
RW
AFE [Block Offset: 48]
0
48
[0]
RW
Bias [Block Offset: 64]
0
64
[0]
1
65
[0]
2
3
[7:4]
reserved
0xC
12
Reserved
[11:8]
reserved
0x8
8
Reserved
[15:12]
reserved
0xF
15
Reserved
reserved
0x53C8
21448
Reserved
[3:0]
reserved
0x8
8
Reserved
[7:4]
reserved
0xC
12
Reserved
[14:8]
reserved
0x53
83
Reserved
66
67
reserved
0x8788
34696
Reserved
[3:0]
reserved
0x8
8
Reserved
[7:4]
reserved
0x8
8
Reserved
www.onsemi.com
45
RW
RW
RW
RW
PYTHON 480
Table 25. REGISTER MAP (continued)
Address
Offset
4
5
6
7
Address
Bit Field
Register Name
Default
(Hex)
Default
Description
[11:8]
reserved
0x7
7
Reserved
[15:12]
reserved
0x8
8
Reserved
lvds_bias
0x0085
133
LVDS Bias Configuration
[3:0]
lvds_ibias
0x5
5
LVDS Ibias
[7:4]
lvds_iref
0x8
8
LVDS Iref
reserved
0x0088
2184
Reserved
[3:0]
reserved
0x8
8
Reserved
[7:4]
reserved
0x8
8
Reserved
[11:8]
reserved
0x8
8
Reserved
reserved
0x4111
16657
Reserved
[3:0]
reserved
0x1
1
Reserved
68
69
70
[7:4]
reserved
0x1
1
Reserved
[11:8]
reserved
0x1
1
Reserved
[15:12]
reserved
0x4
4
Reserved
reserved
0x9788
38792
Reserved
reserved
0x9788
38792
Reserved
configuration
0x3330
13104
Charge Pump Configuration
[0]
reserved
0x0
0
Reserved
[1]
reserved
0x0
0
Reserved
[2]
reserved
0x0
0
Reserved
71
[15:0]
Type
RW
RW
RW
RW
Charge Pump [Block Offset: 72]
0
0
1
72
[6:4]
reserved
0x3
3
Reserved
[10:8]
reserved
0x3
3
Reserved
[14:12]
reserved
0x3
3
Reserved
80
reserved
0x0000
0
Reserved
[1:0]
reserved
0x0
0
Reserved
[3:2]
reserved
0x0
0
Reserved
[5:4]
reserved
0x0
0
Reserved
[7:6]
reserved
0x0
0
Reserved
[9:8]
reserved
0x0
0
Reserved
reserved
0x8881
34945
Reserved
reserved
0x8881
34945
Reserved
enable
0x0000
0
Temperature Sensor Configuration
[0]
reserved
0x0
0
Reserved
[1]
reserved
0x0
0
Reserved
[2]
reserved
0x0
0
Reserved
[3]
reserved
0x0
0
Reserved
[4]
reserved
0x0
0
Reserved
[5]
reserved
0x0
0
Reserved
offset
0x0
0
Temperature Offset (signed)
temp
0x0000
0
Temperature Sensor Status
temp
0x00
0
Temperature Readout
reserved
0x0000
0
Reserved
81
[15:0]
RW
RW
RW
Temperature Sensor [Block Offset: 96]
0
96
[13:8]
1
97
0
104
[7:0]
www.onsemi.com
46
RW
Status
RW
PYTHON 480
Table 25. REGISTER MAP (continued)
Address
Offset
Address
Bit Field
[15:0]
1
2
105
Default
reserved
0x0
0
Reserved
Description
reserved
0x0000
0
Reserved
[1:0]
reserved
0x0
0
Reserved
[5:2]
reserved
0x0
0
Reserved
[7]
reserved
0x0
0
Reserved
[9:8]
reserved
0x0
0
Reserved
[13:10]
reserved
0x0
0
Reserved
[15]
reserved
0x0
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
power_down
0x0000
0
LVDS Power Down Configuration
[0]
clock_out_pwd_n
0x0
0
Power down for Clock Output.
‘0 ’: powered down,
‘1’: powered up
[1]
sync_pwd_n
0x0
0
Power down for Sync channel
‘0’: powered down,
‘1’: powered up
[2]
data_pwd_n
0x0
0
Power down for data channels (4 channels)
‘0’: powered down,
‘1’: powered up
trainingpattern
0x03A6
934
Data Formating - Training Pattern
trainingpattern
0x3A6
934
Training pattern sent on Data channels during
idle mode. This data is used to perform word
alignment on the LVDS data channels.
sync_code0
0x002A
42
LVDS Power Down Configuration
frame_sync_0
0x02A
42
Frame Sync Code LSBs - Even kernels
sync_code1
0x0015
21
Data Formating - BL Indication
bl_0
0x015
21
Black Pixel Identification Sync Code - Even
kernels
sync_code2
0x0035
53
Data Formating - IMG Indication
img_0
0x035
53
Valid Pixel Identification Sync Code - Even
kernels
sync_code3
0x0025
37
Data Formating - IMG Indication
ref_0
0x025
37
Reference Pixel Identification Sync Code Even kernels
sync_code4
0x002A
42
LVDS Power Down Configuration
frame_sync_1
0x02A
42
Frame Sync Code LSBs - Odd kernels
sync_code5
0x0015
21
Data Formating - BL Indication
bl_1
0x015
21
Black Pixel Identification Sync Code Odd kernels
sync_code6
0x0035
53
Data Formating - IMG Indication
img_1
0x035
53
Valid Pixel Identification Sync Code Odd kernels
sync_code7
0x0025
37
Data Formating - IMG Indication
ref_1
0x025
37
Reference Pixel Identification Sync Code Odd kernels
106
[15:0]
3
Default
(Hex)
Register Name
107
[10:0]
Type
RW
RW
RW
Serializers/LVDS/IO [Block Offset: 112]
0
112
RW
Sync Words [Block Offset: 116]
4
116
[9:0]
5
117
[6:0]
6
118
[9:0]
7
119
[9:0]
8
120
[9:0]
9
121
[6:0]
10
122
[9:0]
11
123
[9:0]
12
124
[9:0]
www.onsemi.com
47
RW
RW
RW
RW
RW
RW
RW
RW
RW
PYTHON 480
Table 25. REGISTER MAP (continued)
Address
Offset
Address
13
125
14
126
15
127
Default
(Hex)
Default
sync_code8
0x0059
89
Data Formating - CRC Indication
crc
0x059
89
CRC Value Identification Sync Code
sync_code9
0x03A6
934
Data Formating - TR Indication
tr
0x3A6
934
Training Value Identification Sync Code
reserved
0x02AA
682
Reserved
reserved
0x2AA
682
Reserved
blackcal
0x4714
18196
Black Calibration Configuration
[7:0]
black_offset
0x014
20
Desired black level at output
[10:8]
black_samples
0x7
7
Black pixels taken into account for black
calibration.
Total samples = 2**black_samples
[14:11]
reserved
0x8
8
Reserved
[15]
crc_seed
0x0
0
CRC Seed
‘0’: All-0
‘1’: All-1
general_configuration
0x0001
1
Black Calibration and Data Formating
Configuration
auto_blackcal_enable
0x1
1
Automatic blackcalibration is enabled when 1,
bypassed when 0
[9:1]
blackcal_offset
0x00
0
Black Calibration offset used when auto_black_cal_en = ‘0’.
[10]
blackcal_offset_dec
0x0
0
blackcal_offset is added when 0, subtracted
when 1
[11]
reserved
0x0
0
Reserved
[12]
reserved
0x0
0
Reserved
[13]
reserved
0x0
0
Reserved
[14]
ref_mode
0x0
0
Data contained on reference lines:
‘0’: reference pixels
‘1’: black average for the corresponding data
channel
[15]
ref_bcal_enable
0x0
0
Enable black calibration on reference lines
‘0’: Disabled
‘1’: Enabled
general_configuration1
0x000F
15
Data Formating - Training Pattern
bl_frame_valid_enable
0x1
1
Assert frame_valid for black lines when ‘1’,
gate frame_valid for black lines when ‘0’.
Parallel output mode only.
bl_line_valid_enable
0x1
1
Assert line_valid for black lines when ‘1’, gate
line_valid for black lines when ‘0’.
Parallel output mode only.
ref_frame_valid_enable
0x1
1
Assert frame_valid for ref lines when ‘1’, gate
frame_valid for black lines when ‘0’.
Parallel output mode only.
[3]
ref_line_valid_enable
0x1
1
Assert line_valid for ref lines when ‘1’, gate
line_valid for black lines when ‘0’.
Parallel output mode only.
[4]
frame_valid_mode
0x0
0
Behaviour of frame_valid strobe between
overhead lines when [0] and/or [1] is
deasserted:
‘0’: retain frame_valid deasserted between
lines
‘1’: assert frame_valid between lines
[5]
invert_bitstream
0x0
0
Negative Image
‘0’: Normal
‘1’: Negative
Bit Field
[9:0]
[9:0]
[9:0]
Register Name
Description
Type
RW
RW
RW
Data Block [Block Offset: 128]
0
1
128
129
[0]
2
130
[0]
[1]
[2]
www.onsemi.com
48
RW
RW
RW
PYTHON 480
Table 25. REGISTER MAP (continued)
Address
Offset
8
Address
Bit Field
16
144
Default
Description
data_negedge
0x0
0
Clock−Data Relation
‘0’: data is clocked out on the rising edge of
the related clock
‘1’: data is clocked out on the falling edge of
the related clock
[9]
reserved
0x0
0
Reserved
blackcal_error0
0x0000
0
Black Calibration Status
blackcal_error[1:0]
0x0000
0
Black Calibration Error. This flag is set when
not enough black samples are availlable.
Black Calibration shall not be valid.
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
test_configuration
0x0010
16
Data Formating Test Configuration
[0]
testpattern_en
0x0
0
Insert synthesized testpattern when ‘1’
[1]
inc_testpattern
0x0
0
Incrementing testpattern when ‘1’, constant
testpattern when ’0’
[2]
prbs_en
0x0
0
Insert PRBS when ‘1’
[3]
frame_testpattern
0x0
0
Frame test patterns when ‘1’, unframed
testpatterns when ‘0’
testpattern
0x1
1
Testpattern used when testpatterns_en = ‘1’
[1:0]
140
Default
(Hex)
[8]
136
12
Register Name
[15:0]
[13:4]
Type
Status
RW
RW
AEC [Block Offset: 160]
0
1
160
configuration
0x0010
16
AEC Configuration
[0]
enable
0x0
0
AEC Enable
[1]
restart_filter
0x0
0
Restart AEC filter
[2]
freeze
0x0
0
Freeze AEC filter and enforcer gains
[3]
pixel_valid
0x0
0
Use every pixel from channel when 0, every
4th pixel when 1
[4]
amp_pri
0x1
1
Column amplifier gets higher priority than AFE
PGA in gain distribution if 1. Vice versa if 0
intensity
0x60B8
24760
AEC Configuration
desired_intensity
0xB8
184
Target average intensity
reserved
0x018
24
Reserved
red_scale_factor
0x0080
128
Red Scale Factor
red_scale_factor
0x80
128
Red Scale Factor
3.7 unsigned
green1_scale_factor
0x0080
128
Green1 Scale Factor
green1_scale_factor
0x80
128
Green1 Scale Factor
3.7 unsigned
green2_scale_factor
0x0080
128
Green2 Scale Factor
green2_scale_factor
0x80
128
Green2 Scale Factor
3.7 unsigned
blue_scale_factor
0x0080
128
Blue Scale Factor
blue_scale_factor
0x80
128
Blue Scale Factor
3.7 unsigned
reserved
0x03FF
1023
Reserved
reserved
0x03FF
1023
Reserved
reserved
0x0800
2048
Reserved
[1:0]
reserved
0x0
0
Reserved
[3:2]
reserved
0x0
0
Reserved
[15:4]
reserved
0x080
128
Reserved
161
[9:0]
[15:10]
2
162
[9:0]
3
163
[9:0]
4
164
[9:0]
5
165
[9:0]
6
166
7
167
[15:0]
www.onsemi.com
49
RW
RW
RW
RW
RW
RW
RW
RW
PYTHON 480
Table 25. REGISTER MAP (continued)
Address
Offset
Address
8
168
9
169
Default
(Hex)
Default
min_exposure
0x0001
1
Minimum Exposure Time
min_exposure
0x0001
1
Minimum Exposure Time
min_gain
0x0800
2048
Minimum Gain
[1:0]
min_mux_gain
0x0
0
Minimum Column Amplifier Gain
[3:2]
min_afe_gain
0x0
0
Minimum AFE PGA Gain
[15:4]
min_digital_gain
0x080
128
Minimum Digital Gain
5.7 unsigned
max_exposure
0x03FF
1023
Maximum Exposure Time
max_exposure
0x03FF
1023
Maximum Exposure Time
Bit Field
[15:0]
10
170
[15:0]
11
12
13
14
171
max_gain
0x1001
4097
Maximum Gain
max_mux_gain
0x1
1
Maximum Column Amplifier Gain
[3:2]
max_afe_gain
0x0
0
Maximum AFE PGA Gain
[15:4]
max_digital_gain
0x100
256
Maximum Digital Gain
5.7 unsigned
reserved
0x0083
131
Reserved
[7:0]
reserved
0x083
131
Reserved
[13:8]
reserved
0x00
0
Reserved
[15:14]
reserved
0x0
0
Reserved
reserved
0x2824
10276
Reserved
[7:0]
reserved
0x024
36
Reserved
[15:8]
reserved
0x028
40
Reserved
reserved
0x2A96
10902
Reserved
[3:0]
reserved
0x6
6
Reserved
[7:4]
reserved
0x9
9
Reserved
[11:8]
reserved
0xA
10
Reserved
[15:12]
reserved
0x2
2
Reserved
reserved
0x0080
128
Reserved
reserved
0x080
128
Reserved
reserved
0x00F1
241
Reserved
reserved
0xF1
241
Reserved
reserved
0x0100
256
Reserved
reserved
0x100
256
Reserved
reserved
0x0080
128
Reserved
reserved
0x080
128
Reserved
reserved
0x00AA
170
Reserved
reserved
0x0AA
170
Reserved
reserved
0x0100
256
Reserved
reserved
0x100
256
Reserved
reserved
0x0155
341
Reserved
reserved
0x155
341
Reserved
total_pixels0
0x0000
0
AEC Status
total_pixels[15:0]
0x0000
0
Total number of pixels sampled for Average,
LSB
total_pixels1
0x0000
0
AEC Status
total_pixels[23:16]
0x0
0
Total number of pixels sampled for Average,
MSB
173
174
175
16
176
[9:0]
[9:0]
17
177
[9:0]
18
178
[9:0]
19
179
20
180
21
181
[9:0]
[9:0]
[9:0]
24
184
[15:0]
25
Description
[1:0]
172
15
Register Name
185
[7:0]
www.onsemi.com
50
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Status
Status
PYTHON 480
Table 25. REGISTER MAP (continued)
Address
Offset
Address
26
186
27
Default
(Hex)
Default
average_status
0x0000
0
ASE Status
[9:0]
average
0x000
0
AEC Average Status
[12]
avg_locked
0x0
0
AEC Average Lock Status
exposure_status
0x0000
0
ASE Status
exposure
0x0000
0
AEC Exposure Status
gain_status
0x0000
0
ASE Status
[1:0]
mux_gain
0x0
0
AEC MUX Gain Status
[3:2]
afe_gain
0x0
0
AEC AFE Gain Status
[15:4]
digital_gain
0x000
0
AEC Digital Gain Status
5.7 unsigned
reserved
0x0000
0
Reserved
[12:0]
reserved
0x000
0
Reserved
[13]
reserved
0x0
0
Reserved
general_configuration
0x0002
2
Sequencer General Configuration
[0]
enable
0x0
0
Enable sequencer
‘0’: Idle,
‘1’: enabled
[1]
fast_startup
0x1
1
Fast startup
‘0’: First frame is full frame (blanked out)
‘1’: Reduced startup time
[2]
reserved
0x0
0
Reserved
[3]
reserved
0x0
0
Reserved
[4]
triggered_mode
0x0
0
Triggered Mode Selection
‘0’: Normal Mode,
‘1’: Triggered Mode
[5]
slave_mode
0x0
0
Master/Slave Selection
‘0’: master,
‘1’: slave
[6]
reserved
0x0
0
Reserved
[7]
subsampling
0x0
0
Subsampling mode selection
‘0’: no subsampling,
‘1’: subsampling
Bit Field
187
[15:0]
28
29
188
189
Register Name
Description
Type
Status
Status
Status
Status
Sequencer [Block Offset: 192]
0
2
192
[8]
reserved
0x0
0
Reserved
[10]
roi_aec_enable
0x0
0
Enable windowing for AEC Statistics.
‘0’: Subsample all windows
‘1’: Subsample configured window
[13:11]
monitor_select
0x0
0
Control of the monitor pins
[14]
reserved
0x0
0
Reserved
[15]
sequence
0x0
0
Enable a sequenced readout with different
parameters for even and odd frames
integration_control
0x00E4
228
Integration Control
[0]
reserved
0x0
0
Reserved
[1]
reserved
0x0
0
Reserved
[2]
fr_mode
0x1
1
Representation of fr_length.
‘0’: reset length
‘1’: frame length
[3]
reserved
0x0
0
Reserved
[4]
int_priority
0x0
0
Integration Priority
‘0’: Frame readout has priority over integration
‘1’: Integration End has priority over frame
readout
194
www.onsemi.com
51
RW
RW
PYTHON 480
Table 25. REGISTER MAP (continued)
Address
Offset
3
Address
Bit Field
6
1
The current frame will be completed when the
sequencer is disabled and halt_mode = ‘1’.
When ‘0’, the sensor stops immediately when
disabled, without finishing the current frame.
[6]
fss_enable
0x1
1
Generation of Frame Sequence Start Sync
code (FSS)
‘0’: No generation of FSS
‘1’: Generation of FSS
[7]
fse_enable
0x1
1
Generation of Frame Sequence End Sync
code (FSE)
‘0’: No generation of FSE
‘1’: Generation of FSE
[8]
reverse_y
0x0
0
Reverse readout
‘0’: bottom to top readout
‘1’: top to bottom readout
[9]
reverse_x
0x0
0
Reverse readout (X−direction)
‘0’: left to right
‘1’: right to left
[11:10]
subsampling_mode
0x0
0
Subsampling mode
“00”: Subsampling in x and y (VITA
compatible)
“01”: Subsampling in x, not y
“10”: Subsampling in y, not x
“11”: Subsampling in x an y
[13:12]
reserved
0x0
0
Reserved
[14]
reserved
0x0
0
Reserved
[15]
reserved
0x0
0
Reserved
roi_active0_0
0x0001
1
Active ROI Selection
roi_active0
0x01
1
Active ROI Selection
[0] Roi0 Active
[1] Roi1 Active
...
[3] Roi3 Active
black_lines
0x0104
260
Black Line Configuration
[7:0]
black_lines
0x04
4
Number of black lines. Minimum is 1.
Range 1-255
[12:8]
gate_first_line
0x1
1
Blank out first lines
0: no blank
1-31: blank 1-31 lines
init_reset_length
0x0040
64
Initial Reset Length
init_reset_length
0x0040
64
Initial Reset Length in Fast Startup Mode
(reg_sec_fast_startup = 0x1)
mult_timer0
0x0001
1
Exposure/Frame Rate Configuration
mult_timer0
0x0001
1
Mult Timer (Global shutter only)
Defines granularity (unit = 1/PLL clock) of
exposure and reset_length
fr_length0
0x0000
0
Exposure/Frame Rate Configuration
fr_length0
0x0000
0
Frame/Reset length (Global shutter only)
Reset length when fr_mode = ‘0’,
Frame Length when fr_mode = ‘1’
Granularity defined by mult_timer
exposure0
0x0000
0
Exposure/Frame Rate Configuration
exposure0
0x0000
0
Exposure Time
Granularity defined by mult_timer
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
195
197
198
199
200
[15:0]
9
201
[15:0]
10
202
11
203
Description
0x1
[15:0]
8
Default
halt_mode
[15:0]
7
Default
(Hex)
[5]
[3:0]
5
Register Name
[15:0]
[15:0]
www.onsemi.com
52
Type
RW
RW
RW
RW
RW
RW
RW
RW
PYTHON 480
Table 25. REGISTER MAP (continued)
Address
Offset
Address
12
204
Default
(Hex)
Default
gain_configuration0
0x01E1
481
Gain Configuration
[4:0]
mux_gainsw0
0x01
1
Column Gain Setting
[12:5]
afe_gain0
0xF
15
AFE Programmable Gain Setting
gain_lat_comp
0x0
0
Postpone gain update by 1 frame when ‘1’ to
compensate for exposure time updates
latency.
Gain is applied at start of next frame if ‘0’
digital_gain
_configuration0
0x0080
128
Gain Configuration
db_gain0
0x080
128
Digital Gain
Bit Field
[13]
13
205
[11:0]
14
15
206
17
sync_configuration
0x037A
890
Synchronization Configuration
sync_black_lines
0x1
1
Update of black_lines will not be sync’ed at start
of frame when ‘0’
[3]
sync_exposure
0x1
1
Update of exposure will not be sync’ed at start of
frame when ‘0’
[4]
sync_gain
0x1
1
Update of gain settings (gain_sw, afe_gain) will
not be sync’ed at start of frame when ‘0’
[5]
sync_roi
0x1
1
Update of roi updates (active_roi) will not be
sync’ed at start of frame when ‘0’
[6]
sync_ref_lines
0x1
1
Update of ref_lines will not be sync’ed at start of
frame when ‘0’
[8]
blank_roi_switch
0x1
1
Blank first frame after ROI switching
[9]
blank
_subsampling_ss
0x1
1
Blank first frame after subsampling mode
‘0’: No blanking
‘1’: Blanking
[10]
exposure_sync_mode
0x0
0
When ‘0’, exposure configurations are sync’ed
at the start of FOT. When ‘1’, exposure
configurations sync is disabled (continuously
syncing). This mode is only relevant for Triggered Global - master mode, where the exposure configurations are sync’ed at the start
of exposure rather than the start of FOT. For
all other modes it should be set to ‘0’.
Note: Sync is still postponed if
sync_exposure=‘0’.
ref_lines
0x0000
0
Reference Line Configuration
ref_lines
0x00
0
Number of Reference Lines
0-255
reserved
0xC900
51456
Reserved
[7:0]
reserved
0x00
0
Reserved
[15:8]
reserved
0xC9
201
Reserved
207
208
209
reserved
0x0004
4
Reserved
[0]
reserved
0x0
0
Reserved
[2]
reserved
0x1
1
Reserved
xsm_delay
0x00
0
Delay between ROT end and X−readout
reserved
0x0049
73
Reserved
[0]
reserved
0x1
1
Reserved
[1]
reserved
0x0
0
Reserved
[2]
reserved
0x0
0
Reserved
[15:8]
19
20
Description
[1]
[7:0]
16
Register Name
211
[3]
reserved
0x1
1
Reserved
[6:4]
reserved
0x4
4
Reserved
[15:8]
reserved
0x0
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
212
[9:0]
www.onsemi.com
53
Type
RW
RW
RW
RW
RW
RW
RW
RW
PYTHON 480
Table 25. REGISTER MAP (continued)
Address
Offset
Address
Default
(Hex)
Default
reserved
0x00
0
Reserved
reserved
0x025F
607
Reserved
reserved
0x025F
607
Reserved
reserved
0x0100
256
Reserved
reserved
0x00
0
Reserved
reserved
0x191F
6431
Reserved
[0]
reserved
0x1
1
Reserved
[1]
reserved
0x1
1
Reserved
[2]
reserved
0x1
1
Reserved
[3]
reserved
0x1
1
Reserved
[4]
reserved
0x1
1
Reserved
[5]
reserved
0x0
0
Reserved
[6]
reserved
0x0
0
Reserved
[8]
reserved
0x1
1
Reserved
[9]
reserved
0x0
0
Reserved
[10]
reserved
0x0
0
Reserved
Bit Field
[15]
21
213
[9:0]
22
214
[7:0]
23
24
215
26
27
28
29
[11]
reserved
0x1
1
Reserved
reserved
0x1
1
Reserved
[13]
reserved
0x0
0
Reserved
[14]
reserved
0x0
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x00
0
Reserved
216
217
reserved
0x4848
18504
Reserved
[6:0]
reserved
0x48
72
Reserved
[14:8]
reserved
0x48
72
Reserved
218
reserved
0x4848
18504
Reserved
[6:0]
reserved
0x48
72
Reserved
[14:8]
reserved
0x48
72
Reserved
reserved
0x005C
92
Reserved
[6:0]
reserved
0x05C
92
Reserved
[14:8]
reserved
0x00
0
Reserved
reserved
0x3624
13860
Reserved
[6:0]
reserved
0x24
36
Reserved
[14:8]
reserved
0x36
54
Reserved
reserved
0x0036
54
Reserved
[6:0]
reserved
0x36
54
Reserved
[14:8]
reserved
0x0
0
Reserved
reserved
0x0
reserved
0x0
0
Reserved
219
220
221
30
[14:8]
32
Description
[12]
[6:0]
25
Register Name
224
Reserved
reserved
0x3E07
15879
Reserved
[3:0]
reserved
0x7
7
Reserved
[7:4]
reserved
0x00
0
Reserved
[8]
reserved
0x0
0
Reserved
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54
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
PYTHON 480
Table 25. REGISTER MAP (continued)
Address
Offset
33
34
35
36
Address
Bit Field
1
Reserved
[10]
reserved
0x1
1
Reserved
[11]
reserved
0x1
1
Reserved
[12]
reserved
0x1
1
Reserved
[13]
reserved
0x1
1
Reserved
reserved
0x5EF1
24305
Reserved
[4:0]
reserved
0x11
17
Reserved
[9:5]
reserved
0x17
23
Reserved
[14:10]
reserved
0x17
23
Reserved
[15]
reserved
0x0
0
Reserved
reserved
0x6000
24576
Reserved
[4:0]
reserved
0x00
0
Reserved
[9:5]
reserved
0x00
0
Reserved
[14:10]
reserved
0x18
24
Reserved
[15]
reserved
0x0
0
Reserved
reserved
0x0000
0
Reserved
[0]
reserved
0x0
0
Reserved
[1]
reserved
0x0
0
Reserved
[2]
reserved
0x0
0
Reserved
[3]
reserved
0x0
0
Reserved
[4]
reserved
0x0
0
Reserved
roi_active0_1
0x0001
1
Active ROI Selection
roi_active1
0x01
1
Active ROI Selection
[0] ROI0 Active
[1] ROI1 Active
[2] ROI2 Active
[3] ROI3 Active
reserved
0x0001
1
Reserved
reserved
0x0001
1
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
reserved
0x0000
0
Reserved
226
227
228
230
231
[15:0]
232
41
233
42
234
[15:0]
[15:0]
[15:0]
43
44
235
reserved
0x01E3
483
Reserved
[4:0]
reserved
0x03
3
Reserved
[12:5]
reserved
0xF
15
Reserved
reserved
0x0080
128
Reserved
reserved
0x080
128
Reserved
reserved
0x0000
0
Reserved
reserved
0x0
0
Reserved
reserved
0x1081
4225
Reserved
reserved
0x01
1
Reserved
236
[11:0]
47
239
[1:0]
58
Description
0x1
225
40
Default
reserved
[15:0]
39
Default
(Hex)
[9]
[3:0]
38
Register Name
250
[4:0]
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55
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
PYTHON 480
Table 25. REGISTER MAP (continued)
Address
Offset
59
60
61
62
63
Address
Bit Field
Register Name
Default
(Hex)
Default
Description
[9:5]
reserved
0x04
4
Reserved
[14:10]
reserved
0x04
4
Reserved
reserved
0x030F
783
Reserved
[7:0]
reserved
0xF
15
Reserved
[15:8]
reserved
0x3
3
Reserved
reserved
0x0601
1537
Reserved
[7:0]
reserved
0x1
1
Reserved
[15:8]
reserved
0x6
6
Reserved
roi_aec_configuration0
0xC900
51456
AEC ROI Configuration
[7:0]
x_start
0x00
0
AEC ROI X Start Configuration (used for AEC
statistics when roi_aec_enable=‘1’) (bits 8..1)
[15:8]
x_end
0x0C9
201
AEC ROI X End Configuration (used for AEC
statistics when roi_aec_enable=‘1’) (bits 8..1)
roi_aec_configuration1
0x9700
0
AEC ROI Configuration
[7:0]
y_start
0x00
0
AEC ROI Y Start Configuration (used for AEC
statistics when roi_aec_enable=‘1’) (bits 9..2)
[15:8]
x_end
0x97
151
AEC ROI End Configuration (used for AEC
statistics when roi_aec_enable=‘1’) (bits 9..2)
roi_aec_configuration2
0x00C4
0
AEC ROI Configuration
[0]
x_start(0)
0x0
0
AEC ROI Y End Configuration (used for AEC
statistics when roi_aec_enable=‘1’) (bit 0)
[2]
x_end(0)
0x1
1
AEC ROI End Configuration (used for AEC
statistics when roi_aec_enable=‘1’) (bit 0)
[5:4]
y_start(1:0)
0x0
0
AEC ROI End Configuration (used for AEC
statistics when roi_aec_enable=‘1’) (bits 1..0)
[7:6]
y_end(1:0)
0x3
3
AEC ROI End Configuration (used for AEC
statistics when roi_aec_enable=‘1’) (bits 1..0)
roi0_configuration0
0xC900
51456
ROI Configuration
[7:0]
x_start
0x00
0
ROI 0 − X Start Configuration (bits 8..1)
[15:8]
x_end
0xC9
201
ROI 0 − X End Configuration (bits 8..1)
roi0_configuration1
0x9700
38656
ROI Configuration
[7:0]
y_start
0x00
0
ROI 0 − Y Start Configuration (bits 9..2)
[15:8]
y_end
0x97
151
ROI 0 − Y End Configuration (bits 9..2)
roi1_configuration0
0xC900
51456
ROI Configuration
[7:0]
x_start
0x00
0
ROI 1 − X Start Configuration (bits 8..1)
[15:8]
x_end
0xC9
201
ROI 1 − X End Configuration (bits 8..1)
251
252
253
254
255
Type
RW
RW
RW
RW
RW
Sequencer ROI [Block Offset: 256]
0
1
2
3
4
5
256
257
258
259
roi1_configuration1
0x9700
38656
ROI Configuration
[7:0]
x_start
0x00
0
ROI 1 − Y Start Configuration (bits 9..2)
[15:8]
x_end
0x97
151
ROI 1 − Y End Configuration (bits 9..2)
260
roi2_configuration0
0xC900
51456
ROI Configuration
[7:0]
x_start
0x00
0
ROI 2 − X Start Configuration (bits 8..1)
[15:8]
x_end
0xC9
201
ROI 2 − X End Configuration (bits 8..1)
roi2_configuration1
0x9700
38656
ROI Configuration
[7:0]
y_start
0x00
0
ROI 2 − Y Start Configuration (bits 9..2)
[15:8]
y_end
0x97
151
ROI 2 − Y End Configuration (bits 9..2)
261
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56
RW
RW
RW
RW
RW
RW
PYTHON 480
Table 25. REGISTER MAP (continued)
Address
Offset
Address
6
262
7
8
9
Register Name
Default
(Hex)
Default
roi3_configuration0
0xC900
51456
ROI Configuration
[7:0]
x_start
0x00
0
ROI 3 − X Start Configuration (bits 8..1)
[15:8]
x_end
0xC9
201
ROI 3 − X End Configuration (bits 8..1)
Bit Field
263
Description
roi3_configuration1
0x9700
38656
ROI Configuration
[7:0]
y_start
0x00
0
ROI 3 − Y Start Configuration (bits 9..2)
[15:8]
y_end
0x97
151
ROI 3 − Y End Configuration (bits 9..2)
264
roi_configuration_lsb0
0xC4C4
50372
ROI Configuration
[0]
x_start0(0)
0x0
0
ROI 0 − X Start Configuration (bit 0)
[2]
x_end0(0)
0x1
1
ROI 0 − X End Configuration (bit 0)
[5:4]
y_start0(1:0)
0x0
0
ROI 0 − Y Start Configuration (bits 1..0)
[7:6]
y_end0(1:0)
0x3
3
ROI 0 − Y End Configuration (bits 1..0)
[8]
x_start1(0)
0x0
0
ROI 1 − X Start Configuration (bit 0)
[10]
x_end1(0)
0x1
1
ROI 1 − X End Configuration (bit 0)
[13:12]
y_start1(1:0)
0x0
0
ROI 1 − Y Start Configuration (bits 1..0)
[15:14]
y_end1(1:0)
0x3
3
ROI 1 − Y End Configuration (bits 1..0)
roi_configuration_lsb1
0xC4C4
50372
ROI Configuration
[0]
x_start0(0)
0x0
0
ROI 2 − X Start Configuration (bit 0)
[2]
x_end0(0)
0x1
1
ROI 2 − X End Configuration (bit 0)
[5:4]
y_start0(1:0)
0x0
0
ROI 2 − Y Start Configuration (bits 1..0)
[7:6]
y_end0(1:0)
0x3
3
ROI 2 − Y End Configuration (bits 1..0)
[8]
x_start1(0)
0x0
0
ROI 3 − X Start Configuration (bit 0)
[10]
265
x_end1(0)
0x1
1
ROI 3 − X End Configuration (bit 0)
[13:12]
y_start1(1:0)
0x0
0
ROI 3 − Y Start Configuration (bits 1..0)
[15:14]
y_end1(1:0)
0x3
3
ROI 3 − Y End Configuration (bits 1..0)
Type
RW
RW
RW
RW
Sequencer ROI [Block Offset: 384]
0
384
[15:0]
…
…
95
479
[15:0]
reserved
Reserved
reserved
Reserved
…
…
…
…
reserved
Reserved
reserved
Reserved
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57
RW
RW
RW
PYTHON 480
PACKAGE INFORMATION
Pin List
The LVDS I/Os comply to the TIA/EIA−644−A Standard and the CMOS I/Os have a 1.8 V signal level.
Table 26. PIN LIST
Pin Map
Pin Name
I/O Type
Direction
Description
A1
VDD_PIX
Supply
Pixel Array Supply
B1
VDD_33
Supply
3.3 V Supply
C1
MONITOR0
CMOS
Output
Monitor Output #0
D1
MONITOR1
CMOS
Output
Monitor Output #1
E1
IBIAS_MASTER
Analog
I/O
F1
CP_RESPD
Analog
Output
For Test Only − Do not connect
G1
CP_CALIB
Analog
Output
For Test Only − Do not connect
H1
MBSINOUT_1
Analog
I/O
For Test Only − Do not connect
A2
VDD_18
Supply
Master Bias Reference. Connect with 47kOhm to VSS_33
1.8 V Supply
B2
VSS_COLPC
Supply
C2
SCAN_EN
CMOS
Pixel Array Ground
D2
VSS_18
Supply
1.8 V Ground
E2
VSS_33
Supply
3.3 V Ground
F2
MONITOR2
CMOS
G2
VSS_33
Supply
H2
MBSINOUT_1
Analog
I/O
A3
TR2
CMOS
Input
Connect to VSS_18
B3
TR1
CMOS
Input
Connect to VSS_18
C3
TRIGGER0
CMOS
Input
Trigger Input #0
G3
VDD_33
Supply
H3
MBSINOUT_2
Analog
I/O
For Test Only − Do not connect
A4
SS_N
CMOS
Input
SPI Slave Select (Active Low)
B4
SCK
CMOS
Input
SPI Clock
C4
RESET_N
CMOS
Input
Sensor Reset (Active Low)
G4
MISO
CMOS
Output
SPI Master In − Slave Out
H4
CP_SEL_SAMPLE
Analog
Output
For Test Only − Do not connect
A5
FRAME_VALID
CMOS
Output
Frame Valid Output
Input
For Test Only − Connect to VSS_18
Output
Monitor Output #2
3.3 V Ground
For Test Only − Do not connect
3.3 V Supply
B5
LINE_VALID
CMOS
Output
Line Valid Output
C5
DOUT9
CMOS
Output
Data Output #9
G5
MOSI
CMOS
Input
SPI Master Out − Slave In
H5
TEST_ENABLE
CMOS
Input
For Test Only − Connect to VSS_18
A6
VSS_COLPC
Supply
Pixel Array Ground
B6
VDD_PIX
Supply
Pixel Array Supply
C6
DOUT8
CMOS
G6
VSS_18
Supply
Output
Data Output #8
H6
VREF_BOTPLATE
Supply
Input
A7
DOUT7
CMOS
Output
Data Output #7
B7
DOUT6
CMOS
Output
Data Output #6
1.8 V Ground
1.8 V Supply for Sample and Hold
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58
PYTHON 480
Table 26. PIN LIST (continued)
Pin Map
Pin Name
I/O Type
Direction
Output
Description
C7
DOUT5
CMOS
Data Output #5
G7
VSS_18
Supply
1.8 V Ground
H7
VSS_33
Supply
3.3 V Ground
A8
CLK_OUT
CMOS
Output
Clock Output
B8
DOUT4
CMOS
Output
Data Output #4
Output
Data Output #3
C8
DOUT3
CMOS
G8
VSS_18
Supply
1.8 V Ground
H8
VSS_33
Supply
3.3 V Ground
A9
DOUT2
CMOS
Output
Data Output #2
B9
DOUT0
CMOS
Output
Data Output #0
C9
DOUT1
CMOS
Output
Data Output #1
G9
CLK_PLL
CMOS
Input
H9
VDD_18
Supply
1.8 V Supply
A10
VDD_18
Supply
1.8 V Supply
B10
VDD_PIX
Supply
Pixel Array Supply
C10
CLOCK_OUTN
LVDS
Output
LVDS Clock Output (Negative)
D10
DOUTN
LVDS
Output
LVDS Data Output (Negative)
E10
SYNCN
LVDS
Output
LVDS Sync Channel Output (Negative)
F10
LVDS_CLOCK_INN
LVDS
Input
G10
LOCK_DETECT
CMOS
Output
H10
VDD_33
Supply
3.3 V Supply
A11
VSS_COLPC
Supply
Pixel Array Ground
B11
CLOCK_OUTP
LVDS
Output
LVDS Clock Output (Positive)
C11
DOUTP
LVDS
Output
LVDS Data Output (Positive)
D11
SYNCP
LVDS
Output
LVDS Sync Channel Output (Positive)
E11
LVDS_CLOCK_INP
LVDS
Input
F11
VDD_33
Supply
3.3 V Supply
G11
VSS_18
Supply
1.8 V Ground
H11
VDD_33
Supply
3.3 V Supply
Reference Clock Input for PLL
LVDS Clock Input (Negative)
Lock Detect Output
LVDS Clock Input (Positive)
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59
PYTHON 480
Mechanical Specifications
Mechanical Specifications
Package Body
Dimensions (Top View,
Bumps down, with Pin
A1 top left corner)
Symbol
Min
Typ
Max
Units
Package Body Dimension X
A
6105
6130
6155
mm
Package Body Dimension Y
B
4905
4930
4955
mm
Package Height
C
631.2
691.2
751.2
mm
Ball Height
C1
100
130
160
mm
Package Body Thickness
C2
516.2
561.2
606.2
mm
Distance of Glass Surface to Wafer
C3
425
445
465
mm
Ball Diameter
D
220
250
280
mm
Total Pin Count
N
67
mm
Pin Count X−axis
N1
11
mm
Pin Count Y−axis
N2
8
mm
Pins Pitch X−axis
J1
500
mm
Pins Pitch Y−axis
J2
500
mm
Edge to Pin Center Distance along X
S1
535
565
595
mm
Edge to Pin Center Distance along Y
S2
685
715
745
mm
Optical center referenced from package
center (X−dir)
0
mm
Optical center referenced from package
center (Y−dir)
−175
mm
Glass Lid
Glass Thickness (Material: AF32ECO)
390
400
410
Mechanical shock
JESD22−B104C; Condition G
2000
g
Vibration
JESD22−B103B; Condition 1
2000
Hz
mm
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
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60
PYTHON 480
Pixel (0,0)
Figure 43. Mechanical Diagram
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61
PYTHON 480
Packing and Tray Specification
The PYTHON480 packing specification with ON Semiconductor packing labels is packed as follows:
Figure 45. Tray Drawing
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62
PYTHON 480
Figure 46. Pin 1 Location
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63
PYTHON 480
Glass Lid
The PYTHON 480 image sensors use a glass lid without
any coatings. Figure 44 shows the transmission
characteristics of the glass lid.
As shown in Figure 42, no infrared attenuating color filter
glass is used. Use of an IR cut filter is recommended in the
optical path when color devices are used. (source:
http://www.pgo−online.com).
Figure 47. Transmission Characteristics of the Glass Lid
Protective Foil
The sensor is delivered with protective foil that is intended
to be removed after assembly. The dimensions of the foil are
as illustrated in Figure 48 with tab aligned left center with
Pin A1 to the bottom left.
(units in mm)
Figure 48. Dimensions of the Protective Foil
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64
PYTHON 480
SPECIFICATIONS AND USEFUL REFERENCES
The following references are available to customers under
NDA at the ON Semiconductor Image Sensor Portal:
https://www.onsemi.com/PowerSolutions/myon/erCispFol
der.do
• Product Acceptance Criteria
• Product Qualification Report
• PYTHON Developer’s Guide AND9362/D
For quality and reliability information, please download
the Quality & Reliability Handbook (HBD851/D) from
www.onsemi.com.
For information on Standard terms and Conditions of
Sale, please download Terms and Conditions from
www.onsemi.com.
For information on acronyms and a glossary of terms
used, please download Image Sensor Terminology
(TND6116/D) from www.onsemi.com.
Useful References
For information on ESD and cover glass care and
cleanliness, please download the Image Sensor Handling
and Best Practices Application Note (AN52561/D) from
www.onsemi.com.
Return Material Authorization (RMA)
Refer to the ON Semiconductor RMA policy procedure at
http://www.onsemi.com/site/pdf/CAT_Returns_FailureAn
alysis.pdf
www.onsemi.com
65
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ODCSP67, 4.93x6.13
CASE 570BW
ISSUE O
DATE 16 FEB 2016
SCALE 2:1
E
PIN A1
REFERENCE
OPTICAL
AREA
NOTE 4
A
E1
ÉÉ
ÉÉ
B
F
NOTE 5
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
4. MAXIMUM ROTATION OF OPTICAL AREA
RELATIVE TO PACKAGE EDGES IS 0.1*.
5. DIMENSION F DEFINES THE OPTICAL
CENTER.
DIM
A
A1
A2
b
D
D1
E
E1
e
F
D1 D
0.025 C
2X
0.025 C
MILLIMETERS
MIN
MAX
0.75
−−−
0.10
0.16
0.56 REF
0.22
0.28
4.93 BSC
2.96 REF
6.13 BSC
3.92 REF
0.50 BSC
0.175 REF
TOP VIEW
0.0002 E
DETAIL A
A2
0.05 A
0.0002 D
A1
A
D
0.08 C
C
SIDE VIEW
NOTE 3
LASER MARK
AREA
e
SEATING
PLANE
b
67X
0.05
C A B
M
0.03 C
H
G
e/2
E
RECOMMENDED
SOLDERING FOOTPRINT*
0.50
PITCH
e
F
E
DETAIL A
A1
D
PACKAGE
OUTLINE
C
B
0.50
PITCH
A
PIN A1
REFERENCE
1
2
3
4
5
6
7
8
9 10 11
BOTTOM VIEW
67X
0.25
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON08673G
ODCSP67, 4.93X6.13
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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