NS5B1G385DFT2G

NS5B1G385 Analog Switch, Single SPST, (NO) Normally Open The NS5B1G385 is Single Pole Single Throw (SPST) high−speed TTL−compatible switch. The low resistance and capacitance characteristics of this switch make it ideal for low−distortion audio, video, and data routing applications. The switch has a normally open logic configuration meaning the switch is on (NO connected to COM) when IN is high. These switches are available in 5−pin SC−70 and 5 −pin TSOP−5 (SOT23−5) packages for operation over the industrial (−40°C to +85°C) temperature range. http://onsemi.com MARKING DIAGRAMS • • • • • • • VCC Operating Range: 2.0 V to 5.5 V Low On Resistance : RON: 4.0  Typical @ VCC = 4.5 V Minimal Propagation Delay : tpd < 0.5 ns Control Input Compatible with TTL Levels ESD Performance: Human Body Model > ±2 kV 5−Pin SC−70 or 5−Pin TSOP−5 Packages Available These are Pb−Free Devices 5 TSOP−5 (SOT23−5) CASE 483 5 1 CG CD M G Typical Applications • • • • CG MG G SC−70 CASE 419A Features Audio, Video, and High−Speed Data Switching Mobile Phones Portable Devices Desktop & Notebook Computing CD MG G 1 = For SC−70 = For TSOP−5 = Date Code = Pb−Free Package (Note: Microdot may be in either location) LOGIC DIAGRAM COM NO IN PIN ASSIGNMENTS COM 1 NO 2 GND 3 5 VCC 4 IN ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. © Semiconductor Components Industries, LLC, 2009 March, 2009 − Rev. 0 1 Publication Order Number: NS5B1G385/D NS5B1G385 PIN DESCRIPTION TRUTH TABLE PIN # Name Direction Description IN Control Input Function 1 COM I/O Common Signal Line L NO Disconnected from COM 2 NO I/O Normally Open Signal Line H NO Connected to COM 3 GND Input Ground 4 IN Input Control Signal Line 5 VCC Input Voltage Supply MAXIMUM RATINGS Symbol Pins Rating VCC VCC Positive DC Supply Voltage Value VIS NO or COM VIN IN IIS_CON NO or COM Analog Signal Continuous Current $300 Closed Switch mA IIS_PK NO or COM Analog Signal Peak Current $500 10% Duty Cycle mA IIN IN Unit V Analog Signal Voltage −0.5 to VCC + 0.5 V Control Input Voltage −0.5 to +7.0 V Control Input Current TSTG Condition −0.5 to +7.0 Storage Temperature Range $20 mA −65 to 150 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. RECOMMENDED OPERATING CONDITIONS Symbol Pins VCC VCC VIS NO or COM VIN IN Parameter Value Positive DC Supply Voltage Condition Unit 2.0 to 5.5 V Analog Signal Voltage GND to VCC V Control Input Voltage GND to 5.5 V TA Operating Temperature Range −40 to +85 °C tr, tf Input Rise or Fall Time 20 VCC = 3.3 V 10 VCC = 5.0 V ns/V Minimum and maximum values are guaranteed through test or design across the Recommended Operating Conditions, where applicable. Typical values are listed for guidance only and are based on the particular conditions listed for each section, where applicable. These conditions are valid for all values found in the characteristics tables unless otherwise specified in the test conditions. ESD PROTECTION Pins All Pins Description Minimum Voltage Human Body Model 2 kV http://onsemi.com 2 NS5B1G385 DC ELECTRICAL CHARACTERISTICS CONTROL INPUT (Typical: T = 25°C) Parameter Test Conditions Min 2.0 Symbol Pins VIH IN Control Input High 4.5 − 5.5 VIL IN Control Input Low 4.5 − 5.5 IIN IN Control Input Leakage 0 v VIN v VCC −405C to +855C VCC (V) 5.0 Typ Max Unit V ±0.1 0.8 V ±0.5 A SUPPLY CURRENT AND LEAKAGE (Typical: T = 25°C) Symbol Pins Parameter Test Conditions INO (OFF) NO OFF State Leakage VIN = VIL or VIH VNO = 1.0 V VCOM = 4.5 V ICOM (OFF) COM OFF State Leakage VIN = VIL or VIH VNO = 4.5 V VCOM = 1.0 V ICC VCC Quiescent Supply IOFF IN Power Off Leakage VIN and VIS = VCC or GND ID = 0 A VIN = 5.5 V or GND VCC (V) −405C to +855C Min Typ Max Unit 5.5 ±10 ±100 nA 5.5 ±10 ±100 nA 2.0 − 5.5 ±0.1 ±1.0 A 0 ±0.5 ±1.0 A ON RESISTANCE (Typical: T = 25°C) Symbol Pins RON NO, COM Parameter ON Resistance Test Conditions VIS = 0 V, ION = 30 mA VIS = 0 V, ION = 64 mA VIS = 2.4 V, ION = 15 mA http://onsemi.com 3 VCC (V) 4.5 4.5 4.5 −405C to +855C Min Typ Max Unit 4.0 4.0 11.5 7.0 7.0 15  NS5B1G385 AC ELECTRICAL CHARACTERISTICS TIMING/FREQUENCY (Typical: T = 25°C, RL = 50 , CL = 35 pF, f = 1 MHz) −405C to +855C Max Unit 4.5 6.0 ns As Above, Figures 1 and 2 4.5 2.0 ns Propagation Delay As Above 4.5 0.5 ns −3dB Bandwidth CL = 5 pF, Figures 3 and 4 4.5 Symbol Pins tON IN to NO Turn On Time As Above, Figures 1 and 2 tOFF IN to NO Turn Off Time tPD NO to COM BW VCC (V) Parameter Test Conditions Min Typ 330 MHz CAPACITANCE (Typical: T = 25°C, RL = 50 , CL = 5 pF, f = 1 MHz) Symbol Pins Parameter CIN IN CON NO to COM Through Switch COFF NO Unselected Port Test Conditions Control Input VCC (V) −405C to +855C Min Typ Max Unit 0V 2.2 pF VIN = 0V 4.5 V 12 pF VIS = 4.5 V, VIN = 4.5 V 4.5 V 4.1 pF DEVICE ORDERING INFORMATION Package Type Tape & Reel Size† NS5B1G385DFT2G SC−70 (Pb−Free) 3000 / Tape & Reel NS5B1G385DTT1G TSOP−5 (Pb−Free) 3000 / Tape & Reel Device Order Number †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 4 NS5B1G385 VCC Input DUT VCC 0.1 F 50% Output VOUT Open 50% 0V 50  VOH 90% 35 pF 90% Output VOL Input tON tOFF Figure 1. tON/tOFF VCC VCC Input DUT Output 50% 0V 50  VOUT Open 50% VOH 35 pF Output Input tOFF Figure 2. tON/tOFF 50  Reference DUT Transmitted Input Output 50  Generator 50  Channel switch control/s test socket is normalized. Off isolation is measured across an off channel. On loss is the bandwidth of an On switch. VISO, Bandwidth and VONL are independent of the input signal direction. ǒVVOUT Ǔ for VIN at 100 kHz IN VOUT Ǔ for VIN at 100 kHz to 50 MHz VONL = On Channel Loss = 20 Logǒ VIN VISO = Off Channel Isolation = 20 Log Bandwidth (BW) = the frequency 3 dB below VONL VCT = Use VISO setup and test to all other switch analog input/outputs terminated with 50  Figure 3. Off Channel Isolation/On Channel Loss (BW)/Crosstalk (On Channel to Off Channel)/VONL http://onsemi.com 5 10% 10% VOL tON NS5B1G385 −10 0 −20 MAGNITUDE (dB) −30 −2 −3 −4 −40 −50 −60 −70 −80 −5 −90 −6 10000 1000000 −100 10000 100000000 1000000 100000000 FREQUENCY (Hz) FREQUENCY (Hz) Figure 4. Typical Bandwidth @ VCC = 5.5 V, 255C Figure 5. Off−Channel Isolation @ VCC = 5.5 V, 255C 0.06 0.05 PERCENT (%) MAGNITUDE (dB) −1 0.04 0.03 0.02 0.01 0 10 100 1000 10000 100000 FREQUENCY (Hz) Figure 6. Typical Total Harmonic Distortion @ VCC = 4.5 V http://onsemi.com 6 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SC−88A (SC−70−5/SOT−353) CASE 419A−02 ISSUE L SCALE 2:1 A NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. 419A−01 OBSOLETE. NEW STANDARD 419A−02. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. G 5 4 −B− S 1 2 DATE 17 JAN 2013 DIM A B C D G H J K N S 3 D 5 PL 0.2 (0.008) B M M N INCHES MIN MAX 0.071 0.087 0.045 0.053 0.031 0.043 0.004 0.012 0.026 BSC --0.004 0.004 0.010 0.004 0.012 0.008 REF 0.079 0.087 MILLIMETERS MIN MAX 1.80 2.20 1.15 1.35 0.80 1.10 0.10 0.30 0.65 BSC --0.10 0.10 0.25 0.10 0.30 0.20 REF 2.00 2.20 J GENERIC MARKING DIAGRAM* C K H XXXMG G SOLDER FOOTPRINT 0.50 0.0197 XXX = Specific Device Code M = Date Code G = Pb−Free Package 0.65 0.025 0.65 0.025 0.40 0.0157 1.9 0.0748 SCALE 20:1 (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. mm Ǔ ǒinches STYLE 1: PIN 1. BASE 2. EMITTER 3. BASE 4. COLLECTOR 5. COLLECTOR STYLE 2: PIN 1. ANODE 2. EMITTER 3. BASE 4. COLLECTOR 5. CATHODE STYLE 3: PIN 1. ANODE 1 2. N/C 3. ANODE 2 4. CATHODE 2 5. CATHODE 1 STYLE 4: PIN 1. SOURCE 1 2. DRAIN 1/2 3. SOURCE 1 4. GATE 1 5. GATE 2 STYLE 6: PIN 1. EMITTER 2 2. BASE 2 3. EMITTER 1 4. COLLECTOR 5. COLLECTOR 2/BASE 1 STYLE 7: PIN 1. BASE 2. EMITTER 3. BASE 4. COLLECTOR 5. COLLECTOR STYLE 8: PIN 1. CATHODE 2. COLLECTOR 3. N/C 4. BASE 5. EMITTER STYLE 9: PIN 1. ANODE 2. CATHODE 3. ANODE 4. ANODE 5. ANODE DOCUMENT NUMBER: DESCRIPTION: 98ASB42984B STYLE 5: PIN 1. CATHODE 2. COMMON ANODE 3. CATHODE 2 4. CATHODE 3 5. CATHODE 4 Note: Please refer to datasheet for style callout. If style type is not called out in the datasheet refer to the device datasheet pinout or pin assignment. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. SC−88A (SC−70−5/SOT−353) PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSOP−5 CASE 483 ISSUE N 5 1 SCALE 2:1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSION A. 5. OPTIONAL CONSTRUCTION: AN ADDITIONAL TRIMMED LEAD IS ALLOWED IN THIS LOCATION. TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2 FROM BODY. D 5X NOTE 5 2X DATE 12 AUG 2020 0.20 C A B 0.10 T M 2X 0.20 T 5 B 1 4 2 B S 3 K DETAIL Z G A A TOP VIEW DIM A B C D G H J K M S DETAIL Z J C 0.05 H C SIDE VIEW SEATING PLANE END VIEW GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 0.95 0.037 MILLIMETERS MIN MAX 2.85 3.15 1.35 1.65 0.90 1.10 0.25 0.50 0.95 BSC 0.01 0.10 0.10 0.26 0.20 0.60 0_ 10 _ 2.50 3.00 1.9 0.074 5 5 XXXAYWG G 1 1 Analog 2.4 0.094 XXX = Specific Device Code A = Assembly Location Y = Year W = Work Week G = Pb−Free Package 1.0 0.039 XXX MG G Discrete/Logic XXX = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) 0.7 0.028 SCALE 10:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98ARB18753C TSOP−5 *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without notice. 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