NSPM3042MXT5G

NSPM3042 4.8 V Bidirectional ESD and Surge Protection Device The NSPM3042 is designed to protect voltage sensitive components from ESD. Excellent clamping capability, low leakage, high peak pulse current handling capability and fast response time provide best in class protection on designs that are exposed to ESD. Because of its small size, it is suited for use in cellular phones, tablets, MP3 players, digital cameras and many other portable applications where board space comes at a premium. www.onsemi.com 1 2 Features • • • • • Low Clamping Voltage Low Leakage Small Body Outline: 1.0 mm x 0.6 mm Protection for the following IEC Standards: IEC61000−4−2 Level 4: ±30 kV Contact Discharge IEC61000−4−5 (Lightning) 43 A (8/20 ms) These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant MARKING DIAGRAM QM X2DFN2 CASE 714AB Q M = Specific Device Code = Date Code Typical Applications • Battery Line Protection • Audio Line Protection • GPIO ORDERING INFORMATION Device NSPM3042MXT5G MAXIMUM RATINGS Rating IEC 61000−4−2 (ESD) Symbol Value Unit ±30 ±30 kV TJ, Tstg −65 to +150 °C IPP 43 A Contact Air Operating Junction and Storage Temperature Range Maximum Peak Pulse Current Package Shipping† X2DFN2 (Pb−Free) 8000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. © Semiconductor Components Industries, LLC, 2017 September, 2018 − Rev. 2 1 Publication Order Number: NSPM3042/D NSPM3042 ELECTRICAL CHARACTERISTICS I (TA = 25°C unless otherwise noted) IPP Parameter Symbol IPP Maximum Reverse Peak Pulse Current VC Clamping Voltage @ IPP VRWM IR VBR IT RDYN IT VC VBR VRWM IR IR VRWM VBR VC IT Working Peak Reverse Voltage V RDYN Maximum Reverse Leakage Current @ VRWM Breakdown Voltage @ IT IPP Test Current Bi−Directional Surge Protection *See Application Note AND8308/D for detailed explanations of datasheet parameters. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified) Parameter Reverse Working Voltage Breakdown Voltage Symbol VRWM VBR Conditions Min I/O Pin to GND Pin 1 to 2 Pin 2 to 1 IT = 1 mA, I/O Pin to GND Pin 1 to 2 Pin 2 to 1 Reverse Leakage Current IR VRWM = 4.8 V, Pin 1 to Pin 2 VRWM = 4.5 V, Pin 2 to Pin 1 Clamping Voltage VC IEC61000−4−2, ±8 kV Contact Clamping Voltage TLP (Note 1) VC 4.85 4.55 Typ 5.2 5.0 6.0 6.0 V 0.5 0.5 mA 5.50 V IPP = 16 A, IEC61000−4−2 Level 4 Equivalent (±8 kV Contact, ± 15 kV Air) 5.74 Clamping Voltage 8x20 ms Waveform per Figure 14 (Note 2) VC IPP = 1 A IPP = 43 A 4.9 7.4 100 ns TLP Pulse 0.03 CJ V IPP = 8 A, IEC61000−4−2 Level 2 Equivalent (±4 kV Contact, ± 8 kV Air) IEC61000−4−5 (8 x 20 ms) per Figure 14 Junction Capacitance 4.8 4.5 V IPP RDYN Unit See Figures 1 & 2 Reverse Peak Pulse Current Dynamic Resistance Max VR = 0 V, f = 1 MHz 43 A 80 6.2 8.0 V W 200 pF Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 1. ANSI/ESD STM5.5.1 Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP condtions: Z0 = 50 W, tp = 100 ns, tr = 1 ns, averaging window: t1 = 70 ns to t2 = 90 ns. 2. Non−repetitive current pulse at TA = 25°C, per IEC61000−4−5 waveform. www.onsemi.com 2 NSPM3042 40 5 35 0 30 −5 25 −10 VOLTAGE (V) VOLTAGE (V) TYPICAL CHARACTERISTICS 20 15 10 −15 −20 −25 5 −30 0 −35 −5 −20 0 20 40 60 80 100 −40 −20 140 120 0 20 40 60 80 100 120 TIME (ns) TIME (ns) Figure 1. ESD Clamping Voltage Positive 8 kV Contact per IEC61000−4−2 Figure 2. ESD Clamping Voltage Negative 8 kV Contact per IEC61000−4−2 140 10 −18 9 16 8 −16 8 14 7 −14 7 12 6 10 5 8 4 6 4 −12 6 −10 5 −8 4 3 −6 3 2 −4 2 2 1 −2 1 0 0 10 0 0 1 2 3 4 5 6 7 8 9 0 −1 −2 −3 −4 VCTLP (V) 9 8 8 7 7 VC @ IPK (V) VC @ IPK (V) 10 9 6 5 4 4 3 2 1 1 0 0 25 30 0 −9 −10 5 3 15 20 −8 6 2 10 −7 Figure 4. Negative TLP I−V Curve 10 5 −6 VCTLP (V) Figure 3. Positive TLP I−V Curve 0 −5 VIEC Eq (kV) −20 9 VIEC Eq (kV) ITLP (A) 10 ITLP (A) 20 18 35 40 45 50 55 0 60 5 10 15 20 25 30 35 40 45 50 55 IPK (A) IPK (A) Figure 5. Positive Clamping Voltage vs. Peak Pulse Current (tp = 8/20 ms) Figure 6. Negative Clamping Voltage vs. Peak Pulse Current (tp = 8/20 ms) www.onsemi.com 3 60 NSPM3042 TYPICAL CHARACTERISTICS 1E−03 1E−03 1E−04 1E−04 1E−05 1E−05 1E−06 IR (A) 1E−07 1E−08 1E−07 1E−08 1E−09 1E−09 1E−10 1E−10 1E−11 1E−11 −6 −5 1E−12 −7 −6 −5 −4 −3 −2 −1 −4 −3 −2 −1 0 2 1 3 4 5 6 VR (V) 1 2 3 4 5 Figure 8. Reverse Leakage Current 100 90 80 70 60 50 40 30 20 10 0 −5 0 VR (V) Figure 7. Breakdown Voltage C (pF) IR (A) 1E−06 −4 −3 −2 −1 0 1 2 3 VBIAS (V) Figure 9. Line Capacitance, f = 1 MHz www.onsemi.com 4 4 5 6 7 NSPM3042 Transmission Line Pulse (TLP) Measurement L Transmission Line Pulse (TLP) provides current versus voltage (I−V) curves in which each data point is obtained from a 100 ns long rectangular pulse from a charged transmission line. A simplified schematic of a typical TLP system is shown in Figure 10. TLP I−V curves of ESD protection devices accurately demonstrate the product’s ESD capability because the 10s of amps current levels and under 100 ns time scale match those of an ESD event. This is illustrated in Figure 11 where an 8 kV IEC 61000−4−2 current waveform is compared with TLP current pulses at 8 A and 16 A. A TLP I−V curve shows the voltage at which the device turns on as well as how well the device clamps voltage over a range of current levels. For more information on TLP measurements and how to interpret them please refer to AND9007/D. 50 W Coax Cable S Attenuator ÷ 50 W Coax Cable 10 MW IM VM DUT VC Oscilloscope Figure 10. Simplified Schematic of a Typical TLP System Figure 11. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms www.onsemi.com 5 NSPM3042 IEC61000−4−2 Waveform IEC 61000−4−2 Spec. Ipeak Level Test Voltage (kV) First Peak Current (A) Current at 30 ns (A) Current at 60 ns (A) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 100% 90% I @ 30 ns I @ 60 ns 10% tP = 0.7 ns to 1 ns Figure 12. IEC61000−4−2 Spec ESD Gun Oscilloscope DUT 50 W Cable 50 W Figure 13. Diagram of ESD Test Setup ESD Voltage Clamping at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D. For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage % OF PEAK PULSE CURRENT 100 PEAK VALUE IRSM @ 8 ms tr 90 PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 ms 80 70 60 HALF VALUE IRSM/2 @ 20 ms 50 40 30 tP 20 10 0 0 20 40 t, TIME (ms) 60 Figure 14. 8 X 20 ms Pulse Waveform www.onsemi.com 6 80 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS X2DFN2 1.0x0.6, 0.65P CASE 714AB ISSUE B DATE 21 NOV 2017 SCALE 8:1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. EXPOSED COPPER ALLOWED AS SHOWN. 0.10 C A B D É PIN 1 INDICATOR E DIM A A1 b D E e L 0.05 C TOP VIEW A NOTE 3 0.10 C 0.10 C A1 C SIDE VIEW GENERIC MARKING DIAGRAM* SEATING PLANE XX M e b e/2 MILLIMETERS MIN NOM MAX 0.34 0.37 0.40 −−− 0.03 0.05 0.45 0.50 0.55 0.95 1.00 1.05 0.55 0.60 0.65 0.65 BSC 0.20 0.25 0.30 0.05 M XX = Specific Device Code M = Date Code C A B RECOMMENDED SOLDER FOOTPRINT* 1 2X L 0.05 M C A B BOTTOM VIEW 1.20 2X 0.47 2X 0.60 PIN 1 DIMENSIONS: MILLIMETERS *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON98172F X2DFN2 1.0X0.6, 0.65P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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