NSS40300DDR2G

NSS40300DDR2G Dual 40 V, 6.0 A, Low VCE(sat) PNP Transistor ON Semiconductor’s e2 PowerEdge family of low VCE(sat) transistors are surface mount devices featuring ultra low saturation voltage (VCE(sat)) and high current gain capability. These are designed for use in low voltage, high speed switching applications where affordable efficient energy control is important. Typical applications are low voltage motor controls in mass storage products such as disc drives and tape drives. In the automotive industry they can be used in air bag deployment and in the instrument cluster. The high current gain allows e2PowerEdge devices to be driven directly from PMU’s control outputs, and the Linear Gain (Beta) makes them ideal components in analog amplifiers. http://onsemi.com 40 VOLTS 6.0 AMPS PNP LOW VCE(sat) TRANSISTOR EQUIVALENT RDS(on) 80 mW Features • Halide Free • This is a Pb−Free Device Rating Symbol Max Unit Collector-Emitter Voltage VCEO −40 Vdc Collector-Base Voltage VCBO −40 Vdc Emitter-Base Voltage VEBO −7.0 Vdc Collector Current − Continuous 4 BASE 2 BASE MAXIMUM RATINGS (TA = 25°C) IC −3.0 A Collector Current − Peak ICM −6.0 A Electrostatic Discharge ESD HBM Class 3B MM Class C COLLECTOR 5,6 COLLECTOR 7,8 3 EMITTER 1 EMITTER 8 1 SOIC−8 CASE 751 STYLE 16 DEVICE MARKING Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 8 1 40300 AYWWG G 40300 = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Device Package Shipping† NSS40300DDR2G SOIC−8 (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2008 September, 2008 − Rev. 0 1 Publication Order Number: NSS40300D/D NSS40300DDR2G THERMAL CHARACTERISTICS Characteristic Symbol Max Unit PD 576 mW 4.6 mW/°C RqJA 217 °C/W PD 676 mW 5.4 mW/°C RqJA 185 °C/W PD 653 mW 5.2 mW/°C RqJA 191 °C/W PD 783 mW 6.3 mW/°C RqJA 160 °C/W TJ, Tstg −55 to +150 °C SINGLE HEATED Total Device Dissipation (Note 1) TA = 25°C Derate above 25°C Thermal Resistance, Junction−to−Ambient (Note 1) Total Device Dissipation (Note 2) TA = 25°C Derate above 25°C Thermal Resistance, Junction−to−Ambient (Note 2) DUAL HEATED (Note 3) Total Device Dissipation (Note 1) TA = 25°C Derate above 25°C Thermal Resistance, Junction−to−Ambient (Note 1) Total Device Dissipation (Note 2) TA = 25°C Derate above 25°C Thermal Resistance, Junction−to−Ambient (Note 2) Junction and Storage Temperature Range 10 mm2, 1 oz. copper traces, still air. 100 mm2, 1 oz. copper traces, still air. 1. FR−4 @ 2. FR−4 @ 3. Dual heated values assume total power is the sum of two equally powered devices. http://onsemi.com 2 NSS40300DDR2G ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max −40 − − −40 − − −7.0 − − − − −0.1 − − −0.1 250 220 180 150 380 340 300 230 − − − − − − − − −0.013 −0.075 −0.130 −0.135 −0.017 −0.095 −0.170 −0.170 − −0.780 −0.900 − −0.660 −0.750 100 − − Unit OFF CHARACTERISTICS Collector −Emitter Breakdown Voltage (IC = −10 mAdc, IB = 0) V(BR)CEO Collector −Base Breakdown Voltage (IC = −0.1 mAdc, IE = 0) V(BR)CBO Emitter −Base Breakdown Voltage (IE = −0.1 mAdc, IC = 0) V(BR)EBO Collector Cutoff Current (VCB = −40 Vdc, IE = 0) ICBO Emitter Cutoff Current (VEB = −6.0 Vdc) IEBO Vdc Vdc Vdc mAdc mAdc ON CHARACTERISTICS DC Current Gain (Note 4) (IC = −10 mA, VCE = −2.0 V) (IC = −500 mA, VCE = −2.0 V) (IC = −1.0 A, VCE = −2.0 V) (IC = −2.0 A, VCE = −2.0 V) hFE Collector −Emitter Saturation Voltage (Note 4) (IC = −0.1 A, IB = −0.010 A) (IC = −1.0 A, IB = −0.100 A) (IC = −1.0 A, IB = −0.010 A) (IC = −2.0 A, IB = −0.200 A) VCE(sat) Base −Emitter Saturation Voltage (Note 4) (IC = −1.0 A, IB = −0.01 A) VBE(sat) Base −Emitter Turn−on Voltage (Note 4) (IC = −0.1 A, VCE = −2.0 V) VBE(on) V V V Cutoff Frequency (IC = −100 mA, VCE = −5.0 V, f = 100 MHz) fT MHz Input Capacitance (VEB = −0.5 V, f = 1.0 MHz) Cibo − 250 300 pF Output Capacitance (VCB = −3.0 V, f = 1.0 MHz) Cobo − 50 65 pF Delay (VCC = −30 V, IC = −750 mA, IB1 = −15 mA) td − − 60 ns Rise (VCC = −30 V, IC = −750 mA, IB1 = −15 mA) tr − − 120 ns Storage (VCC = −30 V, IC = −750 mA, IB1 = −15 mA) ts − − 400 ns Fall (VCC = −30 V, IC = −750 mA, IB1 = −15 mA) tf − − 130 ns SWITCHING CHARACTERISTICS 4. Pulsed Condition: Pulse Width = 300 msec, Duty Cycle ≤ 2%. http://onsemi.com 3 NSS40300DDR2G TYPICAL CHARACTERISTICS 0.30 150°C 0.20 −55°C 0.15 25°C 0.10 0.05 0 0.001 0.01 0.1 1 10 300 −55°C (5.0 V) 200 −55°C (2.0 V) 100 0 0.001 0.01 0.1 1 0 0.001 0.01 0.1 1 10 IC/IB = 10 1.0 0.9 −55°C 0.8 25°C 0.7 0.6 150°C 0.5 0.4 0.001 0.01 0.1 1 IC, COLLECTOR CURRENT (A) Figure 3. DC Current Gain vs. Collector Current Figure 4. Base Emitter Saturation Voltage vs. Collector Current 10 2.0 VCE = −2.0 V 0.7 VCE(sat), COLLECTOR−EMITTER VOLTAGE (V) VBE(on), BASE−EMITTER TURN−ON VOLTAGE (V) 0.05 IC, COLLECTOR CURRENT (A) 0.8 −55°C 25°C 0.6 0.5 150°C 0.4 0.3 0.2 0.10 0.3 10 1.0 0.9 0.15 1.1 25°C (2.0 V) 400 0.20 150°C Figure 2. Collector Emitter Saturation Voltage vs. Collector Current 25°C (5.0 V) 500 25°C Figure 1. Collector Emitter Saturation Voltage vs. Collector Current 150°C (2.0 V) 600 −55°C IC, COLLECTOR CURRENT (A) 150°C (5.0 V) 700 IC/IB = 100 0.25 IC, COLLECTOR CURRENT (A) 800 hFE, DC CURRENT GAIN VCE(sat), COLLECTOR−EMITTER SATURATION VOLTAGE (V) IC/IB = 10 VBE(sat), BASE−EMITTER SATURATION VOLTAGE (V) VCE(sat), COLLECTOR−EMITTER SATURATION VOLTAGE (V) 0.25 0.001 0.01 0.1 1 10 1.8 100 mA 1.6 1A 3A 2A 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0.0001 0.001 0.01 IC, COLLECTOR CURRENT (A) Ib, BASE CURRENT (A) Figure 5. Base Emitter Turn−On Voltage vs. Collector Current Figure 6. Saturation Region http://onsemi.com 4 0.1 NSS40300DDR2G TYPICAL CHARACTERISTICS 100 Cobo, OUTPUT CAPACITANCE (pF) 300 250 200 Cibo (pF) 150 100 0 1 2 3 4 5 90 80 70 60 50 Cobo (pF) 40 30 6 0 5 10 15 20 25 30 VEB, EMITTER BASE VOLTAGE (V) Vcb, COLLECTOR BASE VOLTAGE (V) Figure 7. Input Capacitance Figure 8. Output Capacitance 10 1 ms 1s 10 ms 100 ms 1.0 IC (A) Cibo, INPUT CAPACITANCE (pF) 350 0.1 Thermal Limit 0.01 0.001 Single Pulse Test at TA = 25°C 0.01 0.1 1.0 10 VCE (Vdc) Figure 9. Safe Operating Area http://onsemi.com 5 100 35 40 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK 8 1 SCALE 1:1 −X− DATE 16 FEB 2011 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S 8 8 1 1 IC 4.0 0.155 XXXXX A L Y W G IC (Pb−Free) = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package XXXXXX AYWW 1 1 Discrete XXXXXX AYWW G Discrete (Pb−Free) XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 8 8 XXXXX ALYWX G XXXXX ALYWX 1.52 0.060 0.6 0.024 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 7.0 0.275 DIM A B C D G H J K M N S mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. BASE 7. BASE 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. BASE, #1 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. GATE, #1 8. SOURCE, #1 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. ANODE 8. COMMON CATHODE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. GATE 6. GATE 7. SOURCE 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. GATE 7. GATE 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. SECOND STAGE Vd 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR, DIE #1 2. BASE, #1 3. BASE, #2 4. COLLECTOR, #2 5. COLLECTOR, #2 6. EMITTER, #2 7. EMITTER, #1 8. COLLECTOR, #1 STYLE 9: PIN 1. EMITTER, COMMON 2. COLLECTOR, DIE #1 3. COLLECTOR, DIE #2 4. EMITTER, COMMON 5. EMITTER, COMMON 6. BASE, DIE #2 7. BASE, DIE #1 8. EMITTER, COMMON STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. INPUT 8. GROUND STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 13: PIN 1. N.C. 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 14: PIN 1. N−SOURCE 2. N−GATE 3. P−SOURCE 4. P−GATE 5. P−DRAIN 6. P−DRAIN 7. N−DRAIN 8. N−DRAIN STYLE 15: PIN 1. ANODE 1 2. ANODE 1 3. ANODE 1 4. ANODE 1 5. CATHODE, COMMON 6. CATHODE, COMMON 7. CATHODE, COMMON 8. CATHODE, COMMON STYLE 16: PIN 1. EMITTER, DIE #1 2. BASE, DIE #1 3. EMITTER, DIE #2 4. BASE, DIE #2 5. COLLECTOR, DIE #2 6. COLLECTOR, DIE #2 7. COLLECTOR, DIE #1 8. COLLECTOR, DIE #1 STYLE 17: PIN 1. VCC 2. V2OUT 3. V1OUT 4. TXE 5. RXE 6. VEE 7. GND 8. ACC STYLE 18: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 19: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. MIRROR 2 7. DRAIN 1 8. MIRROR 1 STYLE 20: PIN 1. SOURCE (N) 2. GATE (N) 3. SOURCE (P) 4. GATE (P) 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 21: PIN 1. CATHODE 1 2. CATHODE 2 3. CATHODE 3 4. CATHODE 4 5. CATHODE 5 6. COMMON ANODE 7. COMMON ANODE 8. CATHODE 6 STYLE 22: PIN 1. I/O LINE 1 2. COMMON CATHODE/VCC 3. COMMON CATHODE/VCC 4. I/O LINE 3 5. COMMON ANODE/GND 6. I/O LINE 4 7. I/O LINE 5 8. COMMON ANODE/GND STYLE 23: PIN 1. LINE 1 IN 2. COMMON ANODE/GND 3. COMMON ANODE/GND 4. LINE 2 IN 5. LINE 2 OUT 6. COMMON ANODE/GND 7. COMMON ANODE/GND 8. LINE 1 OUT STYLE 24: PIN 1. BASE 2. EMITTER 3. COLLECTOR/ANODE 4. COLLECTOR/ANODE 5. CATHODE 6. CATHODE 7. COLLECTOR/ANODE 8. COLLECTOR/ANODE STYLE 25: PIN 1. VIN 2. N/C 3. REXT 4. GND 5. IOUT 6. IOUT 7. IOUT 8. IOUT STYLE 26: PIN 1. GND 2. dv/dt 3. ENABLE 4. ILIMIT 5. SOURCE 6. SOURCE 7. SOURCE 8. VCC STYLE 29: PIN 1. BASE, DIE #1 2. EMITTER, #1 3. BASE, #2 4. EMITTER, #2 5. COLLECTOR, #2 6. COLLECTOR, #2 7. COLLECTOR, #1 8. COLLECTOR, #1 STYLE 30: PIN 1. DRAIN 1 2. DRAIN 1 3. GATE 2 4. SOURCE 2 5. SOURCE 1/DRAIN 2 6. SOURCE 1/DRAIN 2 7. SOURCE 1/DRAIN 2 8. GATE 1 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB STYLE 27: PIN 1. ILIMIT 2. OVLO 3. UVLO 4. INPUT+ 5. SOURCE 6. SOURCE 7. SOURCE 8. DRAIN STYLE 28: PIN 1. SW_TO_GND 2. DASIC_OFF 3. DASIC_SW_DET 4. GND 5. V_MON 6. VBULK 7. VBULK 8. VIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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