NSB9435T1G,
NSV9435T1G
High Current Bias Resistor
Transistor
PNP Silicon
http://onsemi.com
Features
Collector −Emitter Sustaining Voltage −
VCEO(sus) = 30 Vdc (Min) @ IC = 10 mAdc
High DC Current Gain −
= 125 (Min) @ IC = 0.8 Adc
hFE
= 90 (Min) @ IC = 3.0 Adc
Low Collector −Emitter Saturation Voltage −
VCE(sat) = 0.275 Vdc (Max) @ IC = 1.2 Adc
= 0.55 Vdc (Max) @ IC = 3.0 Adc
SOT−223 Surface Mount Packaging
ESD Rating − Human Body Model: Class 1B
− Machine Model: Class B
AEC−Q101 Qualified and PPAP Capable
NSV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant*
POWER BJT
IC = 3.0 AMPERES
BVCEO = 30 VOLTS
VCE(sat) = 0.275 VOLTS
SOT−223
CASE 318E
STYLE 1
COLLECTOR 2, 4
BASE
1
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
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Symbol
Value
Unit
VCEO
30
Vdc
Collector−Base Voltage
VCB
45
Vdc
Emitter−Base Voltage
VEB
6.0
Vdc
Base Current − Continuous
IB
1.0
Adc
Collector Current
Continuous
Peak
IC
Total Power Dissipation
@ TC = 25_C
Derate above 25_C
Total PD @ TA = 25_C mounted on 1 sq.
(645 sq. mm) Collector pad on FR−4 bd
material
Total PD @ TA = 25_C mounted on 0.012
sq. (7.6 sq. mm) Collector pad on FR−4 bd
material
PD
Rating
Collector−Emitter Voltage
Operating and Storage Junction
Temperature Range
3.0
5.0
W
mW/_C
W
3.0
24
1.56
– 55 to
+ 150
_C
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
December, 2011 − Rev. 7
AYW
9435R G
G
1
A
= Assembly Location
Y
= Year
W
= Work Week
9435R = Device Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
W
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
Semiconductor Components Industries, LLC, 2011
MARKING DIAGRAM
Adc
0.72
TJ, Tstg
EMITTER 3
1
ORDERING INFORMATION
Package
Shipping†
NSB9435T1G
SOT−223
(Pb−Free)
1,000/Tape & Reel
NSV9435T1G
SOT−223
(Pb−Free)
1,000/Tape & Reel
Device
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
NSB9435T1/D
NSB9435T1G, NSV9435T1G
THERMAL CHARACTERISTICS
Characteristic
Symbol
Thermal Resistance
Junction−to−Case
Junction−to−Ambient on 1 sq. (645 sq. mm) Collector pad on FR−4 board material
Junction−to−Ambient on 0.012 sq. (7.6 sq. mm) Collector pad on FR−4 board material
Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 5 s
Value
RqJC
RqJA
RqJA
42
80
174
TL
260
Unit
_C/W
_C
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted)
Characteristics
Symbol
Min
Typ
Max
30
−
−
6.0
−
−
−
−
−
−
20
200
−
−
700
−
−
−
0.155
−
−
0.210
0.275
0.550
−
−
1.25
−
−
1.10
125
110
90
220
−
−
−
−
−
7.5
10
12.5
−
100
150
−
135
−
−
110
−
Unit
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ÏÏÏÏ
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ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏ
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ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
OFF CHARACTERISTICS
Collector−Emitter Sustaining Voltage
(IC = 10 mAdc, IB = 0 Adc)
VCEO(sus)
Emitter−Base Voltage
(IE = 50 mAdc, IC = 0 Adc)
VEBO
Collector Cutoff Current
(VCE = 25 Vdc)
(VCE = 25 Vdc, TJ = 125C)
ICER
Emitter Cutoff Current
(VBE = 5.0 Vdc)
IEBO
Vdc
Vdc
mAdc
mAdc
ON CHARACTERISTICS (Note 1)
Collector−Emitter Saturation Voltage
(IC = 0.8 Adc, IB = 20 mAdc)
(IC = 1.2 Adc, IB = 20 mAdc)
(IC = 3.0 Adc, IB = 0.3 Adc)
VCE(sat)
Base−Emitter Saturation Voltage
(IC = 3.0 Adc, IB = 0.3 Adc)
VBE(sat)
Base−Emitter On Voltage
(IC = 1.2 Adc, VCE = 4.0 Vdc)
VBE(on)
DC Current Gain
(IC = 0.8 Adc, VCE = 1.0 Vdc)
(IC = 1.2 Adc, VCE = 1.0 Vdc)
(IC = 3.0 Adc, VCE = 1.0 Vdc)
hFE
Resistor
R1
Vdc
Vdc
Vdc
−
kW
DYNAMIC CHARACTERISTICS
Output Capacitance
(VCB = 10 Vdc, IE = 0 Adc, f = 1.0 MHz)
Cob
Input Capacitance
(VEB = 8.0 Vdc)
Cib
Current−Gain − Bandwidth Product (Note 2)
(IC = 500 mA, VCE = 10 V, Ftest = 1.0 MHz)
fT
1. Pulse Test: Pulse Width 300 ms, Duty Cycle 2%.
2. fT = |hFE| S ftest
http://onsemi.com
2
pF
pF
MHz
NSB9435T1G, NSV9435T1G
1000
0.25
hFE, DC CURRENT GAIN
VCE(sat), COLLECTOR−EMITTER
SATURATION VOLTAGE (V)
0.3
IC = 3.0 A
0.2
0.15
25C
100
0.1
1.2 A
0.8 A
0.05
0
TA = 150C
−55C
0.5 A
0.25 A
0.001
0.01
0.1
10
1
VCE = 1.0 V
0.1
IB, BASE CURRENT (mA)
Figure 2. DC Current Gain
1000
10
TA = 150C
V, VOLTAGE (V)
hFE, DC CURRENT GAIN
10
IC, COLLECTOR CURRENT (A)
Figure 1. Collector Saturation Region
25C
100
10
1
−55C
VCE = 4.0 V
0.1
1
VCE(sat)
0.1
0.01
10
VBE(sat)
1
IC/IB = 10
1.0E−01
IC, COLLECTOR CURRENT (A)
1.0E+00
1.0E+01
IC, COLLECTOR CURRENT (A)
Figure 3. DC Current Gain
Figure 4. “ON” Voltages
1.0E+00
1.2
VBE(sat)
1
V, VOLTAGE (V)
V, VOLTAGE (V)
VCE(sat)
1.0E−01
1.0E−01
1.0E+00
0.8
25C
0.6
TA = 155C
0.4
0.2
IC/IB = 50
1.0E−02
−55C
1.0E+01
0
0.1
IC, COLLECTOR CURRENT (A)
1
IC, COLLECTOR CURRENT (A)
Figure 5. “ON” Voltages
Figure 6. VBE(on) Voltage
http://onsemi.com
3
10
NSB9435T1G, NSV9435T1G
10
IC, COLLECTOR CURRENT (A)
Cob, OUTPUT CAPACITANCE (pF)
1000
100
10
f = 1 MHz
TA = 25C
1
0.1
10
1
0.5 ms
5.0 ms
1.0
100 ms
0.1
0.01
BONDING WIRE LIMIT
THERMAL LIMIT (Single Pulse)
SECONDARY BREAKDOWN LIMIT
0.001
100
0.1
Figure 7. Output Capacitance
PD, POWER DISSIPATION (WATTS)
TC
2.0
1.0
TA
50
75
100
100
There are two limitations on the power handling ability of
a transistor: average junction temperature and secondary
breakdown. Safe operating area curves indicate IC − VCE
limits of the transistor that must be observed for reliable
operation; i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.
The data of Figure 8 is based on TJ(pk) = 150_C; TC is
variable depending on conditions. Secondary breakdown
pulse limits are valid for duty cycles to 10% provided TJ(pk)
v 150_C. TJ(pk) may be calculated from the data in
Figure 10. At high case temperatures, thermal limitations
will reduce the power that can be handled to values less than
the limitations imposed by secondary breakdown.
3.0
25
10
Figure 8. Active Region Safe Operating Area
4.0
0
1.0
VCE, COLLECTOR−EMITTER VOLTAGE (VOLTS)
VR, REVERSE VOLTAGE (V)
125
150
T, TEMPERATURE (C)
r(t), EFFECTIVE TRANSIENT THERMAL
RESISTANCE (NORMALIZED)
Figure 9. Power Derating
1.0
D = 0.5
0.1
0.01
0.2
0.1
0.05
0.02
0.01
RqJA(t) = r(t) qJA
qJA = 174C/W
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) - TA = P(pk) qJA(t)
SINGLE PULSE
0.001
0.0001
0.0001
0.001
0.01
1.0
0.1
t, TIME (seconds)
Figure 10. Thermal Response
http://onsemi.com
4
10
P(pk)
t1
t2
DUTY CYCLE, D = t1/t2
100
1000
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOT−223 (TO−261)
CASE 318E−04
ISSUE R
DATE 02 OCT 2018
SCALE 1:1
q
q
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42680B
SOT−223 (TO−261)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
SOT−223 (TO−261)
CASE 318E−04
ISSUE R
STYLE 1:
PIN 1.
2.
3.
4.
BASE
COLLECTOR
EMITTER
COLLECTOR
STYLE 2:
PIN 1.
2.
3.
4.
ANODE
CATHODE
NC
CATHODE
STYLE 6:
PIN 1.
2.
3.
4.
RETURN
INPUT
OUTPUT
INPUT
STYLE 7:
PIN 1.
2.
3.
4.
ANODE 1
CATHODE
ANODE 2
CATHODE
STYLE 11:
PIN 1. MT 1
2. MT 2
3. GATE
4. MT 2
STYLE 3:
PIN 1.
2.
3.
4.
GATE
DRAIN
SOURCE
DRAIN
STYLE 8:
STYLE 12:
PIN 1. INPUT
2. OUTPUT
3. NC
4. OUTPUT
CANCELLED
DATE 02 OCT 2018
STYLE 4:
PIN 1.
2.
3.
4.
SOURCE
DRAIN
GATE
DRAIN
STYLE 5:
PIN 1.
2.
3.
4.
STYLE 9:
PIN 1.
2.
3.
4.
INPUT
GROUND
LOGIC
GROUND
STYLE 10:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
DRAIN
GATE
SOURCE
GATE
STYLE 13:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
GENERIC
MARKING DIAGRAM*
AYW
XXXXXG
G
1
A
= Assembly Location
Y
= Year
W
= Work Week
XXXXX = Specific Device Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42680B
SOT−223 (TO−261)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
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A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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