Complementary Bias
Resistor Transistors
R1 = 4.7 kW, R2 = 47 kW
NPN and PNP Transistors with Monolithic
Bias Resistor Network
MUN5333DW1,
NSBC143ZPDXV6,
NSBC143ZPDP6
www.onsemi.com
PIN CONNECTIONS
This series of digital transistors is designed to replace a single
device and its external resistor bias network. The Bias Resistor
Transistor (BRT) contains a single transistor with a monolithic bias
network consisting of two resistors; a series base resistor and a
base-emitter resistor. The BRT eliminates these individual
components by integrating them into a single device. The use of a BRT
can reduce both system cost and board space.
(3)
(2)
R1
•
Simplifies Circuit Design
Reduces Board Space
Reduces Component Count
S and NSV Prefix for Automotive and Other Applications
Requiring Unique Site and Control Change Requirements;
AEC-Q101 Qualified and PPAP Capable*
These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS
Compliant
R2
Q1
Q2
R2
Features
•
•
•
•
(1)
(4)
R1
(5)
(6)
MARKING DIAGRAMS
6
SOT−363
CASE 419B−02
33 MG
G
1
MAXIMUM RATINGS
(TA = 25°C both polarities Q1 (PNP) & Q2 (NPN), unless otherwise noted)
Rating
Symbol
Max
Unit
Collector-Base Voltage
VCBO
50
Vdc
Collector-Emitter Voltage
VCEO
50
Vdc
Collector Current − Continuous
100
mAdc
VIN(fwd)
30
Vdc
Input Reverse Voltage
VIN(rev)
5
Vdc
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
ORDERING INFORMATION
Package
Shipping†
MUN5333DW1T1G,
NSVMUN5333DW1T1G*
SOT−363
3,000/Tape & Reel
NSVMUN5333DW1T3G*
SOT−363
10,000/Tape & Reel
NSBC143ZPDXV6T1G
NSVBC143ZPDXV6T1G*
SOT−563
4,000/Tape & Reel
NSVBC143ZPDXV6T5G*
SOT−563
8,000/Tape & Reel
NSBC143ZPDP6T5G
SOT−963
8,000/Tape & Reel
Device
SOT−963
CASE 527AD
33/Y
M
G
33 MG
1
Y
IC
Input Forward Voltage
SOT−563
CASE 463A
M
1
= Specific Device Code
= Date Code*
= Pb-Free Package
(Note: Microdot may be in either location)
*Date Code orientation may vary depending
upon manufacturing location.
†For information on tape and reel specifications, including part orientation and
tape sizes, please refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
April, 2021 − Rev. 7
1
Publication Order Number:
DTC143ZP/D
MUN5333DW1, NSBC143ZPDXV6, NSBC143ZPDP6
THERMAL CHARACTERISTICS
Characteristic
Symbol
Max
Unit
187
256
1.5
2.0
mW
MUN5333DW1 (SOT−363) ONE JUNCTION HEATED
Total Device Dissipation
TA = 25°C
(Note 1)
(Note 2)
Derate above 25°C
(Note 1)
(Note 2)
Thermal Resistance,
Junction to Ambient
PD
(Note 1)
(Note 2)
RqJA
mW/°C
670
490
°C/W
250
385
2.0
3.0
mW
MUN5333DW1 (SOT−363) BOTH JUNCTION HEATED (Note 3)
PD
Total Device Dissipation
(Note 1)
TA = 25°C
(Note 2)
Derate above 25°C
(Note 1)
(Note 2)
Thermal Resistance,
Junction to Ambient
(Note 2)
RqJA
(Note 1)
Thermal Resistance,
Junction to Lead (Note 1)
(Note 2)
RqJL
Junction and Storage Temperature Range
TJ, Tstg
493
325
188
208
mW/°C
°C/W
°C/W
−55 to +150
°C
357
2.9
mW
mW/°C
NSBC143ZPDXV6 (SOT−563) ONE JUNCTION HEATED
PD
Total Device Dissipation
(Note 1)
TA = 25°C
Derate above 25°C
(Note 1)
Thermal Resistance,
Junction to Ambient
RqJA
(Note 1)
350
°C/W
NSBC143ZPDXV6 (SOT−563) BOTH JUNCTION HEATED (Note 3)
PD
Total Device Dissipation
(Note 1)
TA = 25°C
Derate above 25°C
(Note 1)
Thermal Resistance,
Junction to Ambient
RqJA
(Note 1)
Junction and Storage Temperature Range
TJ, Tstg
500
4.0
250
mW
mW/°C
°C/W
−55 to +150
°C
231
269
1.9
2.2
MW
NSBC143ZPDP6 (SOT−963) ONE JUNCTION HEATED
PD
Total Device Dissipation
(Note 4)
TA = 25°C
(Note 5)
Derate above 25°C
(Note 4)
(Note 5)
Thermal Resistance,
Junction to Ambient
(Note 5)
RqJA
(Note 4)
540
464
mW/°C
°C/W
NSBC143ZPDP6 (SOT−963) BOTH JUNCTION HEATED (Note 3)
PD
Total Device Dissipation
(Note 4)
TA = 25°C
(Note 5)
Derate above 25°C
(Note 4)
(Note 5)
Thermal Resistance,
Junction to Ambient
(Note 5)
RqJA
(Note 4)
Junction and Storage Temperature Range
1.
2.
3.
4.
5.
TJ, Tstg
FR−4 @ Minimum Pad.
FR−4 @ 1.0 × 1.0 Inch Pad.
Both junction heated values assume total power is sum of two equally powered channels.
FR−4 @ 100 mm2, 1 oz. copper traces, still air.
FR−4 @ 500 mm2, 1 oz. copper traces, still air.
www.onsemi.com
2
339
408
2.7
3.3
369
306
−55 to +150
MW
mW/°C
°C/W
°C
MUN5333DW1, NSBC143ZPDXV6, NSBC143ZPDP6
ELECTRICAL CHARACTERISTICS (TA = 25°C both polarities Q1 (PNP) & Q2 (NPN), unless otherwise noted)
Symbol
Characteristic
Min
Typ
Max
−
−
100
−
−
500
−
−
0.18
50
−
−
50
−
−
80
200
−
−
−
0.25
−
−
0.1
−
0.6
0.5
1.3
0.9
−
−
−
0.2
4.9
−
−
Unit
OFF CHARACTERISTICS
Collector-Base Cutoff Current
(VCB = 50 V, IE = 0)
ICBO
Collector-Emitter Cutoff Current
(VCE = 50 V, IB = 0)
ICEO
Emitter-Base Cutoff Current
(VEB = 6.0 V, IC = 0)
IEBO
Collector-Base Breakdown Voltage
(IC = 10 mA, IE = 0)
V(BR)CBO
Collector-Emitter Breakdown Voltage (Note 6)
(IC = 2.0 mA, IB = 0)
V(BR)CEO
nAdc
nAdc
mAdc
Vdc
Vdc
ON CHARACTERISTICS
hFE
DC Current Gain (Note 6)
(IC = 5.0 mA, VCE = 10 V)
Collector-Emitter Saturation Voltage (Note 6)
(IC = 10 mA, IB = 1.0 mA)
VCE(sat)
Collector-Emitter Saturation Voltage (MUN5333DW1) (Note 6)
(IC = 5 mA, IB = 0.25 mA)
VCE(sat)
Input Voltage (Off)
(VCE = 5.0 V, IC = 100 mA)
Vin(off)
Input Voltage (On)
(VCE = 0.3 V, IC = 5.0 mA)
Vin(on)
Output Voltage (On)
(VCC = 5.0 V, VB = 2.5 V, RL = 1.0 kW)
VOL
Output Voltage (Off)
(VCC = 5.0 V, VB = 0.5 V, RL = 1.0 kW)
VOH
Input Resistor
R1
3.3
4.7
6.1
Resistor Ratio
R1/R2
0.08
0.1
0.14
6. Pulsed Condition: Pulse Width = 300 ms, Duty Cycle ≤ 2%.
PD, POWER DISSIPATION (mW)
400
350
300
250
200
(1) SOT−363; 1.0 × 1.0 Inch Pad
(2) SOT−563; Minimum Pad
(3) SOT−963; 100 mm2, 1 oz. Copper Trace
(1) (2) (3)
150
100
50
0
−50
−25
0
25
50
75
100
125
150
AMBIENT TEMPERATURE (°C)
Figure 1. Derating Curve
www.onsemi.com
3
V
V
Vdc
Vdc
Vdc
Vdc
kW
MUN5333DW1, NSBC143ZPDXV6, NSBC143ZPDP6
TYPICAL CHARACTERISTICS − NPN TRANSISTOR
MUN5333DW1, NSBC143ZPDXV6
1000
VCE = 10 V
IC/IB = 10
0.1
hFE, DC CURRENT GAIN
VCE(sat), COLLECTOR−EMITTER
SATURATION VOLTAGE (V)
1
150°C
−55°C
150°C
100
−55°C
25°C
25°C
0.01
1
10
10
100
1
10
IC, COLLECTOR CURRENT (mA)
IC, COLLECTOR CURRENT (mA)
Figure 2. VCE(sat) versus IC
Figure 3. DC Current Gain
3.2
100
2
1.6
1.2
0.8
0.4
0
10
20
30
40
50
150°C
10
−55°C
1
0.1
25°C
0.01
VO = 5 V
0.001
0
1
2
3
VR, REVERSE BIAS VOLTAGE (V)
Vin, INPUT VOLTAGE (V)
Figure 4. Output Capacitance
Figure 5. Output Current versus Input Voltage
10
Vin, INPUT VOLTAGE (V)
Cob, CAPACITANCE (pF)
2.4
IC, COLLECTOR CURRENT (mA)
f = 10 kHz
IE = 0 A
TA = 25°C
2.8
0
100
−55°C
1
150°C
25°C
VO = 0.2 V
0.1
0
10
20
30
40
IC, COLLECTOR CURRENT (mA)
Figure 6. Input Voltage versus Output Current
www.onsemi.com
4
50
4
MUN5333DW1, NSBC143ZPDXV6, NSBC143ZPDP6
1
1000
VCE = 10 V
IC/IB = 10
hFE, DC CURRENT GAIN
VCE(sat), COLLECTOR−EMITTER VOLTAGE (V)
TYPICAL CHARACTERISTICS − PNP TRANSISTOR
MUN5333DW1, NSBC143ZPDXV6
75°C
0.1
−25°C
25°C
0.01
0.001
0
20
40
30
10
IC, COLLECTOR CURRENT (mA)
75°C
100
1
10
IC, COLLECTOR CURRENT (mA)
Figure 7. VCE(sat) vs. IC
100
9
8
7
IC, COLLECTOR CURRENT (mA)
f = 10 kHz
IE = 0 A
TA = 25°C
6
5
4
3
2
1
0
10
20
30
40
75°C
10
25°C
1
0.1
−25°C
0.01
0.001
50
VO = 5 V
VR, REVERSE BIAS VOLTAGE (V)
3
4
5
6
7
Vin, INPUT VOLTAGE (V)
Figure 9. Output Capacitance
Figure 10. Output Current vs. Input Voltage
0
1
2
10
Vin, INPUT VOLTAGE (V)
Cob, CAPACITANCE (pF)
100
Figure 8. DC Current Gain
10
0
25°C
10
1
50
−25°C
−25°C
1
75°C
25°C
VO = 0.2 V
0.1
0
10
20
30
40
IC, COLLECTOR CURRENT (mA)
Figure 11. Input Voltage vs. Output Current
www.onsemi.com
5
50
8
9
10
MUN5333DW1, NSBC143ZPDXV6, NSBC143ZPDP6
TYPICAL CHARACTERISTICS − NPN TRANSISTOR
NSBC143ZPDP6
1000
IC/IB = 10
hFE, DC CURRENT GAIN
VCE(sat), COLLECTOR−EMITTER
SATURATION VOLTAGE (V)
1
150°C
0.1
−55°C
150°C
−55°C
100
25°C
10
25°C
0.01
1
10
20
30
40
1
0.1
50
1
10
100
IC, COLLECTOR CURRENT (mA)
IC, COLLECTOR CURRENT (mA)
Figure 12. VCE(sat) versus IC
Figure 13. DC Current Gain
2.4
100
2
IC, COLLECTOR CURRENT (mA)
f = 10 kHz
IE = 0 A
TA = 25°C
1.6
1.2
0.8
0.4
0
0
10
20
30
40
50
150°C
−55°C
10
1
0.1
25°C
0.01
VO = 5 V
0.001
0
1
2
3
4
VR, REVERSE BIAS VOLTAGE (V)
Vin, INPUT VOLTAGE (V)
Figure 14. Output Capacitance
Figure 15. Output Current versus Input Voltage
100
Vin, INPUT VOLTAGE (V)
Cob, CAPACITANCE (pF)
VCE = 10 V
10
25°C
−55°C
1
150°C
VO = 0.2 V
0.1
0
10
20
30
40
IC, COLLECTOR CURRENT (mA)
Figure 16. Input Voltage versus Output
Current
www.onsemi.com
6
50
MUN5333DW1, NSBC143ZPDXV6, NSBC143ZPDP6
1
1000
IC/IB = 10
hFE, DC CURRENT GAIN
VCE(sat), COLLECTOR−EMITTER VOLTAGE (V)
TYPICAL CHARACTERISTICS − PNP TRANSISTOR
NSBC143ZPDP6
150°C
0.1
−55°C
25°C
0.01
1
10
20
30
150°C
100
−55°C
25°C
10
1
0.1
50
40
VCE = 10 V
1
IC, COLLECTOR CURRENT (mA)
Figure 17. VCE(sat) vs. IC
100
5
IC, COLLECTOR CURRENT (mA)
f = 10 kHz
IE = 0 A
TA = 25°C
6
4
3
2
1
0
10
20
30
40
50
150°C
−55°C
10
1
0.1
25°C
0.01
VO = 5 V
0.001
0
1
2
3
4
VR, REVERSE BIAS VOLTAGE (V)
Vin, INPUT VOLTAGE (V)
Figure 19. Output Capacitance
Figure 20. Output Current vs. Input Voltage
100
Vin, INPUT VOLTAGE (V)
Cob, CAPACITANCE (pF)
100
Figure 18. DC Current Gain
7
0
10
IC, COLLECTOR CURRENT (mA)
10
25°C
−55°C
1
150°C
VO = 0.2 V
0.1
0
10
20
30
40
IC, COLLECTOR CURRENT (mA)
Figure 21. Input Voltage vs. Output Current
www.onsemi.com
7
50
5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE Y
1
SCALE 2:1
DATE 11 DEC 2012
2X
aaa H D
D
H
A
D
6
5
GAGE
PLANE
4
1
2
L
L2
E1
E
DETAIL A
3
aaa C
2X
bbb H D
2X 3 TIPS
e
B
6X
b
ddd
TOP VIEW
C A-B D
M
A2
DETAIL A
A
6X
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.
4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF
THE PLASTIC BODY AND DATUM H.
5. DATUMS A AND B ARE DETERMINED AT DATUM H.
6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP.
7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OF THE FOOT.
ccc C
A1
SIDE VIEW
C
SEATING
PLANE
END VIEW
c
RECOMMENDED
SOLDERING FOOTPRINT*
6X
DIM
A
A1
A2
b
C
D
E
E1
e
L
L2
aaa
bbb
ccc
ddd
MILLIMETERS
MIN
NOM MAX
−−−
−−−
1.10
0.00
−−−
0.10
0.70
0.90
1.00
0.15
0.20
0.25
0.08
0.15
0.22
1.80
2.00
2.20
2.00
2.10
2.20
1.15
1.25
1.35
0.65 BSC
0.26
0.36
0.46
0.15 BSC
0.15
0.30
0.10
0.10
GENERIC
MARKING DIAGRAM*
6
XXXMG
G
6X
0.30
INCHES
NOM MAX
−−− 0.043
−−− 0.004
0.035 0.039
0.008 0.010
0.006 0.009
0.078 0.086
0.082 0.086
0.049 0.053
0.026 BSC
0.010 0.014 0.018
0.006 BSC
0.006
0.012
0.004
0.004
MIN
−−−
0.000
0.027
0.006
0.003
0.070
0.078
0.045
0.66
1
2.50
0.65
PITCH
XXX = Specific Device Code
M
= Date Code*
G
= Pb−Free Package
(Note: Microdot may be in either location)
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
*Date Code orientation and/or position may
vary depending upon manufacturing location.
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42985B
SC−88/SC70−6/SOT−363
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
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are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE Y
DATE 11 DEC 2012
STYLE 1:
PIN 1. EMITTER 2
2. BASE 2
3. COLLECTOR 1
4. EMITTER 1
5. BASE 1
6. COLLECTOR 2
STYLE 2:
CANCELLED
STYLE 3:
CANCELLED
STYLE 4:
PIN 1. CATHODE
2. CATHODE
3. COLLECTOR
4. EMITTER
5. BASE
6. ANODE
STYLE 5:
PIN 1. ANODE
2. ANODE
3. COLLECTOR
4. EMITTER
5. BASE
6. CATHODE
STYLE 6:
PIN 1. ANODE 2
2. N/C
3. CATHODE 1
4. ANODE 1
5. N/C
6. CATHODE 2
STYLE 7:
PIN 1. SOURCE 2
2. DRAIN 2
3. GATE 1
4. SOURCE 1
5. DRAIN 1
6. GATE 2
STYLE 8:
CANCELLED
STYLE 9:
PIN 1. EMITTER 2
2. EMITTER 1
3. COLLECTOR 1
4. BASE 1
5. BASE 2
6. COLLECTOR 2
STYLE 10:
PIN 1. SOURCE 2
2. SOURCE 1
3. GATE 1
4. DRAIN 1
5. DRAIN 2
6. GATE 2
STYLE 11:
PIN 1. CATHODE 2
2. CATHODE 2
3. ANODE 1
4. CATHODE 1
5. CATHODE 1
6. ANODE 2
STYLE 12:
PIN 1. ANODE 2
2. ANODE 2
3. CATHODE 1
4. ANODE 1
5. ANODE 1
6. CATHODE 2
STYLE 13:
PIN 1. ANODE
2. N/C
3. COLLECTOR
4. EMITTER
5. BASE
6. CATHODE
STYLE 14:
PIN 1. VREF
2. GND
3. GND
4. IOUT
5. VEN
6. VCC
STYLE 15:
PIN 1. ANODE 1
2. ANODE 2
3. ANODE 3
4. CATHODE 3
5. CATHODE 2
6. CATHODE 1
STYLE 16:
PIN 1. BASE 1
2. EMITTER 2
3. COLLECTOR 2
4. BASE 2
5. EMITTER 1
6. COLLECTOR 1
STYLE 17:
PIN 1. BASE 1
2. EMITTER 1
3. COLLECTOR 2
4. BASE 2
5. EMITTER 2
6. COLLECTOR 1
STYLE 18:
PIN 1. VIN1
2. VCC
3. VOUT2
4. VIN2
5. GND
6. VOUT1
STYLE 19:
PIN 1. I OUT
2. GND
3. GND
4. V CC
5. V EN
6. V REF
STYLE 20:
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. EMITTER
5. COLLECTOR
6. COLLECTOR
STYLE 21:
PIN 1. ANODE 1
2. N/C
3. ANODE 2
4. CATHODE 2
5. N/C
6. CATHODE 1
STYLE 22:
PIN 1. D1 (i)
2. GND
3. D2 (i)
4. D2 (c)
5. VBUS
6. D1 (c)
STYLE 23:
PIN 1. Vn
2. CH1
3. Vp
4. N/C
5. CH2
6. N/C
STYLE 24:
PIN 1. CATHODE
2. ANODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
STYLE 25:
PIN 1. BASE 1
2. CATHODE
3. COLLECTOR 2
4. BASE 2
5. EMITTER
6. COLLECTOR 1
STYLE 26:
PIN 1. SOURCE 1
2. GATE 1
3. DRAIN 2
4. SOURCE 2
5. GATE 2
6. DRAIN 1
STYLE 27:
PIN 1. BASE 2
2. BASE 1
3. COLLECTOR 1
4. EMITTER 1
5. EMITTER 2
6. COLLECTOR 2
STYLE 28:
PIN 1. DRAIN
2. DRAIN
3. GATE
4. SOURCE
5. DRAIN
6. DRAIN
STYLE 29:
PIN 1. ANODE
2. ANODE
3. COLLECTOR
4. EMITTER
5. BASE/ANODE
6. CATHODE
STYLE 30:
PIN 1. SOURCE 1
2. DRAIN 2
3. DRAIN 2
4. SOURCE 2
5. GATE 1
6. DRAIN 1
Note: Please refer to datasheet for
style callout. If style type is not called
out in the datasheet refer to the device
datasheet pinout or pin assignment.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42985B
SC−88/SC70−6/SOT−363
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOT−563, 6 LEAD
CASE 463A
ISSUE H
6
1
SCALE 4:1
DOCUMENT NUMBER:
DESCRIPTION:
98AON11126D
SOT−563, 6 LEAD
DATE 26 JAN 2021
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOT−563, 6 LEAD
CASE 463A
ISSUE H
DATE 26 JAN 2021
GENERIC
MARKING DIAGRAM*
XX MG
1
XX = Specific Device Code
M = Month Code
G
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON11126D
SOT−563, 6 LEAD
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOT−963
CASE 527AD−01
ISSUE E
DATE 09 FEB 2010
SCALE 4:1
D
X
Y
6
5
4
1
2
3
A
HE
E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS OF
BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS.
DIM
A
b
C
D
E
e
HE
L
L2
C
SIDE VIEW
TOP VIEW
e
6X
6X L2
6X
BOTTOM VIEW
L
MILLIMETERS
MIN
NOM
MAX
0.34
0.37
0.40
0.10
0.15
0.20
0.07
0.12
0.17
0.95
1.00
1.05
0.75
0.80
0.85
0.35 BSC
0.95
1.00
1.05
0.19 REF
0.05
0.10
0.15
GENERIC
MARKING DIAGRAM*
b
0.08 X Y
XM
1
STYLE 1:
PIN 1. EMITTER 1
2. BASE 1
3. COLLECTOR 2
4. EMITTER 2
5. BASE 2
6. COLLECTOR 1
STYLE 2:
PIN 1. EMITTER 1
2. EMITTER2
3. BASE 2
4. COLLECTOR 2
5. BASE 1
6. COLLECTOR 1
STYLE 3:
PIN 1. CATHODE 1
2. CATHODE 1
3. ANODE/ANODE 2
4. CATHODE 2
5. CATHODE 2
6. ANODE/ANODE 1
STYLE 4:
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. EMITTER
5. COLLECTOR
6. COLLECTOR
STYLE 5:
PIN 1. CATHODE
2. CATHODE
3. ANODE
4. ANODE
5. CATHODE
6. CATHODE
STYLE 6:
PIN 1. CATHODE
2. ANODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
STYLE 7:
PIN 1. CATHODE
2. ANODE
3. CATHODE
4. CATHODE
5. ANODE
6. CATHODE
STYLE 8:
PIN 1. DRAIN
2. DRAIN
3. GATE
4. SOURCE
5. DRAIN
6. DRAIN
STYLE 9:
PIN 1. SOURCE 1
2. GATE 1
3. DRAIN 2
4. SOURCE 2
5. GATE 2
6. DRAIN 1
STYLE 10:
PIN 1. CATHODE 1
2. N/C
3. CATHODE 2
4. ANODE 2
5. N/C
6. ANODE 1
DOCUMENT NUMBER:
DESCRIPTION:
X
M
= Specific Device Code
= Month Code
*This information is generic. Please refer
to device data sheet for actual part
marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
RECOMMENDED
MOUNTING FOOTPRINT
6X
0.20
6X
0.35
PACKAGE
OUTLINE
1.20
0.35
PITCH
DIMENSIONS: MILLIMETERS
98AON26456D
SOT−963, 1X1, 0.35P
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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