BSP19A
NPN Silicon Expitaxial
Transistor
This family of NPN Silicon Epitaxial transistors is designed for use
as a general purpose amplifier and in switching applications. The
device is housed in the SOT−223 package which is designed for
medium power surface mount applications.
Features
• High Voltage
• The SOT-223 Package Can Be Soldered Using Wave or Reflow
• SOT-223 Package Ensures Level Mounting, Resulting in Improved
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SOT−223 PACKAGE
NPN SILICON HIGH VOLTAGE
TRANSISTOR SURFACE MOUNT
Thermal Conduction, and Allows Visual Inspection of Soldered Joints
• The Formed Leads Absorb Thermal Stress During Soldering,
•
•
•
•
COLLECTOR 2,4
Eliminating the Possibility of Damage to the Die
PNP Complement is BSP16T1G
Moisture Sensitivity Level (MSL): 1
NSV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Symbol
Value
Unit
Collector-Emitter Voltage (Open Base)
VCEO
350
Vdc
Collector-Base Voltage (Open Emitter)
VCBO
400
Vdc
Emitter-Base Voltage (Open Collector)
VEBO
5.0
Vdc
IC
100
mAdc
Symbol
Max
Unit
PD
0.8
W
6.4
mW/°C
Collector Current (DC)
THERMAL CHARACTERISTICS
Characteristic
Total Power Dissipation @ TA = 25°C
(Note 1)
Derate above 25°C
EMITTER 3
MARKING
DIAGRAM
4
1
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
BASE
1
4
Collector
2
3
TO-261AA
CASE 318E
STYLE 1
AYW
SP19A G
G
1
Base
2
Collector
3
Emitter
A
= Assembly Location
Y
= Year
W
= Work Week
SP19A = Specific Device Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
Thermal Resistance, Junction−to−Ambient
RqJA
156
°C/W
Junction and Storage Temperature Range
Tstg
−65 to +150
°C
ESD − Human Body Model
HBM
3B
V
Device
Package
Shipping†
ESD − Machine Model
MM
C
V
BSP19AT1G
SOT−223
(Pb−Free)
1000 / Tape & Reel
NSVBSP19AT1G
SOT−223
(Pb−Free)
1000 / Tape & Reel
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Device mounted on a FR-4 glass epoxy printed circuit board using minimum
recommended footprint.
© Semiconductor Components Industries, LLC, 2013
January, 2019 − Rev. 12
1
ORDERING INFORMATION
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
BSP19AT1/D
BSP19A
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristics
Symbol
Min
Max
350
−
−
20
−
10
40
−
70
−
−
0.5
−
1.3
Unit
OFF CHARACTERISTICS
V(BR)CEO
Collector-Emitter Breakdown Voltage
(IC = 1.0 mAdc, IB = 0)
Collector-Base Cutoff Current
(VCB = 400 Vdc, IE = 0)
ICBO
Emitter-Base Cutoff Current
(VEB = 5.0 Vdc, IC = 0)
IEBO
Vdc
nAdc
mAdc
ON CHARACTERISTICS (Note 2)
hFE
DC Current Gain
(IC = 20 mAdc, VCE = 10 Vdc)
Current-Gain — Bandwidth Product
(IC = 10 mAdc, VCE = 10 Vdc, f = 5.0 MHz)
fT
Collector-Emitter Saturation Voltage
(IC = 50 mAdc, IB = 4.0 mAdc)
VCE(sat)
Base-Emitter Saturation Voltage
(IC = 50 mAdc, IB = 4.0 mAdc)
VBE(sat)
−
MHz
Vdc
Vdc
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle = 2.0%
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2
BSP19A
TYPICAL CHARACTERISTICS
1000
VCE(sat), COLLECTOR−EMITTER
SATURATION VOLTAGE (V)
1.2
hFE, DC CURRENT GAIN
VCE = 10 V
TJ = 125°C
100
TJ = 25°C
TJ = −55°C
10
1
0.0001
0.001
0.01
0.1
IC, COLLECTOR CURRENT (A)
IC/IB = 10
1
0.8
TJ = 125°C
0.6
0.4
TJ = 25°C
0.2
1
VBE(on), BASE−EMITTER ON VOLTAGE (V)
1
TJ = − 55°C
0.8
TJ = 25°C
TJ = 125°C
0.2
0.001
0.01
1
VCE = 10 V
1
TJ = − 55°C
0.8
0.6
TJ = 25°C
TJ = 125°C
0.4
0.2
0
0.0001
0.001
1
0.01
Figure 3. Base Saturation Voltage
Figure 4. Base ON Voltage
100
VCE = 10 V
10
0.1
1.2
IC, COLLECTOR CURRENT (A)
100
1
0.1
IC, COLLECTOR CURRENT (A)
C, CAPACITANCE (pF)
VBE(sat), BASE−EMITTER SATURATION
VOLTAGE (V)
FTau, CURRENT−GAIN − BANDWIDTH
PRODUCT (MHz)
IC/IB = 10
0
0.0001
0.01
Figure 2. Collector Saturation Voltage
1.2
0.4
0.001
IC, COLLECTOR CURRENT (A)
Figure 1. DC Current Gain
0.6
TJ = − 55°C
0
0.0001
1
10
CIBO
10
COBO
1
100
TJ = 25°C
f = 1.0 MHz
VCE = 10 V
0.1
1
10
100
IC, COLLECTOR CURRENT (mA)
IC, COLLECTOR CURRENT (mA)
Figure 5. Current Gain − Bandwidth Product
Figure 6. Capacitance
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3
1000
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOT−223 (TO−261)
CASE 318E−04
ISSUE R
DATE 02 OCT 2018
SCALE 1:1
q
q
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42680B
SOT−223 (TO−261)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
SOT−223 (TO−261)
CASE 318E−04
ISSUE R
STYLE 1:
PIN 1.
2.
3.
4.
BASE
COLLECTOR
EMITTER
COLLECTOR
STYLE 2:
PIN 1.
2.
3.
4.
ANODE
CATHODE
NC
CATHODE
STYLE 6:
PIN 1.
2.
3.
4.
RETURN
INPUT
OUTPUT
INPUT
STYLE 7:
PIN 1.
2.
3.
4.
ANODE 1
CATHODE
ANODE 2
CATHODE
STYLE 11:
PIN 1. MT 1
2. MT 2
3. GATE
4. MT 2
STYLE 3:
PIN 1.
2.
3.
4.
GATE
DRAIN
SOURCE
DRAIN
STYLE 8:
STYLE 12:
PIN 1. INPUT
2. OUTPUT
3. NC
4. OUTPUT
CANCELLED
DATE 02 OCT 2018
STYLE 4:
PIN 1.
2.
3.
4.
SOURCE
DRAIN
GATE
DRAIN
STYLE 5:
PIN 1.
2.
3.
4.
STYLE 9:
PIN 1.
2.
3.
4.
INPUT
GROUND
LOGIC
GROUND
STYLE 10:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
DRAIN
GATE
SOURCE
GATE
STYLE 13:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
GENERIC
MARKING DIAGRAM*
AYW
XXXXXG
G
1
A
= Assembly Location
Y
= Year
W
= Work Week
XXXXX = Specific Device Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42680B
SOT−223 (TO−261)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2018
www.onsemi.com
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, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
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