NST65010MW6
Dual Matched General
Purpose Transistor
PNP Matched Pair
These transistors are housed in an ultra−small SOT−363 package
ideally suited for portable products. They are assembled to create a
pair of devices highly matched in all parameters, eliminating the need
for costly trimming. Applications are Current Mirrors; Differential,
Sense and Balanced Amplifiers; Mixers; Detectors and Limiters.
Complementary NPN equivalent NST65011MW6T1G is available.
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6
1
SOT−363
CASE 419B
STYLE 1
Features
•
•
•
•
•
Current Gain Matching to 10%
Base−Emitter Voltage Matched to ≤ 2 mV
Drop−In Replacement for Standard Device
NSV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
(3)
(2)
(1)
Q1
Q2
(4)
(5)
(6)
MAXIMUM RATINGS
Symbol
Value
Unit
Collector −Emitter Voltage
Rating
VCEO
−65
V
Collector −Base Voltage
VCBO
−80
V
Emitter −Base Voltage
VEBO
−5.0
V
IC
−100
mAdc
Collector Current − Continuous
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL CHARACTERISTICS
Characteristic
Total Device Dissipation
Per Device
FR− 5 Board (Note 1)
TA = 25°C
Derate Above 25°C
Symbol
Max
Unit
PD
380
250
mW
3.0
mW/°C
4G MG
G
4G = Device Code
M
= Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Package
Shipping†
SOT−363
(Pb−Free)
3000 /
Tape & Reel
NSVT65010MW6T1G SOT−363
(Pb−Free)
3000 /
Tape & Reel
Device
NST65010MW6T1G
Thermal Resistance,
Junction to Ambient
RqJA
328
°C/W
Junction and Storage
Temperature Range
TJ, Tstg
−55 to +150
°C
1. FR−5 = 1.0 x 0.75 x 0.062 in.
© Semiconductor Components Industries, LLC, 2015
July, 2015 − Rev. 0
MARKING DIAGRAMS
1
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
NST65010MW6/D
NST65010MW6
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
Collector −Emitter Breakdown Voltage, (IC = −10 mA)
V(BR)CEO
−65
−
−
V
Collector −Emitter Breakdown Voltage, (IC = −10 mA, VEB = 0)
V(BR)CES
−80
−
−
V
Collector −Base Breakdown Voltage, (IC = −10 mA)
V(BR)CBO
−80
−
−
V
Emitter −Base Breakdown Voltage, (IE = −1.0 mA)
V(BR)EBO
−5.0
−
−
V
ICBO
−
−
−
−
−15
−5.0
nA
mA
−
220
0.9
150
290
1.0
−
475
1.1
−
−
−
−
−300
−650
−
−
−700
−900
−
−
VBE(1) − VBE(2)
−600
−
−
−
−
−1.0
−750
−820
−2.0
fT
100
−
−
MHz
Output Capacitance, (VCB = −10 V, f = 1.0 MHz)
Cob
−
−
4.5
pF
Noise Figure, (IC = −0.2 mA, VCE = −5 Vdc, RS = 2 kW, f = 1 kHz, BW = 200Hz)
NF
−
−
10
dB
OFF CHARACTERISTICS
Collector Cutoff Current (VCB = −30 V)
Collector Cutoff Current (VCB = −30 V, TA = 150°C)
ON CHARACTERISTICS
hFE
DC Current Gain
(IC = −10 mA, VCE = −5.0 V)
(IC = −2.0 mA, VCE = −5.0 V)
(IC = −2.0 mA, VCE = −5.0 V) (Note 2)
hFE(1)/hFE(2)
Collector −Emitter Saturation Voltage
(IC = −10 mA, IB = −0.5 mA)
(IC = −100 mA, IB = −5.0 mA)
VCE(sat)
Base −Emitter Saturation Voltage
(IC = −10 mA, IB = −0.5 mA)
(IC = −100 mA, IB = −5.0 mA)
VBE(sat)
Base −Emitter On Voltage
(IC = −2.0 mA, VCE = −5.0 V)
(IC = −10 mA, VCE = −5.0 V)
(IC = −2.0 mA, VCE = −5.0 V) (Note 3)
VBE(on)
−
mV
mV
mV
SMALL− SIGNAL CHARACTERISTICS
Current −Gain − Bandwidth Product, (IC = −10 mA, VCE = −5 Vdc, f = 100 MHz)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. hFE(1)/hFE(2) is the ratio of one transistor compared to the other transistor within the same package. The smaller hFE is used as numerator.
3. VBE(1) − VBE(2) is the absolute difference of one transistor compared to the other transistor within the same package.
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2
NST65010MW6
TYPICAL CHARACTERISTICS
-1.0
1.5
TA = 25°C
-0.9
VCE = -10 V
TA = 25°C
VBE(sat) @ IC/IB = 10
-0.8
V, VOLTAGE (VOLTS)
hFE , NORMALIZED DC CURRENT GAIN
2.0
1.0
0.7
0.5
-0.7
VBE(on) @ VCE = -10 V
-0.6
-0.5
-0.4
-0.3
-0.2
0.3
VCE(sat) @ IC/IB = 10
-0.1
0.2
-0.2
-0.5 -1.0 -2.0
-5.0 -10 -20
-50
IC, COLLECTOR CURRENT (mAdc)
0
-0.1 -0.2
-100 -200
Figure 1. Normalized DC Current Gain
1.0
θVB , TEMPERATURE COEFFICIENT (mV/ °C)
VCE , COLLECTOR-EMITTER VOLTAGE (V)
TA = 25°C
-1.6
-1.2
IC =
-10 mA
IC = -50 mA
IC = -200 mA
IC = -100 mA
IC = -20 mA
-0.4
0
-0.02
-55°C to +125°C
1.2
1.6
2.0
2.4
2.8
-10 -20
-0.1
-1.0
IB, BASE CURRENT (mA)
-0.2
10
Cib
7.0
TA = 25°C
5.0
Cob
3.0
2.0
1.0
-0.4 -0.6
-1.0
-2.0
-4.0 -6.0
-10
-10
-1.0
IC, COLLECTOR CURRENT (mA)
-100
Figure 4. Base−Emitter Temperature Coefficient
f,
T CURRENT-GAIN - BANDWIDTH PRODUCT (MHz)
Figure 3. Collector Saturation Region
C, CAPACITANCE (pF)
-100
-50
Figure 2. “Saturation” and “On” Voltages
-2.0
-0.8
-0.5 -1.0 -2.0
-5.0 -10 -20
IC, COLLECTOR CURRENT (mAdc)
-20 -30 -40
400
300
200
150
VCE = -10 V
TA = 25°C
100
80
60
40
30
20
-0.5
-1.0
-2.0 -3.0
-5.0
-10
-20
-30
-50
VR, REVERSE VOLTAGE (VOLTS)
IC, COLLECTOR CURRENT (mAdc)
Figure 5. Capacitances
Figure 6. Current−Gain − Bandwidth Product
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3
NST65010MW6
TYPICAL CHARACTERISTICS
The safe operating area curves indicate IC−VCE limits
of the transistor that must be observed for reliable
operation. Collector load lines for specific circuits must
fall below the limits indicated by the applicable curve.
The data of Figure 7 is based upon TJ(pk) = 150°C; TC
or TA is variable depending upon conditions.
200
IC, COLLECTOR CURRENT (mA)
1s
3 ms
100
50
TA = 25°C
TJ = 25°C
10
5.0
2.0
1.0
BONDING WIRE LIMIT
THERMAL LIMIT
SECOND BREAKDOWN LIMIT
5.0
10
30 45
VCE, COLLECTOR-EMITTER VOLTAGE (V)
65
100
Figure 7. Active Region Safe Operating Area
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4
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE Y
1
SCALE 2:1
DATE 11 DEC 2012
2X
aaa H D
D
H
A
D
6
5
GAGE
PLANE
4
1
2
L
L2
E1
E
DETAIL A
3
aaa C
2X
bbb H D
2X 3 TIPS
e
B
6X
b
ddd
TOP VIEW
C A-B D
M
A2
DETAIL A
A
6X
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.
4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF
THE PLASTIC BODY AND DATUM H.
5. DATUMS A AND B ARE DETERMINED AT DATUM H.
6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP.
7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OF THE FOOT.
ccc C
A1
SIDE VIEW
C
SEATING
PLANE
END VIEW
c
RECOMMENDED
SOLDERING FOOTPRINT*
6X
DIM
A
A1
A2
b
C
D
E
E1
e
L
L2
aaa
bbb
ccc
ddd
MILLIMETERS
MIN
NOM MAX
−−−
−−−
1.10
0.00
−−−
0.10
0.70
0.90
1.00
0.15
0.20
0.25
0.08
0.15
0.22
1.80
2.00
2.20
2.00
2.10
2.20
1.15
1.25
1.35
0.65 BSC
0.26
0.36
0.46
0.15 BSC
0.15
0.30
0.10
0.10
GENERIC
MARKING DIAGRAM*
6
XXXMG
G
6X
0.30
INCHES
NOM MAX
−−− 0.043
−−− 0.004
0.035 0.039
0.008 0.010
0.006 0.009
0.078 0.086
0.082 0.086
0.049 0.053
0.026 BSC
0.010 0.014 0.018
0.006 BSC
0.006
0.012
0.004
0.004
MIN
−−−
0.000
0.027
0.006
0.003
0.070
0.078
0.045
0.66
1
2.50
0.65
PITCH
XXX = Specific Device Code
M
= Date Code*
G
= Pb−Free Package
(Note: Microdot may be in either location)
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
*Date Code orientation and/or position may
vary depending upon manufacturing location.
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42985B
SC−88/SC70−6/SOT−363
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE Y
DATE 11 DEC 2012
STYLE 1:
PIN 1. EMITTER 2
2. BASE 2
3. COLLECTOR 1
4. EMITTER 1
5. BASE 1
6. COLLECTOR 2
STYLE 2:
CANCELLED
STYLE 3:
CANCELLED
STYLE 4:
PIN 1. CATHODE
2. CATHODE
3. COLLECTOR
4. EMITTER
5. BASE
6. ANODE
STYLE 5:
PIN 1. ANODE
2. ANODE
3. COLLECTOR
4. EMITTER
5. BASE
6. CATHODE
STYLE 6:
PIN 1. ANODE 2
2. N/C
3. CATHODE 1
4. ANODE 1
5. N/C
6. CATHODE 2
STYLE 7:
PIN 1. SOURCE 2
2. DRAIN 2
3. GATE 1
4. SOURCE 1
5. DRAIN 1
6. GATE 2
STYLE 8:
CANCELLED
STYLE 9:
PIN 1. EMITTER 2
2. EMITTER 1
3. COLLECTOR 1
4. BASE 1
5. BASE 2
6. COLLECTOR 2
STYLE 10:
PIN 1. SOURCE 2
2. SOURCE 1
3. GATE 1
4. DRAIN 1
5. DRAIN 2
6. GATE 2
STYLE 11:
PIN 1. CATHODE 2
2. CATHODE 2
3. ANODE 1
4. CATHODE 1
5. CATHODE 1
6. ANODE 2
STYLE 12:
PIN 1. ANODE 2
2. ANODE 2
3. CATHODE 1
4. ANODE 1
5. ANODE 1
6. CATHODE 2
STYLE 13:
PIN 1. ANODE
2. N/C
3. COLLECTOR
4. EMITTER
5. BASE
6. CATHODE
STYLE 14:
PIN 1. VREF
2. GND
3. GND
4. IOUT
5. VEN
6. VCC
STYLE 15:
PIN 1. ANODE 1
2. ANODE 2
3. ANODE 3
4. CATHODE 3
5. CATHODE 2
6. CATHODE 1
STYLE 16:
PIN 1. BASE 1
2. EMITTER 2
3. COLLECTOR 2
4. BASE 2
5. EMITTER 1
6. COLLECTOR 1
STYLE 17:
PIN 1. BASE 1
2. EMITTER 1
3. COLLECTOR 2
4. BASE 2
5. EMITTER 2
6. COLLECTOR 1
STYLE 18:
PIN 1. VIN1
2. VCC
3. VOUT2
4. VIN2
5. GND
6. VOUT1
STYLE 19:
PIN 1. I OUT
2. GND
3. GND
4. V CC
5. V EN
6. V REF
STYLE 20:
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. EMITTER
5. COLLECTOR
6. COLLECTOR
STYLE 21:
PIN 1. ANODE 1
2. N/C
3. ANODE 2
4. CATHODE 2
5. N/C
6. CATHODE 1
STYLE 22:
PIN 1. D1 (i)
2. GND
3. D2 (i)
4. D2 (c)
5. VBUS
6. D1 (c)
STYLE 23:
PIN 1. Vn
2. CH1
3. Vp
4. N/C
5. CH2
6. N/C
STYLE 24:
PIN 1. CATHODE
2. ANODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
STYLE 25:
PIN 1. BASE 1
2. CATHODE
3. COLLECTOR 2
4. BASE 2
5. EMITTER
6. COLLECTOR 1
STYLE 26:
PIN 1. SOURCE 1
2. GATE 1
3. DRAIN 2
4. SOURCE 2
5. GATE 2
6. DRAIN 1
STYLE 27:
PIN 1. BASE 2
2. BASE 1
3. COLLECTOR 1
4. EMITTER 1
5. EMITTER 2
6. COLLECTOR 2
STYLE 28:
PIN 1. DRAIN
2. DRAIN
3. GATE
4. SOURCE
5. DRAIN
6. DRAIN
STYLE 29:
PIN 1. ANODE
2. ANODE
3. COLLECTOR
4. EMITTER
5. BASE/ANODE
6. CATHODE
STYLE 30:
PIN 1. SOURCE 1
2. DRAIN 2
3. DRAIN 2
4. SOURCE 2
5. GATE 1
6. DRAIN 1
Note: Please refer to datasheet for
style callout. If style type is not called
out in the datasheet refer to the device
datasheet pinout or pin assignment.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42985B
SC−88/SC70−6/SOT−363
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
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