NTB25P06, NVB25P06
MOSFET – P-Channel,
D2PAK
-60 V, -27.5 A
Designed for low voltage, high speed switching applications and to
withstand high energy in the avalanche and commutation modes.
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Features
• AEC Q101 Qualified − NVB25P06
• These Devices are Pb−Free and are RoHS Compliant
V(BR)DSS
RDS(on) TYP
ID MAX
−60 V
65 mW @ −10 V
−27.5 A
Typical Applications
•
•
•
•
P−Channel
PWM Motor Controls
Power Supplies
Converters
Bridge Circuits
D
G
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
−60
V
Gate−to−Source Voltage
− Continuous
− Non−Repetitive (tpv10 ms)
VGS
VGSM
"15
"20
V
Vpk
Drain Current
− Continuous @ TA = 25°C
− Single Pulse (tpv10 ms)
ID
IDM
27.5
80
A
Apk
Total Power Dissipation @ TA = 25°C
PD
120
W
TJ, Tstg
−55 to
+175
°C
EAS
600
mJ
Operating and Storage
Temperature Range
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 25 V, VGS = 10 V,
IL(pk) = 20 A, L = 3 mH, RG = 25 W)
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient (Note 1)
− Junction−to−Ambient (Note 2)
Maximum Lead Temperature for Soldering
Purposes, (1/8″ from case for 10 s)
RqJC
RqJA
RqJA
1.25
46.8
63.2
TL
260
°C/W
°C
May, 2019 − Rev. 4
MARKING DIAGRAM
& PIN ASSIGNMENT
Drain
4
1
1
NTB
25P06G
AYWW
2
3
D2PAK
CASE 418B
Gate
A
Y
WW
G
Drain
Source
= Assembly Location
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Package
Shipping†
NTB25P06T4G
D2PAK
(Pb−Free)
800 / Tape & Reel
NVB25P06T4G
D2PAK
(Pb−Free)
800 / Tape & Reel
Device
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. When surface mounted to an FR4 board using 1″ pad size
(Cu Area 1.127 in2).
2. When surface mounted to an FR4 board using the minimum recommended
pad size (Cu Area 0.412 in2).
© Semiconductor Components Industries, LLC, 2011
S
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Publication Order Number:
NTB25P06/D
NTB25P06, NVB25P06
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
−60
−
−
64
−
−
−
−
−
−
−10
−100
−
−
±100
−2.0
−
−2.8
6.2
−4.0
−
−
−
0.065
0.070
0.075
0.082
−
13
−
Ciss
−
1200
1680
Coss
−
345
480
Crss
−
90
180
td(on)
−
14
24
ns
tr
−
72
118
ns
td(off)
−
43
68
ns
tf
−
190
320
ns
QT
−
33
50
nC
Q1
−
6.5
−
Q2
−
15
−
VSD
−
−
−1.8
−1.4
−2.5
−
V
trr
−
70
−
ns
ta
−
50
−
tb
−
20
−
QRR
−
0.2
−
OFF CHARACTERISTICS
V(BR)DSS
Drain−to−Source Breakdown Voltage (Note 3)
(VGS = 0 V, ID = −250 mA)
(Positive Temperature Coefficient)
Zero Gate Voltage Drain Current
(VGS = 0 V, VDS = −60 V, TJ = 25°C)
(VGS = 0 V, VDS = −60 V, , TJ = 150°C)
IDSS
Gate−Body Leakage Current (VGS = ± 15 V, VDS = 0 V)
IGSS
V
mV/°C
mA
nA
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
(VDS = VGS, ID = −250 mA)
(Negative Threshold Temperature Coefficient)
VGS(th)
Static Drain−Source On−State Resistance
(VGS = −10 V, ID = −12.5 A)
(VGS = −10 V, ID = −25 A)
RDS(on)
Forward Transconductance
(VDS = −10 V, ID = −12.5 A)
V
gFS
mV/°C
W
Mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = −25 V, VGS = 0 V,
F = 1.0 MHz)
Reverse Transfer Capacitance
pF
SWITCHING CHARACTERISTICS (Notes 3 & 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
(VDD = −30 V, ID = −25 A,
VGS = −10 V RG = 9.1 W)
Fall Time
Gate Charge
(VDS = −48 V, ID = −25 A,
VGS = −10 V)
BODY−DRAIN DIODE RATINGS (Note 3)
Diode Forward On−Voltage
(IS = −25 A, VGS = 0 V)
(IS = −25 A, VGS = 0 V, TJ = 150°C)
Reverse Recovery Time
(IS = −25 A, VGS = 0 V,
dIS/dt = 100 A/ms)
Reverse Recovery Stored Charge
3. Indicates Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.
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2
mC
NTB25P06, NVB25P06
VGS = −10 V
−ID, DRAIN CURRENT (AMPS)
45
50
TJ = 25°C
−7 V
−8 V
−9 V
−ID, DRAIN CURRENT (AMPS)
50
40
35
30
−6 V
25
20
−5.5 V
15
−5 V
10
−4.5 V
−4.2 V
5
0
0
2
4
6
8
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
TJ = 25°C
40
TJ = −55°C
30
10
2
4
6
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
TJ = 125°C
0.1
TJ = 25°C
TJ = −55°C
0
10
20
30
40
50
0.095
TJ = 25°C
0.085
VGS = −10 V
0.075
VGS = −15 V
0.065
10
20
30
40
50
−ID, DRAIN CURRENT (AMPS)
−ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance vs. Drain Current and
Temperature
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
1.75
1.5
10000
ID = −25 A
VGS = −10 V
−IDSS, LEAKAGE (nA)
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
VGS = −10 V
0.05
8
Figure 2. Transfer Characteristics
0.15
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
Figure 1. On−Region Characteristics
0.2
TJ = 125°C
20
0
10
VDS ≥ 10 V
1.25
1
VGS = 0 V
1000
TJ = 150°C
100
TJ = 125°C
0.75
0.5
−50
−25
0
25
50
75
100
125
150
10
0
10
20
30
40
50
TJ, JUNCTION TEMPERATURE (°C)
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
60
3000
2500
C, CAPACITANCE (pF)
VGS = 0 V
VDS = 0 V
TJ = 25°C
Ciss
2000
Crss
1500
Ciss
1000
Coss
500
Crss
0
10
5 −VGS 0 −VDS 5
10
15
20
25
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
NTB25P06, NVB25P06
10
8
Q1
4
2
0
ID = −25 A
TJ = 25°C
0
4
−IS, SOURCE CURRENT (AMPS)
25
t, TIME (ns)
td(off)
td(on)
10
1
VDD = −30 V
ID = −25 A
VGS = −10 V
1
10
100
20
1 ms
0.1
0.1
RDS(on) Limit
Thermal Limit
Package Limit
1
35
10
5
0
0
0.25
0.5
0.75
1
1.25
1.5
1.75
100 ms
10
100
Figure 10. Diode Forward Voltage vs. Current
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
−ID, DRAIN CURRENT (AMPS)
dc
10 ms
1
30
−VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
VGS = −20 V
SINGLE PULSE
TC = 25°C
10
25
15
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
100
20
VGS = 0 V
TJ = 25°C
RG, GATE RESISTANCE (W)
1000
15
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
1000
tf
10
Qg, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
100
VGS
Q2
6
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE
(VOLTS)
tr
QT
VDS
600
ID = −25 A
500
400
300
200
100
0
25
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
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4
150
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
D2PAK 3
CASE 418B−04
ISSUE L
DATE 17 FEB 2015
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 418B−01 THRU 418B−03 OBSOLETE,
NEW STANDARD 418B−04.
C
E
−B−
V
W
4
1
2
A
S
3
−T−
SEATING
PLANE
K
W
J
G
D
DIM
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
S
V
H
3 PL
0.13 (0.005)
M
T B
M
VARIABLE
CONFIGURATION
ZONE
N
R
P
L
M
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
L
M
F
F
F
VIEW W−W
1
VIEW W−W
2
VIEW W−W
3
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
MILLIMETERS
MIN
MAX
8.64
9.65
9.65 10.29
4.06
4.83
0.51
0.89
1.14
1.40
7.87
8.89
2.54 BSC
2.03
2.79
0.46
0.64
2.29
2.79
1.32
1.83
7.11
8.13
5.00 REF
2.00 REF
0.99 REF
14.60 15.88
1.14
1.40
U
L
M
INCHES
MIN
MAX
0.340 0.380
0.380 0.405
0.160 0.190
0.020 0.035
0.045 0.055
0.310 0.350
0.100 BSC
0.080
0.110
0.018 0.025
0.090
0.110
0.052 0.072
0.280 0.320
0.197 REF
0.079 REF
0.039 REF
0.575 0.625
0.045 0.055
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 4:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 5:
STYLE 6:
PIN 1. CATHODE
PIN 1. NO CONNECT
2. ANODE
2. CATHODE
3. CATHODE
3. ANODE
4. ANODE
4. CATHODE
MARKING INFORMATION AND FOOTPRINT ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42761B
D2PAK 3
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
D2PAK 3
CASE 418B−04
ISSUE L
DATE 17 FEB 2015
GENERIC
MARKING DIAGRAM*
xx
xxxxxxxxx
AWLYWWG
xxxxxxxxG
AYWW
AYWW
xxxxxxxxG
AKA
IC
Standard
Rectifier
xx
A
WL
Y
WW
G
AKA
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
= Polarity Indicator
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
SOLDERING FOOTPRINT*
10.49
8.38
16.155
2X
3.504
2X
1.016
5.080
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42761B
D2PAK 3
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
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