NTB30N20
Power MOSFET
30 Amps, 200 Volts
N−Channel Enhancement−Mode D2PAK
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Features
• Source−to−Drain Diode Recovery Time Comparable to a Discrete
•
•
•
•
VDSS
Fast Recovery Diode
Avalanche Energy Specified
IDSS and RDS(on) Specified at Elevated Temperature
Mounting Information Provided for the D2PAK Package
Pb−Free Packages are Available
200 V
RDS(ON) TYP
ID MAX
68 mW @ VGS = 10 V
30 A
N−Channel
D
Typical Applications
• PWM Motor Controls
• Power Supplies
• Converters
G
S
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
200
Vdc
Drain−to−Source Voltage (RGS = 1.0 MW)
VDGR
200
Vdc
Gate−to−Source Voltage
− Continuous
− Non−Repetitive (tpv10 ms)
VGS
VGSM
"30
"40
ID
ID
30
22
90
Adc
214
1.43
2.0
W
W/°C
W
−55 to
+175
°C
Drain Current
− Continuous @ TA 25°C
− Continuous @ TA 100°C
− Pulsed (Note 2)
Total Power Dissipation @ TA = 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C (Note 1)
IDM
PD
PD
TJ, Tstg
Single Drain−to−Source Avalanche Energy,
Starting TJ = 25°C
(VDD = 100 Vdc, VGS = 10 Vdc,
IL(pk) = 20 A, L = 3.0 mH, RG = 25 W)
EAS
Maximum Lead Temperature for Soldering
Purposes for 10 seconds
mJ
450
°C/W
RqJC
RqJA
RqJA
TL
August, 2005 − Rev. 4
4
1
0.7
62.5
50
2
°C
260
30N20G
AYWW
3
D2PAK
CASE 418B
STYLE 2
30N20
A
Y
WW
G
1
Gate
2
Drain
3
Source
= Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Package
Shipping †
NTB30N20
D2PAK
50 Units/Rail
NTB30N20G
D2PAK
50 Units/Rail
Device
(Pb−Free)
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. When surface mounted to an FR4 board using the minimum recommended
pad size, (Cu Area 0.412 in2).
2. Pulse Test: Pulse Width = 10 ms, Duty Cycle = 2%.
© Semiconductor Components Industries, LLC, 2005
4
Drain
Vdc
Operating and Storage Temperature Range
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient
− Junction−to−Ambient (Note 1)
MARKING DIAGRAM
& PIN ASSIGNMENT
1
NTB30N20T4
NTB30N20T4G
D2PAK
800 Tape & Reel
D2PAK
(Pb−Free)
800 Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Publication Order Number:
NTB30N20/D
NTB30N20
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)
Symbol
Characteristic
Min
Typ
Max
Unit
200
−
−
307
−
−
−
−
−
−
5.0
125
−
−
± 100
2.0
−
2.9
−8.9
4.0
−
−
−
−
0.068
0.067
0.200
0.081
0.080
0.240
−
2.0
2.5
gFS
−
20
−
Mhos
pF
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 mAdc)
Temperature Coefficient (Positive)
V(BR)DSS
Zero Gate Voltage Collector Current
(VGS = 0 Vdc, VDS = 200 Vdc, TJ = 25°C)
(VGS = 0 Vdc, VDS = 200 Vdc, TJ = 175°C)
IDSS
Gate−Body Leakage Current (VGS = ± 30 Vdc, VDS = 0)
IGSS
Vdc
mV/°C
mAdc
nAdc
ON CHARACTERISTICS
Gate Threshold Voltage
VDS = VGS, ID = 250 mAdc)
Temperature Coefficient (Negative)
VGS(th)
Static Drain−to−Source On−State Resistance
(VGS = 10 Vdc, ID = 15 Adc)
(VGS = 10 Vdc, ID = 10 Adc)
(VGS = 10 Vdc, ID = 15 Adc, TJ = 175°C)
RDS(on)
Drain−to−Source On−Voltage
(VGS = 10 Vdc, ID = 30 Adc)
VDS(on)
Forward Transconductance (VDS = 15 Vdc, ID = 15 Adc)
Vdc
mV/°C
W
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz)
Ciss
−
2335
−
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz)
(VDS = 160 Vdc, VGS = 0 Vdc, f = 1.0 MHz)
Coss
−
−
380
148
−
−
Reverse Transfer Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz)
Crss
−
75
−
td(on)
−
−
10
12
−
−
SWITCHING CHARACTERISTICS (Notes 3 & 4)
Turn−On Delay Time
ns
Rise Time
(VDD = 100 Vdc, ID = 18 Adc,
VGS = 5.0 Vdc, RG = 2.5 W)
tr
−
−
20
70
−
−
Turn−Off Delay Time
(VDD = 160 Vdc, ID = 30 Adc,
VGS = 10 Vdc, RG = 9.1 W)
td(off)
−
−
40
82
−
−
tf
−
−
24
88
−
−
Qtot
−
−
75
48
100
−
Qgs
−
−
20
16
−
−
Qgd
−
32
−
VSD
−
−
0.91
0.80
1.1
−
Vdc
trr
−
230
−
ns
ta
−
140
−
tb
−
85
−
QRR
−
1.85
−
Fall Time
Gate Charge
(VDS = 160 Vdc, ID = 30 Adc,
VGS = 10 Vdc)
(VDS = 160 Vdc, ID = 18 Adc,
VGS = 5.0 Vdc)
nC
BODY−DRAIN DIODE RATINGS (Note 3)
Forward On−Voltage
(IS = 30 Adc, VGS = 0 Vdc)
(IS = 30 Adc, VGS = 0 Vdc, TJ = 150°C)
Reverse Recovery Time
(IS = 30 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/ms)
Reverse Recovery Stored Charge
3. Indicates Pulse Test: P. W. = 300 ms max, Duty Cycle = 2%.
4. Switching characteristics are independent of operating junction temperature.
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2
mC
NTB30N20
60
VGS = 10 V
6V
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
60
9V
50
TJ = 25°C
8V
40
7V
30
5V
20
10
VDS ≥ 10 V
50
40
30
20
TJ = 25°C
10
TJ = 100°C
4V
0
0
8
2
4
6
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0
10
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
0.2
VGS = 10 V
TJ = 100°C
0.15
0.1
TJ = 25°C
0.05
0
TJ = −55°C
5
15
25
35
45
ID, DRAIN CURRENT (AMPS)
10
55
0.1
TJ = 25°C
0.09
VGS = 10 V
0.08
VGS = 15 V
0.07
0.06
0.05
5
Figure 3. On−Resistance versus Drain Current
and Temperature
15
25
35
45
ID, DRAIN CURRENT (AMPS)
55
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
3
2.5
2
4
6
8
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
100000
VGS = 0 V
ID = 15 A
VGS = 10 V
TJ = 175°C
10000
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
Figure 1. On−Region Characteristics
TJ = −55°C
2
1.5
1
1000
TJ = 100°C
100
0.5
0
−50 −25
0
25
50
75 100 125 150
TJ, JUNCTION TEMPERATURE (°C)
10
175
20
Figure 5. On−Resistance Variation with
Temperature
40
60
80 100 120 140 160 180 200
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 6. Drain−to−Source Leakage Current
versus Voltage
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3
NTB30N20
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
6000
VDS = 0 V
C, CAPACITANCE (pF)
5000
VGS = 0 V
TJ = 25°C
Ciss
4000
3000
Crss
Ciss
2000
1000
Coss
Crss
0
0
0
5
VGS
5
10
15
20
25
VDS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE
(VOLTS)
Figure 7. Capacitance Variation
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4
180
QT
VDS
10
150
120
8
6
Q1
VGS
Q2
90
60
4
ID = 30 A
TJ = 25°C
2
0
0
10
20
30
40
50
QG, TOTAL GATE CHARGE (nC)
60
30
0
70
1000
VDD = 160 V
ID = 30 A
VGS = 10 V
tf
100
t, TIME (ns)
12
VDS,DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
NTB30N20
tr
td(off)
10
1
td(on)
1
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
10
RG, GATE RESISTANCE (W)
100
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
IS, SOURCE CURRENT (AMPS)
30
25
VGS = 0 V
TJ = 25°C
20
15
10
5
0
0.5
0.6
0.7
0.8
0.9
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
1
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed
in
AN569,
“Transient
Thermal
Resistance−General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 ms. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) − TC)/(RqJC).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous ID can safely be assumed to
equal the values indicated.
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5
NTB30N20
I D, DRAIN CURRENT (AMPS)
1000
VGS = 20 V
SINGLE PULSE
TC = 25°C
100
10 ms
100 ms
10
1 ms
10 ms
1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
(NORMALIZED)
0.1
0.1
dc
1.0
10
100
1000
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
SAFE OPERATING AREA
500
ID = 30 A
400
300
200
100
0
25
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
50
75
100
125
150
175
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1.0
D = 0.5
0.2
0.1
0.1
P(pk)
0.05
0.02
t1
0.01
t2
DUTY CYCLE, D = t1/t2
SINGLE PULSE
0.01
0.00001
0.0001
0.001
0.01
t, TIME (ms)
RqJC(t) = r(t) RqJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) RqJC(t)
0.1
Figure 13. Thermal Response
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 14. Diode Reverse Recovery Waveform
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6
1.0
10
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
D2PAK 3
CASE 418B−04
ISSUE L
DATE 17 FEB 2015
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 418B−01 THRU 418B−03 OBSOLETE,
NEW STANDARD 418B−04.
C
E
−B−
V
W
4
1
2
A
S
3
−T−
SEATING
PLANE
K
W
J
G
D
DIM
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
S
V
H
3 PL
0.13 (0.005)
M
T B
M
VARIABLE
CONFIGURATION
ZONE
N
R
P
L
M
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
L
M
F
F
F
VIEW W−W
1
VIEW W−W
2
VIEW W−W
3
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
MILLIMETERS
MIN
MAX
8.64
9.65
9.65 10.29
4.06
4.83
0.51
0.89
1.14
1.40
7.87
8.89
2.54 BSC
2.03
2.79
0.46
0.64
2.29
2.79
1.32
1.83
7.11
8.13
5.00 REF
2.00 REF
0.99 REF
14.60 15.88
1.14
1.40
U
L
M
INCHES
MIN
MAX
0.340 0.380
0.380 0.405
0.160 0.190
0.020 0.035
0.045 0.055
0.310 0.350
0.100 BSC
0.080
0.110
0.018 0.025
0.090
0.110
0.052 0.072
0.280 0.320
0.197 REF
0.079 REF
0.039 REF
0.575 0.625
0.045 0.055
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 4:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 5:
STYLE 6:
PIN 1. CATHODE
PIN 1. NO CONNECT
2. ANODE
2. CATHODE
3. CATHODE
3. ANODE
4. ANODE
4. CATHODE
MARKING INFORMATION AND FOOTPRINT ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42761B
D2PAK 3
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
D2PAK 3
CASE 418B−04
ISSUE L
DATE 17 FEB 2015
GENERIC
MARKING DIAGRAM*
xx
xxxxxxxxx
AWLYWWG
xxxxxxxxG
AYWW
AYWW
xxxxxxxxG
AKA
IC
Standard
Rectifier
xx
A
WL
Y
WW
G
AKA
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
= Polarity Indicator
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
SOLDERING FOOTPRINT*
10.49
8.38
16.155
2X
3.504
2X
1.016
5.080
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42761B
D2PAK 3
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
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