NTB35N15G

NTB35N15 MOSFET – N-Channel, Enhancement Mode, D2PAK 37 A, 150 V http://onsemi.com Features • Source−to−Drain Diode Recovery Time Comparable to a Discrete • • • • 37 AMPERES, 150 VOLTS 50 m @ VGS = 10 V Fast Recovery Diode Avalanche Energy Specified IDSS and RDS(on) Specified at Elevated Temperature Mounting Information Provided for the D2PAK Package Pb−Free Packages are Available N−Channel D Typical Applications • PWM Motor Controls • Power Supplies • Converters G S MARKING DIAGRAM & PIN ASSIGNMENT MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Symbol Value Unit Drain−to−Source Voltage VDSS 150 Vdc Drain−to−Source Voltage (RGS = 1.0 M) VDGR 150 Vdc Gate−to−Source Voltage − Continuous − Non−Repetitive (tpv10 ms) VGS VGSM "20 "40 ID ID 37 23 111 Adc PD 178 1.43 2.0 W W/°C W TJ, Tstg −55 to +150 °C EAS 700 mJ Rating Drain Current − Continuous @ TA = 25°C − Continuous @ TA = 100°C − Pulsed (Note 2) Total Power Dissipation @ TA = 25°C Derate above 25°C Total Power Dissipation @ TA = 25°C (Note 1) Operating and Storage Temperature Range Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 100 Vdc, VGS = 10 Vdc, IL(pk) = 21.6 A, L = 3.0 mH, RG = 25 ) Thermal Resistance − Junction−to−Case − Junction−to−Ambient − Junction−to−Ambient (Note 1) Maximum Lead Temperature for Soldering Purposes, 1/8 in from case for 10 seconds Vdc IDM May, 2019 − Rev. 5 4 1 2 35N15G AYWW 3 D2PAK CASE 418B STYLE 2 35N15 A Y WW G 1 Gate 2 Drain 3 Source = Device Code = Assembly Location = Year = Work Week = Pb−Free Package ORDERING INFORMATION RJC RJA RJA 0.7 62.5 50 TL 260 °C/W °C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. When surface mounted to an FR4 board using the minimum recommended pad size, (Cu. Area 0.412 in2). © Semiconductor Components Industries, LLC, 2005 4 Drain 1 Package Shipping† NTB35N15 D2PAK 50 Units/Rail NTB35N15G D2PAK 50 Units/Rail Device (Pb−Free) NTB35N15T4 NTB35N15T4G D2PAK 800 Tape & Reel D2PAK (Pb−Free) 800 Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Publication Order Number: NTB35N15/D NTB35N15 2. Pulse Test: Pulse Width = 10 s, Duty Cycle = 2%. http://onsemi.com 2 NTB35N15 ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 150 − − 240 − − − − − − 5.0 50 − − ± 100 2.0 − 2.9 −8.56 4.0 − − − 0.042 − 0.050 0.120 − 1.55 1.78 gFS − 26 − mhos Ciss − 2275 3200 pF Coss − 450 650 Crss − 90 175 (VDD = 120 Vdc, ID = 37 Adc, VGS = 10 Vdc, RG = 9.1 ) td(on) − 20 35 tr − 125 225 td(off) − 90 175 tf − 120 210 (VDS = 120 Vdc, ID = 37 Adc, VGS = 10 Vdc) Qtot − 70 100 Qgs − 14 − Qgd − 32 − (IS = 37 Adc, VGS = 0 Vdc) (IS = 37 Adc, VGS = 0 Vdc, TJ = 125°C) VSD − − 1.00 0.88 1.5 − Vdc (IS = 37 Adc, VGS = 0 Vdc, dIS/dt = 100 A/s) trr − 170 − ns ta − 112 − tb − 58 − QRR − 1.14 − OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VGS = 0 Vdc, VDS = 150 Vdc, TJ = 25°C) (VGS = 0 Vdc, VDS = 150 Vdc, TJ = 125°C) IDSS Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) IGSS Vdc mV/°C Adc nAdc ON CHARACTERISTICS Gate Threshold Voltage VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) VGS(th) Static Drain−to−Source On−State Resistance (VGS = 10 Vdc, ID = 18.5 Adc) (VGS = 10 Vdc, ID = 18.5 Adc, TJ = 125°C) RDS(on) Drain−to−Source On−Voltage (VGS = 10 Vdc, ID = 18.5 Adc) VDS(on) Forward Transconductance (VDS = 10 Vdc, ID = 18.5 Adc) Vdc mV/°C  Vdc DYNAMIC CHARACTERISTICS (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Notes 3 & 4) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Total Gate Charge Gate−to−Source Charge Gate−to−Drain Charge ns nC BODY−DRAIN DIODE RATINGS (Note 3) Diode Forward On−Voltage Reverse Recovery Time Reverse Recovery Stored Charge 3. Pulse Test: Pulse Width = 300 s max, Duty Cycle = 2%. 4. Switching characteristics are independent of operating junction temperature. http://onsemi.com 3 C NTB35N15 60 VGS = 8 V 40 VGS = 7 V 30 20 VGS = 6 V VGS = 5 V VGS = 4.5 V 10 0 8 9 1 2 3 4 5 6 7 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 50 40 30 TJ = 100°C 20 TJ = 25°C 10 VGS = 4 V 0 VDS ≥ 10 V 60 VGS = 5.5 V VGS = 9 V 50 70 TJ = 25°C VGS = 10 V ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) 70 TJ = −55°C 0 10 2 VGS = 10 V 0.08 TJ = 100°C 0.06 TJ = 25°C 0.02 0 TJ = −55°C 0 10 20 30 40 50 ID, DRAIN CURRENT (AMPS) 60 70 RDS(on), DRAIN−TO−SOURCE RESISTANCE () 0.1 0.04 0.055 TJ = 25°C 0.05 VGS = 10 V 0.045 VGS = 15 V 0.04 0.035 0.03 0 Figure 3. On−Resistance versus Drain Current and Temperature 2.0 10 50 20 30 40 ID, DRAIN CURRENT (AMPS) 60 70 Figure 4. On−Resistance versus Drain Current and Gate Voltage 2.5 2.25 7 Figure 2. Transfer Characteristics 10,000 VGS = 0 V TJ = 150°C ID = 18.5 A VGS = 10 V IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) RDS(on), DRAIN−TO−SOURCE RESISTANCE () Figure 1. On−Region Characteristics 3 4 5 6 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 1.75 1.5 1.25 1.0 0.75 1000 100 TJ = 100°C 0.5 0.25 0 −50 −25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) 10 150 30 40 50 60 70 80 90 100 110 120 130 140 150 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current versus Voltage http://onsemi.com 4 NTB35N15 POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off−state condition when calculating td(on) and is read at a voltage corresponding to the on−state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain−gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG − VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn−on and turn−off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG − VGSP)] td(off) = RG Ciss In (VGG/VGSP) 6000 VDS = 0 V C, CAPACITANCE (pF) 5000 VGS = 0 V TJ = 25°C Ciss 4000 3000 Crss Ciss 2000 1000 Coss Crss 0 10 5 5 0 VGS 10 15 20 25 VDS GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation http://onsemi.com 5 120 10 QT VDS 100 VGS 8 Q1 6 80 Q2 60 40 4 ID = 37 A TJ = 25°C 2 0 0 10 20 30 40 50 QG, TOTAL GATE CHARGE (nC) 60 20 0 70 1000 VDD = 75 V ID = 37 A VGS = 10 V td(off) t, TIME (ns) 12 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) NTB35N15 tf tr 100 td(on) 10 1 Figure 8. Gate−To−Source and Drain−To−Source Voltage versus Total Charge 10 RG, GATE RESISTANCE (OHMS) 100 Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN−TO−SOURCE DIODE CHARACTERISTICS 40 VGS = 0 V TJ = 25°C I S , SOURCE CURRENT (AMPS) 35 30 25 20 15 10 5 0 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) 1 Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non−linearly with an increase of peak current in avalanche and peak junction temperature. Although many E−FETs can withstand the stress of drain−to−source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. The Forward Biased Safe Operating Area curves define the maximum simultaneous drain−to−source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance − General Data and Its Use.” Switching between the off−state and the on−state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) − TC)/(RJC). A Power MOSFET designated E−FET can be safely used in switching circuits with unclamped inductive loads. For http://onsemi.com 6 NTB35N15 SAFE OPERATING AREA VGS = 20 V SINGLE PULSE TC = 25°C 100 EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) I D , DRAIN CURRENT (AMPS) 1000 10 s 100 s 10 1 1 ms 10 ms dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 700 500 400 300 200 100 0.1 10 1.0 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) 0.1 ID = 21.6 A 600 0 25 1000 Figure 11. Maximum Rated Forward Biased Safe Operating Area 150 50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature 1.0 D = 0.5 0.2 0.1 0.1 P(pk) 0.05 0.02 t1 0.01 t2 DUTY CYCLE, D = t1/t2 SINGLE PULSE 0.01 0.00001 0.0001 0.001 0.01 t, TIME (s) RJC(t) = r(t) RJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TC = P(pk) RJC(t) 0.1 Figure 13. Thermal Response di/dt IS trr ta tb TIME 0.25 IS tp IS Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 7 1.0 10 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS D2PAK 3 CASE 418B−04 ISSUE L DATE 17 FEB 2015 SCALE 1:1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. 418B−01 THRU 418B−03 OBSOLETE, NEW STANDARD 418B−04. C E −B− V W 4 1 2 A S 3 −T− SEATING PLANE K W J G D DIM A B C D E F G H J K L M N P R S V H 3 PL 0.13 (0.005) M T B M VARIABLE CONFIGURATION ZONE N R P L M STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR L M F F F VIEW W−W 1 VIEW W−W 2 VIEW W−W 3 STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN MILLIMETERS MIN MAX 8.64 9.65 9.65 10.29 4.06 4.83 0.51 0.89 1.14 1.40 7.87 8.89 2.54 BSC 2.03 2.79 0.46 0.64 2.29 2.79 1.32 1.83 7.11 8.13 5.00 REF 2.00 REF 0.99 REF 14.60 15.88 1.14 1.40 U L M INCHES MIN MAX 0.340 0.380 0.380 0.405 0.160 0.190 0.020 0.035 0.045 0.055 0.310 0.350 0.100 BSC 0.080 0.110 0.018 0.025 0.090 0.110 0.052 0.072 0.280 0.320 0.197 REF 0.079 REF 0.039 REF 0.575 0.625 0.045 0.055 STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 4: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 5: STYLE 6: PIN 1. CATHODE PIN 1. NO CONNECT 2. ANODE 2. CATHODE 3. CATHODE 3. ANODE 4. ANODE 4. CATHODE MARKING INFORMATION AND FOOTPRINT ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42761B D2PAK 3 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com D2PAK 3 CASE 418B−04 ISSUE L DATE 17 FEB 2015 GENERIC MARKING DIAGRAM* xx xxxxxxxxx AWLYWWG xxxxxxxxG AYWW AYWW xxxxxxxxG AKA IC Standard Rectifier xx A WL Y WW G AKA = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package = Polarity Indicator *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. SOLDERING FOOTPRINT* 10.49 8.38 16.155 2X 3.504 2X 1.016 5.080 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98ASB42761B D2PAK 3 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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