NTB45N06T4

NTP45N06, NTB45N06 Power MOSFET 45 Amps, 60 Volts N−Channel TO−220 and D2PAK Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits. http://onsemi.com Features • • • • • • • • • Higher Current Rating Lower RDS(on) Lower VDS(on) Lower Capacitances Lower Total Gate Charge Tighter VSD Specification Lower Diode Reverse Recovery Time Lower Reverse Recovery Stored Charge Pb−Free Packages are Available 45 AMPERES, 60 VOLTS RDS(on) = 26 mW N−Channel D G Typical Applications • • • • S Power Supplies Converters Power Motor Controls Bridge Circuits 4 4 MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Symbol Value Unit Drain−to−Source Voltage VDSS 60 Vdc Drain−to−Gate Voltage (RGS = 10 MW) VDGR 60 Vdc Gate−to−Source Voltage − Continuous − Non−Repetitive (tpv10 ms) Vdc VGS VGS "20 "30 ID ID 45 30 150 Adc PD 125 0.83 3.2 2.4 W W/°C W W Operating and Storage Temperature Range TJ, Tstg −55 to +175 °C Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 50 Vdc, VGS = 10 Vdc, RG = 25 W, IL(pk) = 40 A, L = 0.3 mH, VDS = 60 Vdc) EAS 240 mJ Drain Current − Continuous @ TA = 25°C − Continuous @ TA = 100°C − Single Pulse (tpv10 ms) Total Power Dissipation @ TA = 25°C Derate above 25°C Total Power Dissipation @ TA = 25°C (Note 1) Total Power Dissipation @ TA = 25°C (Note 2) Thermal Resistance − Junction−to−Case − Junction−to−Ambient (Note 1) − Junction−to−Ambient (Note 2) Maximum Lead Temperature for Soldering Purposes, 1/8 in from case for 10 seconds IDM August, 2005 − Rev. 1 1 2 °C/W 1.2 46.8 63.2 TL 260 °C 1 3 TO−220AB CASE 221A STYLE 5 D2PAK CASE 418B STYLE 2 3 4 Drain 4 Drain NTx 45N06G AYWW NTx45N06G AYWW 1 Gate RqJC RqJA RqJA 2 MARKING DIAGRAMS & PIN ASSIGNMENTS Apk Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. When surface mounted to an FR4 board using 1 in pad size, (Cu Area 1.127 in2). 2. When surface mounted to an FR4 board using the minimum recommended pad size, (Cu Area 0.412 in2). © Semiconductor Components Industries, LLC, 2005 1 3 Source 1 Gate 2 Drain 3 Source 2 Drain NTx45N06 x A Y WW G = Device Code = B or P = Assembly Location = Year = Work Week = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. Publication Order Number: NTP45N06/D NTP45N06, NTB45N06 ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Symbol Characteristic Min Typ Max Unit 60 − 70 57 − − − − − − 1.0 10 − − ±100 2.0 − 2.8 7.2 4.0 − − 21 26 − − 0.93 0.93 1.4 − gFS − 16.6 − mhos pF OFF CHARACTERISTICS V(BR)DSS Drain−to−Source Breakdown Voltage (Note 3) (VGS = 0 Vdc, ID = 250 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C) IDSS Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/°C mAdc nAdc ON CHARACTERISTICS (Note 3) Gate Threshold Voltage (Note 3) (VDS = VGS, ID = 250 mAdc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain−to−Source On−Resistance (Note 3) (VGS = 10 Vdc, ID = 22.5 Adc) RDS(on) Static Drain−to−Source On−Voltage (Note 3) (VGS = 10 Vdc, ID = 45 Adc) (VGS = 10 Vdc, ID = 22.5 Adc, TJ = 150°C) VDS(on) Forward Transconductance (Note 3) (VDS = 8.0 Vdc, ID = 12 Adc) Vdc mV/°C mW Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Output Capacitance Transfer Capacitance Ciss − 1224 1725 Coss − 345 485 Crss − 76 160 td(on) − 10 25 200 SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time (VDD = 30 Vdc, ID = 45 Adc, VGS = 10 Vdc, RG = 9.1 W) (Note 3) Turn−Off Delay Time Fall Time Gate Charge (VDS = 48 Vdc, ID = 45 Adc, VGS = 10 Vdc) (Note 3) ns tr − 101 td(off) − 33 70 tf − 106 220 QT − 33 46 Q1 − 6.4 − Q2 − 15 − VSD − − 1.08 0.93 1.2 − Vdc trr − 53.1 − ns ta − 36 − tb − 16.9 − QRR − 0.087 − nC SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (IS = 45 Adc, VGS = 0 Vdc) (Note 3) (IS = 45 Adc, VGS = 0 Vdc, TJ = 150°C) Reverse Recovery Time (IS = 45 Adc, VGS = 0 Vdc, dIS/dt = 100 A/ms) (Note 3) Reverse Recovery Stored Charge mC 3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. ORDERING INFORMATION Package Shipping † NTP45N06 TO−220AB 50 Units / Rail NTP45N06G TO−220AB (Pb−Free) 50 Units / Rail D2PAK 50 Units / Rail NTB45N06G D2PAK (Pb−Free) 50 Units / Rail NTB45N06T4 D2PAK 800 Units / Tape & Reel NTB45N06T4G D2PAK 800 Units / Tape & Reel Device NTB45N06 (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 2 NTP45N06, NTB45N06 90 90 VGS = 10 V VGS = 7 V VDS > = 10 V VGS = 9 V 70 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) 80 VGS = 6.5 V 60 VGS = 8 V VGS = 6 V 50 VGS = 7.5 V 40 VGS = 5.5 V 30 VGS = 5 V 20 VGS = 4.5 V 10 80 70 60 50 40 30 TJ = 25°C 20 TJ = 100°C 10 TJ = −55°C 0 0 0 1 2 3 4 5 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 3 6 3.5 4 4.5 5 5.5 6 6.5 7 7.5 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 2. Transfer Characteristics RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) Figure 1. On−Region Characteristics 0.05 VGS = 10 V 0.042 0.034 TJ = 100°C 0.026 TJ = 25°C 0.018 TJ = −55°C 0 10 20 30 40 50 60 70 80 90 0.03 0.028 0.026 0.024 VGS = 10 V 0.022 0.02 0.018 VGS = 15 V 0 10 20 30 40 50 60 70 80 90 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance vs. Gate−to−Source Voltage Figure 4. On−Resistance vs. Drain Current and Gate Voltage 10000 2.2 2 0.032 VGS = 0 V ID = 22.5 A VGS = 10 V IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 0.01 8 1.8 1.6 1.4 1.2 TJ = 150°C 1000 TJ = 125°C 100 1 TJ = 100°C 0.8 0.6 −50 −25 10 0 25 50 75 100 125 150 175 0 10 20 30 40 50 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage http://onsemi.com 3 60 3600 VDS = 0 V 3200 VGS = 0 V TJ = 25°C Ciss C, CAPACITANCE (pF) 2800 Crss 2400 2000 1600 Ciss 1200 800 Coss 400 Crss 0 10 5 VGS 0 VDS 5 10 15 20 25 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) NTP45N06, NTB45N06 12 QT 10 VGS 8 Q1 6 Q2 4 2 ID = 45 TJ = 25°C 0 0 4 8 GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) 24 28 32 36 50 IS, SOURCE CURRENT (AMPS) VDS = 30 V ID = 45 A VGS = 10 V t, TIME (ns) 20 Figure 8. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge 1000 tf 100 tr td(off) td(on) 10 1 10 VGS = 0 V TJ = 25°C 40 30 20 10 0 0.6 0.64 0.68 0.72 0.76 0.8 0.84 0.88 0.92 0.96 1 1.04 100 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) RG, GATE RESISTANCE (W) 1000 VGS = 20 V SINGLE PULSE TC = 25°C 100 dc 10 ms 10 1 ms 1 0.1 0.10 RDS(on) Limit Thermal Limit Package Limit 1 100 ms 10 100 Figure 10. Diode Forward Voltage vs. Current EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) Figure 9. Resistive Switching Time Variation vs. Gate Resistance ID, DRAIN CURRENT (AMPS) 16 Qg, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation 1 12 280 ID = 45 A 240 200 160 120 80 40 0 25 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 50 75 100 125 150 TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 4 175 NTP45N06, NTB45N06 Normalized to RqJC at Steady State 0.1 r(t), EFFECTIVE TRANSIENT THERMAL RESPONSE (NORMALIZED) 1 0.01 0.00001 0.0001 0.001 0.01 0.1 1 10 t, TIME (s) Figure 13. Thermal Response r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) 10 Normalized to RqJA at Steady State, 1″ square Cu Pad, Cu Area 1.127 in2, 3 x 3 inch FR4 board 1 0.1 0.01 0.001 0.00001 0.0001 0.001 0.01 0.1 1 t, TIME (s) Figure 14. Thermal Response http://onsemi.com 5 10 100 1000 NTP45N06, NTB45N06 PACKAGE DIMENSIONS D2PAK CASE 418B−04 ISSUE J C NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. 418B−01 THRU 418B−03 OBSOLETE, NEW STANDARD 418B−04. E V W −B− 4 DIM A B C D E F G H J K L M N P R S V A 1 2 S 3 −T− SEATING PLANE K W J G D 3 PL 0.13 (0.005) VARIABLE CONFIGURATION ZONE H M T B M N R M STYLE 2: PIN 1. 2. 3. 4. P U L L M L M F F F VIEW W−W 1 VIEW W−W 2 VIEW W−W 3 SOLDERING FOOTPRINT* 8.38 0.33 1.016 0.04 10.66 0.42 5.08 0.20 3.05 0.12 17.02 0.67 SCALE 3:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 6 INCHES MIN MAX 0.340 0.380 0.380 0.405 0.160 0.190 0.020 0.035 0.045 0.055 0.310 0.350 0.100 BSC 0.080 0.110 0.018 0.025 0.090 0.110 0.052 0.072 0.280 0.320 0.197 REF 0.079 REF 0.039 REF 0.575 0.625 0.045 0.055 GATE DRAIN SOURCE DRAIN MILLIMETERS MIN MAX 8.64 9.65 9.65 10.29 4.06 4.83 0.51 0.89 1.14 1.40 7.87 8.89 2.54 BSC 2.03 2.79 0.46 0.64 2.29 2.79 1.32 1.83 7.11 8.13 5.00 REF 2.00 REF 0.99 REF 14.60 15.88 1.14 1.40 NTP45N06, NTB45N06 PACKAGE DIMENSIONS TO−220 CASE 221A−09 ISSUE AA −T− B SEATING PLANE C F T S 4 DIM A B C D F G H J K L N Q R S T U V Z A Q 1 2 3 U H K Z L R V J NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. G D N INCHES MIN MAX 0.570 0.620 0.380 0.405 0.160 0.190 0.025 0.035 0.142 0.147 0.095 0.105 0.110 0.155 0.018 0.025 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.045 0.055 0.235 0.255 0.000 0.050 0.045 −−− −−− 0.080 STYLE 5: PIN 1. 2. 3. 4. MILLIMETERS MIN MAX 14.48 15.75 9.66 10.28 4.07 4.82 0.64 0.88 3.61 3.73 2.42 2.66 2.80 3.93 0.46 0.64 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 1.15 1.39 5.97 6.47 0.00 1.27 1.15 −−− −−− 2.04 GATE DRAIN SOURCE DRAIN ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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