NTB45N06, NTBV45N06
MOSFET – N-Channel,
D2PAK
45 A, 60 V, 26 mW
Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
circuits.
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Features
•
•
•
•
•
•
•
•
•
•
Higher Current Rating
Lower RDS(on)
Lower VDS(on)
Lower Capacitances
Lower Total Gate Charge
Tighter VSD Specification
Lower Diode Reverse Recovery Time
Lower Reverse Recovery Stored Charge
AEC−Q101 Qualified and PPAP Capable − NTBV45N06
These Devices are Pb−Free and are RoHS Compliant
•
•
•
•
Power Supplies
Converters
Power Motor Controls
Bridge Circuits
45 AMPERES, 60 VOLTS
RDS(on) = 26 mW
N−Channel
D
G
S
Typical Applications
4
1
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
60
Vdc
Drain−to−Gate Voltage (RGS = 10 MW)
VDGR
60
Vdc
Gate−to−Source Voltage
− Continuous
− Non−Repetitive (tpv10 ms)
VGS
VGS
"20
"30
ID
ID
45
30
150
Adc
PD
125
0.83
3.2
2.4
W
W/°C
W
W
Rating
Drain Current
− Continuous @ TA = 25°C
− Continuous @ TA = 100°C
− Single Pulse (tpv10 ms)
Total Power Dissipation @ TA = 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C (Note 1)
Total Power Dissipation @ TA = 25°C (Note 2)
IDM
Vdc
TJ, Tstg
−55 to
+175
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 50 Vdc, VGS = 10 Vdc, RG = 25 W,
IL(pk) = 40 A, L = 0.3 mH, VDS = 60 Vdc)
EAS
240
mJ
RqJC
RqJA
RqJA
1.2
46.8
63.2
TL
260
Maximum Lead Temperature for Soldering
Purposes, 1/8 in from case for 10 seconds
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. When surface mounted to an FR4 board using 1 in pad size, (Cu Area 1.127 in2).
© Semiconductor Components Industries, LLC, 2011
May, 2019 − Rev. 1
3
D2PAK
CASE 418B
STYLE 2
MARKING DIAGRAMS
& PIN ASSIGNMENTS
4
Drain
Apk
Operating and Storage Temperature Range
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient (Note 1)
− Junction−to−Ambient (Note 2)
2
1
NTx
45N06G
AYWW
1
Gate
NTx45N06
x
A
Y
WW
G
2
Drain
3
Source
= Device Code
= B or P
= Assembly Location
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
Publication Order Number:
NTB45N06/D
NTB45N06, NTBV45N06
2. When surface mounted to an FR4 board using the minimum recommended
pad size, (Cu Area 0.412 in2).
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2
NTB45N06, NTBV45N06
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
60
−
70
57
−
−
−
−
−
−
1.0
10
−
−
±100
2.0
−
2.8
7.2
4.0
−
−
21
26
−
−
0.93
0.93
1.4
−
gFS
−
16.6
−
mhos
pF
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage (Note 3)
(VGS = 0 Vdc, ID = 250 mAdc)
Temperature Coefficient (Positive)
V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C)
IDSS
Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc)
IGSS
Vdc
mV/°C
mAdc
nAdc
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage (Note 3)
(VDS = VGS, ID = 250 mAdc)
Threshold Temperature Coefficient (Negative)
VGS(th)
Static Drain−to−Source On−Resistance (Note 3)
(VGS = 10 Vdc, ID = 22.5 Adc)
RDS(on)
Static Drain−to−Source On−Voltage (Note 3)
(VGS = 10 Vdc, ID = 45 Adc)
(VGS = 10 Vdc, ID = 22.5 Adc, TJ = 150°C)
VDS(on)
Forward Transconductance (Note 3) (VDS = 8.0 Vdc, ID = 12 Adc)
Vdc
mV/°C
mW
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Output Capacitance
Transfer Capacitance
Ciss
−
1224
1725
Coss
−
345
485
Crss
−
76
160
td(on)
−
10
25
200
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
(VDD = 30 Vdc, ID = 45 Adc,
VGS = 10 Vdc, RG = 9.1 W) (Note 3)
Turn−Off Delay Time
Fall Time
Gate Charge
(VDS = 48 Vdc, ID = 45 Adc,
VGS = 10 Vdc) (Note 3)
ns
tr
−
101
td(off)
−
33
70
tf
−
106
220
QT
−
33
46
Q1
−
6.4
−
Q2
−
15
−
VSD
−
−
1.08
0.93
1.2
−
Vdc
trr
−
53.1
−
ns
ta
−
36
−
tb
−
16.9
−
QRR
−
0.087
−
nC
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(IS = 45 Adc, VGS = 0 Vdc) (Note 3)
(IS = 45 Adc, VGS = 0 Vdc, TJ = 150°C)
Reverse Recovery Time
(IS = 45 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/ms) (Note 3)
Reverse Recovery Stored Charge
mC
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.
ORDERING INFORMATION
Package
Shipping†
D2PAK
800 / Tape & Reel
D2PAK
(Pb−Free)
800 / Tape & Reel
Device
NTB45N06T4G
(Pb−Free)
NTBV45N06T4G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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3
NTB45N06, NTBV45N06
VGS = 10 V
ID, DRAIN CURRENT (AMPS)
80
VGS = 9 V
70
VGS = 6.5 V
60
50
40
VGS = 8 V
VGS = 6 V
VGS = 7.5 V
VGS = 5.5 V
30
VGS = 5 V
20
VGS = 4.5 V
10
0
90
VGS = 7 V
ID, DRAIN CURRENT (AMPS)
90
0
4
5
1
2
3
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VDS > = 10 V
80
70
60
50
40
30
TJ = 25°C
20
TJ = 100°C
10
0
6
TJ = −55°C
3
3.5
4
4.5
5
5.5
6
6.5
7
7.5
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
0.05
VGS = 10 V
0.042
0.034
TJ = 100°C
0.026
TJ = 25°C
0.018
0
10
20
30
40
50
60
70
80
90
0.03
0.028
0.026
0.024
VGS = 10 V
0.022
0.02
0.018
VGS = 15 V
0
10
20
30
40
50
60
70
90
80
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
10000
2.2
2
0.032
ID = 22.5 A
VGS = 10 V
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
0.01
TJ = −55°C
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
Figure 1. On−Region Characteristics
8
1.8
1.6
1.4
1.2
VGS = 0 V
TJ = 150°C
1000
TJ = 125°C
100
1
TJ = 100°C
0.8
0.6
−50 −25
0
25
50
75
100
125
150
175
10
0
10
20
30
40
50
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
http://onsemi.com
4
60
3600
3200
TJ = 25°C
Ciss
2800
C, CAPACITANCE (pF)
VGS = 0 V
VDS = 0 V
Crss
2400
2000
1600
Ciss
1200
800
Coss
400
Crss
0
10
5 VGS 0 VDS 5
10
15
20
25
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
NTB45N06, NTBV45N06
12
QT
10
VGS
8
Q1
6
4
2
ID = 45
TJ = 25°C
0
0
4
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE
(VOLTS)
100
tr
td(off)
td(on)
10
1
IS, SOURCE CURRENT (AMPS)
t, TIME (ns)
tf
1
10
40
0.1
0.10
1 ms
1
32
36
20
10
100 ms
10
100
Figure 10. Diode Forward Voltage vs. Current
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
ID, DRAIN CURRENT (AMPS)
10 ms
RDS(on) Limit
Thermal Limit
Package Limit
28
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
dc
1
24
0
0.6 0.64 0.68 0.72 0.76 0.8 0.84 0.88 0.92 0.96 1 1.04
100
VGS = 20 V
SINGLE PULSE
TC = 25°C
10
20
30
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
100
16
VGS = 0 V
TJ = 25°C
RG, GATE RESISTANCE (W)
1000
12
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
50
VDS = 30 V
ID = 45 A
VGS = 10 V
8
Qg, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
1000
Q2
280
ID = 45 A
240
200
160
120
80
40
0
25
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
50
75
100
125
150
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
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5
175
NTB45N06, NTBV45N06
Normalized to RqJC at Steady State
0.1
r(t),
EFFECTIVE TRANSIENT THERMAL RESPONSE (NORMALIZED)
1
0.01
0.00001
0.0001
0.001
0.01
0.1
1
10
t, TIME (s)
Figure 13. Thermal Response
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED)
10
Normalized to RqJA at Steady State,
1″ square Cu Pad, Cu Area 1.127 in2,
3 x 3 inch FR4 board
1
0.1
0.01
0.001
0.00001
0.0001
0.001
0.01
0.1
1
t, TIME (s)
Figure 14. Thermal Response
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6
10
100
1000
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
D2PAK 3
CASE 418B−04
ISSUE L
DATE 17 FEB 2015
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 418B−01 THRU 418B−03 OBSOLETE,
NEW STANDARD 418B−04.
C
E
−B−
V
W
4
1
2
A
S
3
−T−
SEATING
PLANE
K
W
J
G
D
DIM
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
S
V
H
3 PL
0.13 (0.005)
M
T B
M
VARIABLE
CONFIGURATION
ZONE
N
R
P
L
M
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
L
M
F
F
F
VIEW W−W
1
VIEW W−W
2
VIEW W−W
3
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
MILLIMETERS
MIN
MAX
8.64
9.65
9.65 10.29
4.06
4.83
0.51
0.89
1.14
1.40
7.87
8.89
2.54 BSC
2.03
2.79
0.46
0.64
2.29
2.79
1.32
1.83
7.11
8.13
5.00 REF
2.00 REF
0.99 REF
14.60 15.88
1.14
1.40
U
L
M
INCHES
MIN
MAX
0.340 0.380
0.380 0.405
0.160 0.190
0.020 0.035
0.045 0.055
0.310 0.350
0.100 BSC
0.080
0.110
0.018 0.025
0.090
0.110
0.052 0.072
0.280 0.320
0.197 REF
0.079 REF
0.039 REF
0.575 0.625
0.045 0.055
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 4:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 5:
STYLE 6:
PIN 1. CATHODE
PIN 1. NO CONNECT
2. ANODE
2. CATHODE
3. CATHODE
3. ANODE
4. ANODE
4. CATHODE
MARKING INFORMATION AND FOOTPRINT ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42761B
D2PAK 3
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
D2PAK 3
CASE 418B−04
ISSUE L
DATE 17 FEB 2015
GENERIC
MARKING DIAGRAM*
xx
xxxxxxxxx
AWLYWWG
xxxxxxxxG
AYWW
AYWW
xxxxxxxxG
AKA
IC
Standard
Rectifier
xx
A
WL
Y
WW
G
AKA
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
= Polarity Indicator
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
SOLDERING FOOTPRINT*
10.49
8.38
16.155
2X
3.504
2X
1.016
5.080
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42761B
D2PAK 3
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
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