NTB52N10T4G

NTB52N10 Power MOSFET 52 Amps, 100 Volts N−Channel Enhancement−Mode D2PAK http://onsemi.com Features • Source−to−Drain Diode Recovery Time Comparable to a Discrete • • • • Fast Recovery Diode Avalanche Energy Specified IDSS and RDS(on) Specified at Elevated Temperature Mounting Information Provided for the D2PAK Package Pb−Free Packages are Available VDSS RDS(ON) TYP ID MAX 100 V 23 mW @ 10 V 52 A N−Channel D Typical Applications • PWM Motor Controls • Power Supplies • Converters G S MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Symbol Value Unit Drain−to−Source Voltage VDSS 100 Vdc Drain−to−Source Voltage (RGS = 1.0 MW) VDGR 100 Vdc Gate−to−Source Voltage − Continuous − Non−Repetitive (tpv10 ms) VGS VGSM "20 "40 ID ID 52 40 156 PD 178 1.43 2.0 W W/°C W TJ, Tstg −55 to +150 °C EAS 800 mJ Drain Current − Continuous @ TC = 25°C − Continuous @ TC = 100°C − Pulsed (Note 1) Total Power Dissipation @ TC = 25°C Derate above 25°C Total Power Dissipation @ TA = 25°C (Note 2) Operating and Storage Temperature Range Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 50 Vdc, VGS = 10 Vdc, IL(pk) = 40 A, L = 1.0 mH, RG = 25 W) Thermal Resistance − Junction−to−Case − Junction−to−Ambient − Junction−to−Ambient (Note 2) Maximum Lead Temperature for Soldering Purposes, 1/8in from case for 10 seconds Vdc Adc IDM RqJC RqJA RqJA 0.7 62.5 50 TL 260 March, 2011 − Rev. 4 NTB 52N10G AYWW 2 3 D2PAK CASE 418B STYLE 2 °C/W NTB52N10 A Y WW G 1 1 Gate 2 Drain 3 Source = Device Code = Assembly Location = Year = Work Week = Pb−Free Package ORDERING INFORMATION Package Shipping† NTB52N10 D2PAK 50 Units / Rail NTB52N10G D2PAK 50 Units / Rail Device °C 4 Drain 4 1 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Pulse Test: Pulse Width = 10 ms, Duty Cycle = 2%. 2. When surface mounted to an FR4 board using the minimum recommended pad size, (Cu. Area 0.412 in2). © Semiconductor Components Industries, LLC, 2011 MARKING DIAGRAM & PIN ASSIGNMENT (Pb−Free) NTB52N10T4 NTB52N10T4G D2PAK 800 / Tape & Reel D2PAK (Pb−Free) 800 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Publication Order Number: NTB52N10/D NTB52N10 ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) Symbol Characteristic Min Typ Max Unit 100 − − 160 − − − − − − 5.0 50 − − ± 100 2.0 − 2.92 −8.75 4.0 − − − 0.023 0.050 0.030 0.060 − 1.25 1.45 gFS − 31 − mhos Ciss − 2250 3150 pF Coss − 620 860 Crss − 135 265 td(on) − 15 25 tr − 95 180 td(off) − 74 150 OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VGS = 0 Vdc, VDS = 100 Vdc, TJ = 25°C) (VGS = 0 Vdc, VDS = 100 Vdc, TJ = 125°C) IDSS Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/°C mAdc nAdc ON CHARACTERISTICS Gate Threshold Voltage VDS = VGS, ID = 250 mAdc) Temperature Coefficient (Negative) VGS(th) Static Drain−to−Source On−State Resistance (VGS = 10 Vdc, ID = 26 Adc) (VGS = 10 Vdc, ID = 26 Adc, TJ = 125°C) RDS(on) Drain−to−Source On−Voltage (VGS = 10 Vdc, ID = 52 Adc) VDS(on) Forward Transconductance (VDS = 26 Vdc, ID = 10 Adc) Vdc mV/°C W Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Notes 3 & 4) Turn−On Delay Time (VDD = 80 Vdc, ID = 52 Adc, VGS = 10 Vdc, RG = 9.1 W) Rise Time Turn−Off Delay Time Fall Time Total Gate Charge (VDS = 80 Vdc, ID = 52 Adc, VGS = 10 Vdc) Gate−to−Source Charge Gate−to−Drain Charge ns tf − 100 190 Qtot − 72 135 Qgs − 13 − Qgd − 37 − VSD − − 1.06 0.95 1.5 − Vdc trr − 148 − ns ta − 106 − tb − 42 − QRR − 0.66 − nC BODY−DRAIN DIODE RATINGS (Note 3) Diode Forward On−Voltage (IS = 52 Adc, VGS = 0 Vdc) (IS = 37 Adc, VGS = 0 Vdc, TJ = 125°C) Reverse Recovery Time (IS = 52 Adc, VGS = 0 Vdc, dIS/dt = 100 A/ms) Reverse Recovery Stored Charge 3. Pulse Test: Pulse Width = 300 ms max, Duty Cycle = 2%. 4. Switching characteristics are independent of operating junction temperature. http://onsemi.com 2 mC NTB52N10 VGS = 10 V 90 7V 100 TJ = 25°C 9V 80 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) 100 6V 8V 70 60 5.5 V 50 40 5V 30 20 4.5 V 10 0 4V 0 1 2 3 4 5 6 7 8 9 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 90 VDS ≥ 10 V 80 70 60 50 40 TJ = 100°C 30 TJ = 25°C 20 TJ = −55°C 10 0 10 2 3 4 5 6 7 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 0.05 VGS = 10 V 0.04 TJ = 100°C 0.03 TJ = 25°C 0.02 TJ = −55°C 0.01 0 10 20 60 70 80 30 40 50 ID, DRAIN CURRENT (AMPS) 90 100 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) Figure 2. Transfer Characteristics 0.05 TJ = 25°C 0.04 0.03 VGS = 10 V 0.02 VGS = 15 V 0.01 0 0 Figure 3. On−Resistance versus Drain Current and Temperature 2.5 2.25 2.0 1.75 10 20 30 40 50 60 70 80 ID, DRAIN CURRENT (AMPS) 90 100 Figure 4. On−Resistance versus Drain Current and Gate Voltage 10,000 VGS = 0 V TJ = 150°C ID = 26 A VGS = 10 V IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) Figure 1. On−Region Characteristics 8 1.5 1.25 1.0 0.75 1000 100 TJ = 100°C 0.5 0.25 0 −60 −30 0 30 60 90 120 TJ, JUNCTION TEMPERATURE (°C) 10 150 30 Figure 5. On−Resistance Variation with Temperature 60 70 80 90 100 40 50 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 6. Drain−to−Source Leakage Current versus Voltage http://onsemi.com 3 NTB52N10 POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Dt) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain−gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off−state condition when calculating td(on) and is read at a voltage corresponding to the on−state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG − VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn−on and turn−off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG − VGSP)] td(off) = RG Ciss In (VGG/VGSP) 6000 C, CAPACITANCE (pF) 5000 VDS = 0 V VGS = 0 V TJ = 25°C Ciss 4000 3000 Crss Ciss 2000 1000 0 −10 Coss Crss −5 VGS 0 VDS 5 10 15 20 GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation http://onsemi.com 4 25 NTB52N10 QT 16 80 VDS 14 12 60 10 8 Q1 Q2 VGS 6 4 0 20 ID = 52 A TJ = 25°C 2 0 10 20 30 40 50 QG, TOTAL GATE CHARGE (nC) 60 40 70 0 1000 VDD = 80 V ID = 52 A VGS = 10 V tf td(off) tr 100 t, TIME (ns) VGS , GATE−TO−SOURCE VOLTAGE (VOLTS) 18 V DS,DRAIN−TO−SOURCE VOLTAGE (VOLTS) 100 20 td(on) 10 1 1 Figure 8. Gate−To−Source and Drain−To−Source Voltage versus Total Charge 10 RG, GATE RESISTANCE (OHMS) 100 Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN−TO−SOURCE DIODE CHARACTERISTICS IS , SOURCE CURRENT (AMPS) 60 50 VGS = 0 V TJ = 25°C 40 30 20 10 0 0.45 0.55 0.65 0.75 0.85 0.25 0.35 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) 0.95 Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain−to−source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance − General Data and Its Use.” Switching between the off−state and the on−state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 ms. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) − TC)/(RqJC). A Power MOSFET designated E−FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non−linearly with an increase of peak current in avalanche and peak junction temperature. Although many E−FETs can withstand the stress of drain−to−source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. http://onsemi.com 5 NTB52N10 I D, DRAIN CURRENT (AMPS) 1000 VGS = 20 V SINGLE PULSE TC = 25°C 100 10 ms 100 ms 10 1 ms 10 ms dc 1 r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) 0.1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10 100 1000 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) EAS , SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) SAFE OPERATING AREA 800 700 ID = 40 A 600 500 400 300 200 100 0 Figure 11. Maximum Rated Forward Biased Safe Operating Area 25 50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (°C) 150 Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature 1 D = 0.5 0.2 0.1 0.1 P(pk) 0.05 0.02 t1 0.01 t2 DUTY CYCLE, D = t1/t2 SINGLE PULSE 0.01 0.00001 0.0001 0.001 0.01 t, TIME (ms) RqJC(t) = r(t) RqJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TC = P(pk) RqJC(t) 0.1 Figure 13. Thermal Response di/dt IS trr ta tb TIME 0.25 IS tp IS Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 6 1 10 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS D2PAK 3 CASE 418B−04 ISSUE L DATE 17 FEB 2015 SCALE 1:1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. 418B−01 THRU 418B−03 OBSOLETE, NEW STANDARD 418B−04. C E −B− V W 4 1 2 A S 3 −T− SEATING PLANE K W J G D DIM A B C D E F G H J K L M N P R S V H 3 PL 0.13 (0.005) M T B M VARIABLE CONFIGURATION ZONE N R P L M STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR L M F F F VIEW W−W 1 VIEW W−W 2 VIEW W−W 3 STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN MILLIMETERS MIN MAX 8.64 9.65 9.65 10.29 4.06 4.83 0.51 0.89 1.14 1.40 7.87 8.89 2.54 BSC 2.03 2.79 0.46 0.64 2.29 2.79 1.32 1.83 7.11 8.13 5.00 REF 2.00 REF 0.99 REF 14.60 15.88 1.14 1.40 U L M INCHES MIN MAX 0.340 0.380 0.380 0.405 0.160 0.190 0.020 0.035 0.045 0.055 0.310 0.350 0.100 BSC 0.080 0.110 0.018 0.025 0.090 0.110 0.052 0.072 0.280 0.320 0.197 REF 0.079 REF 0.039 REF 0.575 0.625 0.045 0.055 STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 4: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 5: STYLE 6: PIN 1. CATHODE PIN 1. NO CONNECT 2. ANODE 2. CATHODE 3. CATHODE 3. ANODE 4. ANODE 4. CATHODE MARKING INFORMATION AND FOOTPRINT ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42761B D2PAK 3 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com D2PAK 3 CASE 418B−04 ISSUE L DATE 17 FEB 2015 GENERIC MARKING DIAGRAM* xx xxxxxxxxx AWLYWWG xxxxxxxxG AYWW AYWW xxxxxxxxG AKA IC Standard Rectifier xx A WL Y WW G AKA = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package = Polarity Indicator *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. SOLDERING FOOTPRINT* 10.49 8.38 16.155 2X 3.504 2X 1.016 5.080 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98ASB42761B D2PAK 3 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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