NTB5405N, NVB5405N
MOSFET – Power, Single,
N-Channel, D2PAK
40 V, 116 A
Features
•
•
•
•
•
http://onsemi.com
Low RDS(on)
High Current Capability
Low Gate Charge
AEC−Q101 Qualified and PPAP Capable − NVB5405N
These Devices are Pb−Free and are RoHS Compliant
V(BR)DSS
RDS(ON) TYP
ID MAX
(Note 1)
40 V
4.9 mΩ @ 10 V
116 A
Applications
N−Channel
• Electronic Brake Systems
• Electronic Power Steering
• Bridge Circuits
D
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Parameter
G
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
40
V
Gate−to−Source Voltage
VGS
±20
V
ID
116
A
Continuous Drain
Current − RJC
Steady
State
Power Dissipation −
RJC
Steady
State
Continuous Drain
Current − RJA (Note 1)
Steady
State
Power Dissipation −
RJA (Note 1)
Steady
State
Pulsed Drain Current
TC = 25°C
TC = 100°C
150
W
TA = 25°C
ID
16.5
A
TA = 100°C
ID
11.6
TA = 25°C
PD
3.0
W
IDM
280
A
TJ,
TSTG
−55 to
175
°C
IS
75
A
EAS
800
mJ
TL
260
°C
tp = 10 s
Operating Junction and Storage Temperature
Source Current (Body Diode) Pulsed
Single Pulse Drain−to Source Avalanche
Energy − (VDD = 50 V, VGS = 10 V, IPK = 40 A,
L = 1 mH, RG = 25 )
Lead Temperature for Soldering Purposes
(1/8” from case for 10 s)
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Max
Unit
Junction−to−Case (Drain)
RθJC
1.0
°C/W
Junction−to−Ambient (Note 1)
RθJA
50
°C/W
1. Surface mounted on FR4 board using 1 sq in pad size,
(Cu Area 1.127 sq in [2 oz] including traces).
© Semiconductor Components Industries, LLC, 2011
May, 2019 − Rev. 5
MARKING
DIAGRAM
82
PD
TC = 25°C
S
1
1
2
3
NTB5405NG
AYWW
D2PAK
CASE 418B
STYLE 2
1
NTB5405N
G
A
Y
WW
= Specific Device Code
= Pb−Free Device
= Assembly Location
= Year
= Work Week
ORDERING INFORMATION
Package
Shipping†
NTB5405NG
Device
D2PAK
(Pb−Free)
50 Units / Rail
NTB5405NT4G
D2PAK
(Pb−Free)
800 / Tape & Reel
NVB5405NT4G
D2PAK
(Pb−Free)
800 / Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
NTB5405N/D
NTB5405N, NVB5405N
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise stated)
Parameter
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 A
40
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJ
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate−to−Source Leakage Current
V
39
IDSS
VGS = 0 V,
VDS = 40 V
mV/°C
TJ = 25°C
1.0
TJ = 100°C
10
IGSS
VDS = 0 V, VGS = ±30 V
VGS(TH)
VGS = VDS, ID = 250 A
±100
A
nA
ON CHARACTERISTICS (Note 2)
Gate Threshold Voltage
Gate Threshold Temperature
Coefficient
Drain−to−Source On Resistance
Forward Transconductance
VGS(TH)/TJ
1.5
3.5
−7.0
RDS(on)
gFS
V
mV/°C
VGS = 10 V, ID = 40 A
4.9
5.8
VGS = 5.0 V, ID = 15 A
7.0
8.0
VGS = 10 V, ID = 15 A
32
m
S
CHARGES AND CAPACITANCES
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
2700
4000
VGS = 0 V, f = 1.0 MHz,
VDS = 32 V
700
1400
300
600
VGS = 10 V, VDS = 32 V,
ID = 40 A
Total Gate Charge
QG(TOT)
88
Threshold Gate Charge
QG(TH)
3.25
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
pF
nC
9.5
37
SWITCHING CHARACTERISTICS, VGS = 10 V (Note 3)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(ON)
tr
td(OFF)
ns
8.5
VGS = 10 V, VDD = 32 V,
ID = 40 A, RG = 2.5
tf
52
55
70
SWITCHING CHARACTERISTICS, VGS = 5 V (Note 3)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(ON)
tr
td(OFF)
ns
19
VGS = 5 V, VDD = 20 V,
ID = 20 A, RG = 2.5
tf
153
32
42
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
VSD
TJ = 25°C
0.82
TJ = 100°C
TBD
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V,
IS = 20 A
66
VGS = 0 V, dISD/dt = 100 A/s,
IS = 20 A
QRR
http://onsemi.com
2
V
ns
35
31
113
2. Pulse Test: pulse width ≤ 300 s, duty cycle ≤ 2%.
3. Switching characteristics are independent of operating junction temperatures.
1.1
nC
NTB5405N, NVB5405N
TYPICAL PERFORMANCE CURVES
175
125
TJ = 25°C
VGS = 6 V to 10 V
VDS ≥ 10 V
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
200
5.5 V
150
5V
125
4.5 V
100
75
4V
50
25
3.5 V
0
0
1
3
2
5
4
6
7
9
8
100
75
50
TJ = 125°C
25
TJ = 25°C
TJ = −55°C
0
10
0
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
1
2
6
7
3
5
4
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
0.01
ID = 40 A
TJ = 25°C
0.009
0.008
0.007
0.006
0.005
0.004
0.003
3
5
4
7
6
9
8
10
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
RDS(on), DRAIN−TO−SOURCE RESISTANCE ()
RDS(on), DRAIN−TO−SOURCE RESISTANCE ()
Figure 1. On−Region Characteristics
0.01
0.008
0.007
VGS = 5 V
0.006
0.005
VGS = 10 V
0.004
0.003
0.002
15
25
35
45
100000
1.2
1
75
85
95
105 115
VGS = 0 V
10000
1.4
65
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
ID = 40 A
VGS = 10 V
1.6
55
ID, DRAIN CURRENT (AMPS)
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
1.8
TJ = 25°C
0.009
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
2
8
TJ = 175°C
1000
TJ = 100°C
100
0.8
0.6
−50
−25
0
25
50
75
100
150
125
175
10
10
15
20
25
30
35
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
http://onsemi.com
3
40
NTB5405N, NVB5405N
TYPICAL PERFORMANCE CURVES
TJ = 25°C
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
C, CAPACITANCE (pF)
7000
VDS = 0 V VGS = 0 V
Ciss
6000
5000
Crss
4000
Ciss
3000
2000
Coss
1000
Crss
0
10
VGS
0
10
VDS
30
20
36
12
QT
10
40
18
QGS
QGD
4
12
2
0
ID = 40 A
TJ = 25°C
0
10
1000
40
td(off)
tr
td(on)
10
1
IS, SOURCE CURRENT (AMPS)
t, TIME (ns)
tf
1
10
RG, GATE RESISTANCE (OHMS)
25
20
15
10
5
1
800
100 s
10 s
10 ms
100
dc
10
VGS = 20 V
Single Pulse
TC = 25°C
RDS(on) Limit
Thermal Limit
Package Limit
0.1
1
ID = 40 A
700
AVALANCHE ENERGY (mJ)
1 ms
ID, DRAIN CURRENT (A)
0.5
0.7
0.6
0.8
0.9
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage vs. Current
1000
0.1
0
90
30
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
1
80
VGS = 0 V
TJ = 25°C
35
0
0.4
100
50
70
20
30
40
60
QG, TOTAL GATE CHARGE (nC)
6
Figure 8. Gate−To−Source and
Drain−To−Source Voltage vs. Total Charge
Figure 7. Capacitance Variation
100
24
6
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VDS = 32 V
ID = 40 A
VGS = 10 V
30
VGS
VDS
8
V DS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)
8000
10
600
500
400
300
200
100
0
25
100
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
50
75
100
125
150
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
http://onsemi.com
4
175
NTB5405N, NVB5405N
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
(NORMALIZED)
TYPICAL PERFORMANCE CURVES
1.0
D = 0.5
0.2
0.1
0.1
P(pk)
0.05
0.02
t1
0.01
t2
DUTY CYCLE, D = t1/t2
SINGLE PULSE
0.01
0.00001
0.0001
0.001
0.01
t, TIME (s)
Figure 13. Thermal Response
http://onsemi.com
5
0.1
RJC(t) = r(t) RJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) RJC(t)
1.0
10
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
D2PAK 3
CASE 418B−04
ISSUE L
DATE 17 FEB 2015
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 418B−01 THRU 418B−03 OBSOLETE,
NEW STANDARD 418B−04.
C
E
−B−
V
W
4
1
2
A
S
3
−T−
SEATING
PLANE
K
W
J
G
D
DIM
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
S
V
H
3 PL
0.13 (0.005)
M
T B
M
VARIABLE
CONFIGURATION
ZONE
N
R
P
L
M
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
L
M
F
F
F
VIEW W−W
1
VIEW W−W
2
VIEW W−W
3
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
MILLIMETERS
MIN
MAX
8.64
9.65
9.65 10.29
4.06
4.83
0.51
0.89
1.14
1.40
7.87
8.89
2.54 BSC
2.03
2.79
0.46
0.64
2.29
2.79
1.32
1.83
7.11
8.13
5.00 REF
2.00 REF
0.99 REF
14.60 15.88
1.14
1.40
U
L
M
INCHES
MIN
MAX
0.340 0.380
0.380 0.405
0.160 0.190
0.020 0.035
0.045 0.055
0.310 0.350
0.100 BSC
0.080
0.110
0.018 0.025
0.090
0.110
0.052 0.072
0.280 0.320
0.197 REF
0.079 REF
0.039 REF
0.575 0.625
0.045 0.055
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 4:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 5:
STYLE 6:
PIN 1. CATHODE
PIN 1. NO CONNECT
2. ANODE
2. CATHODE
3. CATHODE
3. ANODE
4. ANODE
4. CATHODE
MARKING INFORMATION AND FOOTPRINT ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42761B
D2PAK 3
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
D2PAK 3
CASE 418B−04
ISSUE L
DATE 17 FEB 2015
GENERIC
MARKING DIAGRAM*
xx
xxxxxxxxx
AWLYWWG
xxxxxxxxG
AYWW
AYWW
xxxxxxxxG
AKA
IC
Standard
Rectifier
xx
A
WL
Y
WW
G
AKA
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
= Polarity Indicator
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
SOLDERING FOOTPRINT*
10.49
8.38
16.155
2X
3.504
2X
1.016
5.080
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42761B
D2PAK 3
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
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