NTB60N06, NVB60N06
MOSFET – Power,
N-Channel, D2PAK
60 V, 60 A
Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
circuits.
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60 VOLTS, 60 AMPERES
RDS(on) = 14 mW
Features
• AEC−Q101 Qualified and PPAP Capable − NVB60N06
• These Devices are Pb−Free and are RoHS Compliant
N−Channel
D
Typical Applications
•
•
•
•
Power Supplies
Converters
Power Motor Controls
Bridge Circuits
G
S
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
60
Vdc
Drain−to−Gate Voltage (RGS = 10 MW)
VDGR
60
Vdc
Rating
Gate−to−Source Voltage
− Continuous
− Non−Repetitive (tpv10 ms)
"20
"30
ID
ID
60
42.3
180
Adc
PD
150
1.0
2.4
W
W/°C
W
Operating and Storage Temperature Range
TJ, Tstg
−55 to
+175
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 75 Vdc, VGS = 10 Vdc, L = 0.3 mH
IL(pk) = 55 A, VDS = 60 Vdc)
EAS
454
mJ
Total Power Dissipation @ TA = 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C (Note 1)
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient (Note 1)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
4
Drain
4
Vdc
VGS
VGS
Drain Current
− Continuous @ TA = 25°C
− Continuous @ TA = 100°C
− Single Pulse (tpv10 ms)
MARKING
DIAGRAM
IDM
2
D2PAK
CASE 418B
STYLE 2
NTx60N06
AYWW
3
2
1
3
Drain
Gate
Source
Apk
NTx60N06
x
A
Y
WW
= Device Code
= P or B
= Assembly Location
= Year
= Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
RqJC
RqJA
1.0
62.5
TL
260
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. When surface mounted to an FR4 board using minimum recommended pad
size, (Cu Area 0.412 in2).
© Semiconductor Components Industries, LLC, 2011
May, 2019 − Rev. 0
1
Publication Order Number:
NTP60N06/D
NTB60N06, NVB60N06
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
60
−
72.3
69.8
−
−
−
−
−
−
1.0
10
−
−
±100
2.0
−
2.85
8.0
4.0
−
−
11.5
14
−
−
0.715
1.43
1.01
−
gFS
−
35
−
mhos
Ciss
−
2300
3220
pF
Coss
−
660
925
Crss
−
144
300
td(on)
−
25.5
50
OFF CHARACTERISTICS
V(BR)DSS
Drain−to−Source Breakdown Voltage (Note 2)
(VGS = 0 Vdc, ID = 250 mAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C)
IDSS
Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc)
IGSS
Vdc
mV/°C
mAdc
nAdc
ON CHARACTERISTICS (Note 2)
Gate Threshold Voltage (Note 2)
(VDS = VGS, ID = 250 mAdc)
Threshold Temperature Coefficient (Negative)
VGS(th)
Static Drain−to−Source On−Resistance (Note 2)
(VGS = 10 Vdc, ID = 30 Adc)
RDS(on)
Static Drain−to−Source On−Voltage (Note 2)
(VGS = 10 Vdc, ID = 60 Adc)
(VGS = 10 Vdc, ID = 30 Adc, TJ = 150°C)
VDS(on)
Forward Transconductance (Note 2) (VDS = 8.0 Vdc, ID = 12 Adc)
Vdc
mV/°C
mW
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Transfer Capacitance
SWITCHING CHARACTERISTICS (Note 3)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
(VDD = 30 Vdc, ID = 60 Adc,
VGS = 10 Vdc, RG = 9.1 W) (Note 2)
Fall Time
Gate Charge
(VDS = 48 Vdc, ID = 60 Adc,
VGS = 10 Vdc) (Note 2)
ns
tr
−
180.7
360
td(off)
−
94.5
200
tf
−
142.5
300
QT
−
62
81
Q1
−
10.8
−
Q2
−
29.4
−
VSD
−
−
0.99
0.87
1.05
−
Vdc
trr
−
64.9
−
ns
ta
−
44.1
−
tb
−
20.8
−
QRR
−
0.146
−
nC
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(IS = 60 Adc, VGS = 0 Vdc) (Note 2)
(IS = 45 Adc, VGS = 0 Vdc, TJ = 150°C)
Reverse Recovery Time
(IS = 60 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/ms) (Note 2)
Reverse Recovery Stored Charge
2. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
3. Switching characteristics are independent of operating junction temperatures.
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2
mC
NTB60N06, NVB60N06
120
VGS = 10 V
VDS ≥ 10 V
7V
9V
100
6V
8V
80
60
5.5 V
40
5V
20
0
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
120
4.5 V
4
1
2
3
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0
100
80
60
40
TJ = 25°C
20
TJ = 100°C
TJ = −55°C
0
5
3
0.026
VDS = 10 V
0.022
VGS = 15 V
0.022
TJ = 100°C
0.018
TJ = 100°C
0.018
0.014
0.014
TJ = 25°C
0.01
0.006
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
0.026
8
Figure 2. Transfer Characteristics
TJ = −55°C
0
20
40
60
80
100
ID, DRAIN CURRENT (AMPS)
120
TJ = 25°C
0.01
TJ = −55°C
0.006
0
Figure 3. On−Resistance versus Gate−to−Source
Voltage
2.2
2
20
40
60
80
100
ID, DRAIN CURRENT (AMPS)
120
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
10,000
ID = 30 A
VGS = 10 V
VGS = 0 V
TJ = 150°C
1.8
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
Figure 1. On−Region Characteristics
4
5
6
7
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
1.6
1.4
1.2
1
1000
TJ = 125°C
100
TJ = 100°C
0.8
0.6
−50
−25
0
25
50
75
100
125
150
10
175
0
10
20
30
40
50
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
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3
60
NTB60N06, NVB60N06
POWER MOSFET SWITCHING
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
6400
C, CAPACITANCE (pF)
5600
4800
VDS = 0 V
VGS = 0 V
TJ = 25°C
Ciss
4000
3200
2400
Crss
Ciss
1600
Coss
800
0
10
Crss
5
0
VGS
5
10
15
20
25
VDS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
1000
12
VDS = 30 V
ID = 60 A
VGS = 10 V
QT
10
VGS
8
Q1
Q2
6
4
2
0
0
tr
t, TIME (ns)
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
NTB60N06, NVB60N06
100
td(off)
ID = 60 A
TJ = 25°C
10
20
30
40
50
QG, TOTAL GATE CHARGE (nC)
60
tf
td(on)
10
70
1
10
RG, GATE RESISTANCE (W)
Figure 8. Gate−to−Source and Drain−to−Source
Voltage versus Total Charge
100
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
IS, SOURCE CURRENT (AMPS)
60
VGS = 0 V
TJ = 25°C
50
40
TJ = 150°C
30
20
TJ = 25°C
10
0
0.4
0.48
0.56
0.64
0.72
0.8
0.88
0.96
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous ID can safely be assumed to
equal the values indicated.
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed
in
AN569,
“Transient
Thermal
Resistance−General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 ms. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) − TC)/(RqJC).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
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5
NTB60N06, NVB60N06
ID, DRAIN CURRENT (AMPS)
1000
VGS = 20 V
SINGLE PULSE
TC = 25°C
10 ms
100
100 ms
10
1
1 ms
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
10 ms
dc
1
10
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
100
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
SAFE OPERATING AREA
500
ID = 55 A
400
300
200
100
0
25
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
150
50
75
100
125
TJ, STARTING JUNCTION TEMPERATURE (°C)
175
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1.0
D = 0.5
0.2
0.1
0.1
P(pk)
0.05
0.02
t1
0.01
t2
DUTY CYCLE, D = t1/t2
SINGLE PULSE
0.01
0.00001
0.0001
0.001
0.01
RqJC(t) = r(t) RqJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) RqJC(t)
0.1
t, TIME (s)
Figure 13. Thermal Response
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 14. Diode Reverse Recovery Waveform
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6
1.0
10
NTB60N06, NVB60N06
ORDERING INFORMATION
Package
Shipping†
NTB60N06T4G
D2PAK
(Pb−Free)
800 / Tape & Reel
NVB60N06T4G
D2PAK
(Pb−Free)
800 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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7
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
D2PAK 3
CASE 418B−04
ISSUE L
DATE 17 FEB 2015
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 418B−01 THRU 418B−03 OBSOLETE,
NEW STANDARD 418B−04.
C
E
−B−
V
W
4
1
2
A
S
3
−T−
SEATING
PLANE
K
W
J
G
D
DIM
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
S
V
H
3 PL
0.13 (0.005)
M
T B
M
VARIABLE
CONFIGURATION
ZONE
N
R
P
L
M
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
L
M
F
F
F
VIEW W−W
1
VIEW W−W
2
VIEW W−W
3
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
MILLIMETERS
MIN
MAX
8.64
9.65
9.65 10.29
4.06
4.83
0.51
0.89
1.14
1.40
7.87
8.89
2.54 BSC
2.03
2.79
0.46
0.64
2.29
2.79
1.32
1.83
7.11
8.13
5.00 REF
2.00 REF
0.99 REF
14.60 15.88
1.14
1.40
U
L
M
INCHES
MIN
MAX
0.340 0.380
0.380 0.405
0.160 0.190
0.020 0.035
0.045 0.055
0.310 0.350
0.100 BSC
0.080
0.110
0.018 0.025
0.090
0.110
0.052 0.072
0.280 0.320
0.197 REF
0.079 REF
0.039 REF
0.575 0.625
0.045 0.055
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 4:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 5:
STYLE 6:
PIN 1. CATHODE
PIN 1. NO CONNECT
2. ANODE
2. CATHODE
3. CATHODE
3. ANODE
4. ANODE
4. CATHODE
MARKING INFORMATION AND FOOTPRINT ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42761B
D2PAK 3
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
D2PAK 3
CASE 418B−04
ISSUE L
DATE 17 FEB 2015
GENERIC
MARKING DIAGRAM*
xx
xxxxxxxxx
AWLYWWG
xxxxxxxxG
AYWW
AYWW
xxxxxxxxG
AKA
IC
Standard
Rectifier
xx
A
WL
Y
WW
G
AKA
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
= Polarity Indicator
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
SOLDERING FOOTPRINT*
10.49
8.38
16.155
2X
3.504
2X
1.016
5.080
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42761B
D2PAK 3
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
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