NTB6410ANT4G

NTB6410AN, NTP6410AN N-Channel Power MOSFET 100 V, 76 A, 13 mW Features • • • • Low RDS(on) High Current Capability 100% Avalanche Tested These are Pb−Free Devices V(BR)DSS 100 V Unit V V A http://onsemi.com ID MAX (Note 1) 76 A RDS(ON) MAX 13 mW @ 10 V MAXIMUM RATINGS (TJ = 25°C Unless otherwise specified) Parameter Drain−to−Source Voltage Gate−to−Source Voltage − Continuous Continuous Drain Current RqJC Power Dissipation RqJC Pulsed Drain Current Steady State Steady State TC = 25°C TC = 100°C TC = 25°C PD IDM TJ, Tstg IS EAS Symbol VDSS VGS ID Value 100 $20 76 54 188 305 −55 to +175 76 500 W A °C A mJ N−Channel D G S 4 4 1 2 3 tp = 10 ms Operating Junction and Storage Temperature Range Source Current (Body Diode) Single Pulse Drain−to−Source Avalanche Energy (VDD = 50 Vdc, VGS = 10 Vdc, IL(pk) = 57.7 A, L = 0.3 mH, RG = 25 W) Lead Temperature for Soldering Purposes, 1/8″ from Case for 10 Seconds TL 260 °C 1 2 THERMAL RESISTANCE RATINGS Parameter Junction−to−Case (Drain) Steady State Junction−to−Ambient (Note 1) Symbol RqJC RqJA Max 0.8 32 Unit °C/W TO−220AB CASE 221A STYLE 5 3 D2PAK CASE 418B STYLE 2 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface mounted on FR4 board using 1 sq in pad size, (Cu Area 1.127 sq in [2 oz] including traces). 4 Drain MARKING DIAGRAM & PIN ASSIGNMENT 4 Drain NTP 6410ANG AYWW 1 Gate 2 Drain 3 Source 1 Gate NTB 6410ANG AYWW 2 Drain 3 Source 6410AN = Specific Device Code G = Pb−Free Device A = Assembly Location Y = Year WW = Work Week ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. © Semiconductor Components Industries, LLC, 2009 December, 2009 − Rev. 0 1 Publication Order Number: NTB6410AN/D NTB6410AN, NTP6410AN ELECTRICAL CHARACTERISTICS (TJ = 25°C Unless otherwise specified) Characteristics OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage Drain−to−Source Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current V(BR)DSS V(BR)DSS/TJ IDSS IGSS VGS(th) VGS(th)/TJ RDS(on) gFS Ciss Coss Crss QG(TOT) QG(TH) QGS QGD VGP RG td(on) tr td(off) tf VSD trr ta tb QRR VGS = 0 V, IS = 76 A, dISD/dt = 100 A/ms TJ = 25°C TJ = 125°C VGS = 10 V, VDD = 80 V, ID = 76 A, RG = 6.2 W VGS = 10 V, VDS = 80 V, ID = 76 A VDS = 25 V, VGS = 0 V, f = 1 MHz VGS = 10 V, ID = 76 A VGS = 10 V, ID = 20 A Forward Transconductance CHARGES, CAPACITANCES & GATE RESISTANCE Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Threshold Gate Charge Gate−to−Source Charge Gate−to−Drain Charge Plateau Voltage Gate Resistance 4500 650 250 120 5.2 20 57 5.1 2.4 V W ns nC pF VDS = 5 V, ID = 20 A VGS = 0 V, VDS = 100 V TJ = 25°C TJ = 150°C VGS = 0 V, ID = 250 mA 100 94 1.0 100 $100 nA V mV/°C mA Symbol Test Condition Min Typ Max Unit Gate−to−Source Leakage Current ON CHARACTERISTICS (Note 2) Gate Threshold Voltage Negative Threshold Temperature Coefficient Drain−to−Source On−Resistance VDS = 0 V, VGS = $20 V VGS = VDS, ID = 250 mA 2.0 9.0 11 10 40 4.0 V mV/°C 13 12 mW S SWITCHING CHARACTERISTICS, VGS = 10 V (Note 3) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage IS = 76 A 1.0 0.9 93 69 24 300 nC ns 1.3 V 17 170 120 190 Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Charge 2. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 3. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 NTB6410AN, NTP6410AN 160 140 ID, DRAIN CURRENT (A) 120 100 80 60 40 20 0 VGS = 4.4 V 0 1 2 3 4 5 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 5.4 V 5.0 V 6.0 V TJ = 25°C 10 V 7.0 V ID, DRAIN CURRENT (A) 6.5 V 160 140 120 100 80 60 40 20 0 2 3 4 5 TJ = 125°C TJ = 25°C TJ = −55°C VDS w 10 V 6 7 8 VGS, GATE−TO−SOURCE VOLTAGE (V) Figure 1. On−Region Characteristics RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) ID = 76 A TJ = 25°C 0.030 0.025 0.020 0.015 0.010 0.005 0.000 Figure 2. Transfer Characteristics VGS = 10 V 0.035 TJ = 175°C TJ = 125°C 0.025 TJ = 25°C TJ = −55°C 0.015 0.005 5 6 7 8 9 10 10 20 30 40 50 60 70 80 VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A) Figure 3. On−Region versus Gate Voltage Figure 4. On−Region versus Drain Current and Gate Voltage 100000 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 2.5 VGS = 10 V ID = 76 A VGS = 0 V TJ = 150°C 2 IDSS, LEAKAGE (nA) 10000 1.5 TJ = 125°C 1000 1 0.5 −50 −25 0 25 50 75 100 125 150 175 100 10 20 30 40 50 60 70 80 90 10 Figure 5. On−Resistance Variation with Temperature TJ, JUNCTION TEMPERTURE (°C) Figure 6. Drian−to−Source Leakage Current versus Voltage VDS, DRAIN−TO−SOURCE VOLTAGE (V) http://onsemi.com 3 NTB6410AN, NTP6410AN QT VGS Qgd VDS, DRAIN−TO−SOURCE VOLTAGE (V) 1.1 VGS, GATE−TO−SOURCE VOLTAGE (V) 8000 7000 C, CAPACITANCE (pF) 6000 5000 4000 3000 2000 1000 0 Crss 0 10 20 30 40 50 60 70 80 90 VDS, DRAIN−TO−SOURCE VOLTAGE (V) Coss Ciss TJ = 25°C VGS = 0 V 10 8 VDS 6 4 2 0 Qgs 100 80 60 40 VDS = 80 V ID = 76 A TJ = 25°C 0 20 40 60 80 100 20 0 120 100 Qg, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation 1000 VDS = 80 V ID = 76 A VGS = 10 V Figure 8. Gate−to−Source and Drain−to−Source Voltage versus Total Charge 80 IS, SOURCE CURRENT (A) 70 60 50 40 30 20 10 TJ = 25°C VGS = 0 V 100 t, TIME (ns) tf tr td(on) td(off) 10 1 1 10 RG, GATE RESISTANCE (W) 100 0 0.4 0.5 0.6 0.7 0.8 0.9 1.0 VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation versus Gate Resistance 1000 AVALANCHE ENERGY (mJ) 500 Figure 10. Diode Forward Voltage versus Current ID = 57.7 A ID, DRAIN CURRENT (A) 100 10 ms 100 ms 400 300 200 100 0 25 10 1 ms 10 ms dc 1 0.1 1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT VGS = 10 V SINGLE PULSE TC = 25°C 10 100 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 1000 50 75 100 125 150 175 TJ, STARTING JUNCTION TEMPERATURE Figure 11. Maximum Rated Forward Biased Safe Opeating Area Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 4 NTB6410AN, NTP6410AN 1 D = 0.5 0.2 R(t) (°C/W) 0.1 0.1 0.05 0.02 0.01 0.01 SINGLE PULSE 0.001 0.000001 0.00001 0.0001 0.001 0.01 0.1 t, PULSE TIME (s) 1.0 10 100 1000 Figure 13. Thermal Response ORDERING INFORMATION Device NTB6410ANG NTB6410ANT4G NTP6410ANG Package D2PAK (Pb−Free) D2PAK (Pb−Free) TO−220 (Pb−Free) Shipping† 50 Units / Rail 800 / Tape & Reel 50 Units / Rail †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 5 NTB6410AN, NTP6410AN PACKAGE DIMENSIONS D2PAK 3 CASE 418B−04 ISSUE K C E −B− 4 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. 418B−01 THRU 418B−03 OBSOLETE, NEW STANDARD 418B−04. DIM A B C D E F G H J K L M N P R S V INCHES MIN MAX 0.340 0.380 0.380 0.405 0.160 0.190 0.020 0.035 0.045 0.055 0.310 0.350 0.100 BSC 0.080 0.110 0.018 0.025 0.090 0.110 0.052 0.072 0.280 0.320 0.197 REF 0.079 REF 0.039 REF 0.575 0.625 0.045 0.055 MILLIMETERS MIN MAX 8.64 9.65 9.65 10.29 4.06 4.83 0.51 0.89 1.14 1.40 7.87 8.89 2.54 BSC 2.03 2.79 0.46 0.64 2.29 2.79 1.32 1.83 7.11 8.13 5.00 REF 2.00 REF 0.99 REF 14.60 15.88 1.14 1.40 V W 1 2 3 S A −T− SEATING PLANE K G D 3 PL 0.13 (0.005) H M J W TB M VARIABLE CONFIGURATION ZONE L M R N U L P L M STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN M F VIEW W−W 1 F VIEW W−W 2 F VIEW W−W 3 SOLDERING FOOTPRINT* 10.49 8.38 16.155 3.504 1.016 5.080 PITCH DIMENSIONS: MILLIMETERS 2X 2X *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 6 NTB6410AN, NTP6410AN PACKAGE DIMENSIONS TO−220 CASE 221A−09 ISSUE AF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. DIM A B C D F G H J K L N Q R S T U V Z INCHES MIN MAX 0.570 0.620 0.380 0.405 0.160 0.190 0.025 0.035 0.142 0.161 0.095 0.105 0.110 0.155 0.014 0.025 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.045 0.055 0.235 0.255 0.000 0.050 0.045 ----0.080 GATE DRAIN SOURCE DRAIN MILLIMETERS MIN MAX 14.48 15.75 9.66 10.28 4.07 4.82 0.64 0.88 3.61 4.09 2.42 2.66 2.80 3.93 0.36 0.64 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 1.15 1.39 5.97 6.47 0.00 1.27 1.15 ----2.04 −T− B 4 SEATING PLANE F T C S Q 123 A U K H Z L V G D N R J STYLE 5: PIN 1. 2. 3. 4. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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