NTB65N02RT4

NTB65N02R, NTP65N02R Power MOSFET 65 A, 24 V N−Channel TO−220, D2PAK Features • • • • • http://onsemi.com Planar HD3e Process for Fast Switching Performance Low RDSon to Minimize Conduction Loss Low Ciss to Minimize Driver Loss Low Gate Charge Pb−Free Packages are Available* V(BR)DSS RDS(on) TYP ID MAX 24 V 8.4 m @ 10 V 65 A D MAXIMUM RATINGS (TJ = 25°C Unless otherwise specified) Parameter G Symbol Value Unit Drain−to−Source Voltage VDSS 25 Vdc Gate−to−Source Voltage − Continuous VGS ±20 Vdc Thermal Resistance − Junction−to−Case Total Power Dissipation @ TC = 25°C Drain Current − Continuous @ TC = 25°C, Chip Continuous @ TC =25°C, Limited by Package Single Pulse (tp = 10 s) RJC PD 2.0 62.5 °C/W W ID ID IDM 65 58 160 A A A Thermal Resistance − Junction−to−Ambient (Note 1) Total Power Dissipation @ TA = 25°C Drain Current − Continuous @ TA = 25°C RJA PD ID 67 1.86 10 °C/W W A Thermal Resistance − Junction−to−Ambient (Note 2) Total Power Dissipation @ TA = 25°C Drain Current − Continuous @ TA = 25°C RJA PD ID 120 1.04 7.6 °C/W W A TJ and Tstg −55 to 150 °C Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 50 Vdc, VGS = 10 Vdc, IL = 11 Apk, L = 1 mH, RG = 25 ) EAS 60 mJ Maximum Lead Temperature for Soldering Purposes, 1/8″ from Case for 10 Seconds TL Operating and Storage Temperature Range 4 1 2 TO−220AB CASE 221A STYLE 5 P65N02RG AYWW 3 4 2 1 3 D2PAK CASE 418AA STYLE 2 65N02RG AYWW 65N02R = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package °C 260 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. May, 2005 − Rev. 6 MARKING DIAGRAMS 1 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. When surface mounted to an FR4 board using 1 in. pad size, (Cu Area 1.127 in2). 2. When surface mounted to an FR4 board using minimum recommended pad size, (Cu Area 0.412 in2).  Semiconductor Components Industries, LLC, 2005 S PIN ASSIGNMENT PIN FUNCTION 1 Gate 2 Drain 3 Source 4 Drain ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. Publication Order Number: NTB65N02R/D NTB65N02R, NTP65N02R ELECTRICAL CHARACTERISTICS (TJ = 25°C Unless otherwise specified) Characteristics Symbol Drain−to−Source Breakdown Voltage (Note 3) (VGS = 0 Vdc, ID = 250 Adc) Temperature Coefficient (Positive) V(BR)DSS Min Typ Max Unit 24 − 27.5 25.5 − − − − − − 1.5 10 − − ±100 1.0 − 1.5 4.1 2.0 − − − − 11.2 8.4 8.2 12.5 10.5 − − 27 − Ciss − 948 1330 Coss − 456 640 Crss − 160 225 td(on) − 7.0 − tr − 53 − td(off) − 14 − tf − 10 − QT − 9.5 − Q1 − 3.0 − Q2 − 4.4 − VSD − − − 0.88 1.10 0 80 0.80 1.2 − − Vdc trr − 29.1 − ns ta − 13.6 − tb − 15.5 − QRR − 0.02 − OFF CHARACTERISTICS Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 150°C) IDSS Gate−Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/°C Adc nAdc ON CHARACTERISTICS (Note 3) Gate Threshold Voltage (Note 3) (VDS = VGS, ID = 250 Adc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain−to−Source On−Resistance (Note 3) (VGS = 4.5 Vdc, ID = 15 Adc) (VGS = 10 Vdc, ID = 20 Adc) (VGS = 10 Vdc, ID = 30 Adc) RDS(on) Forward Transconductance (Note 3) (VDS = 10 Vdc, ID = 15 Adc) Vdc mV/°C m gFS Mhos DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance ((VDS = 20 Vdc, VGS = 0 V,, f = 1 MHz)) Transfer Capacitance pF SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time (VGS = 10 Vdc, VDD = 10 Vdc, ID = 30 Adc, RG = 3
) Fall Time Gate Charge (VGS = 4.5 Vdc, ID = 30 Adc, VDS = 10 Vdc) (Note 3) ns nC SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (IS = 20 Adc, VGS = 0 Vdc) (Note 3) ((IS = 30 Adc, VGS = 0 Vdc) (IS = 15 Adc, VGS = 0 Vdc, TJ = 125°C) Reverse Recovery Time (IS = 30 Adc d , VGS = 0 Vdc d , dIS/dt = 100 A/s)  ) (Note ( 3)) Reverse Recovery Stored Charge 3. Pulse Test: Pulse Width
300 s, Duty Cycle
2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 C NTB65N02R, NTP65N02R 120 VGS = 10 V 80 VDS  10 V VGS = 4.5 V VGS = 8.0 V VGS = 6.0 V 100 100 ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 120 VGS = 4.0 V VGS = 5.5 V VGS = 5.0 V 60 VGS = 3.5 V 40 VGS = 3.0 V 20 80 60 40 TJ = 25°C 20 VGS = 2.5 V 0 0 2 4 6 8 TJ = 150°C 10 0 1 0.02 TJ = 150°C 0.012 TJ = 25°C TJ = −55°C 0.004 10 20 30 40 50 60 70 80 90 100 110 120 6 5 0.028 VGS = 4.5 V 0.024 0.02 TJ = 150°C TJ = 125°C 0.016 TJ = 25°C 0.012 TJ = −55°C 0.008 0.004 10 20 30 40 50 60 70 80 90 100 110 120 ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) Figure 3. On−Resistance versus Drain Current and Temperature Figure 4. On−Resistance versus Drain Current and Temperature 10000 1.8 ID = 30 A VGS = 4.5 V and 10 V TJ = 150°C IDSS, LEAKAGE (nA) 1.6 RDS(on), DRAIN−TO−SOURCE RESISTANCE () 0.024 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) RDS(on), DRAIN−TO−SOURCE RESISTANCE () VGS = 10 V TJ = 125°C 3 Figure 2. Transfer Characteristics 0.028 0.008 2 VDS, DRAIN−TO−SOURCE VOLTAGE (V) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 1. On−Region Characteristics 0.016 TJ = −55°C 0 1.4 1.2 1.0 1000 TJ = 125°C 100 TJ = 100°C 0.8 0.6 −50 10 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) 0 5 10 15 20 VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current versus Voltage http://onsemi.com 3 25 NTB65N02R, NTP65N02R VDS = 0 V VGS = 0 V VGS, GATE−TO−SOURCE VOLTAGE (V) Ciss TJ = 25°C C, CAPACITANCE (pF) 1600 1200 Ciss Crss 800 Coss 400 Crss 0 10 5 VGS 0 5 VDS 10 15 20 5 QT QGS QGD 8 VGS 3 6 2 4 1 0 2 ID = 30 A TJ = 25°C 2 0 4 8 6 10 12 Figure 8. Gate−to−Source and Drain−to−Source Voltage versus Total Charge Figure 7. Capacitance Variation 1000 60 IS, SOURCE CURRENT (A) VDS = 10 V ID = 30 A VGS = 10 V 100 tr td(off) tf 10 td(on) 50 40 30 20 TJ = 150°C 10 TJ = 25°C 0 1 1 10 100 0 RG, GATE RESISTANCE () 0.2 0.4 ID, DRAIN CURRENT (A) 0.8 1 Figure 10. Diode Forward Voltage versus Current 1000 VGS = 20 V SINGLE PULSE TC = 25°C 100 10 s 100 s 10 1 ms 10 ms dc RDS(ON) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 0.6 VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation versus Gate Resistance 1 1 10 100 VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 11. Maximum Rated Forward Biased Safe Operating Area http://onsemi.com 4 0 Qg, TOTAL GATE CHARGE (nC) GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V) t, TIME (ns) 10 VDS 4 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 2000 r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) NTB65N02R, NTP65N02R 1 D = 0.5 0.2 0.1 0.05 0.01 SINGLE PULSE 0.1 0.0001 0.001 0.01 0.1 1 10 t, TIME (s) Figure 12. Thermal Response ORDERING INFORMATION Package Shipping† NTB65N02R D2PAK 50 Units / Rail NTB65N02RG D2PAK 50 Units / Rail Device (Pb−Free) NTB65N02RT4 D2PAK 800 / Tape & Reel NTB65N02RT4G D2PAK 800 / Tape & Reel (Pb−Free) NTP65N02R TO−220AB 50 Units / Rail NTP65N02RG TO−220AB (Pb−Free) 50 Units / Rail †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 5 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TO−220 CASE 221A ISSUE AK DATE 13 JAN 2022 SCALE 1:1 STYLE 1: PIN 1. 2. 3. 4. BASE COLLECTOR EMITTER COLLECTOR STYLE 2: PIN 1. 2. 3. 4. BASE EMITTER COLLECTOR EMITTER STYLE 3: PIN 1. 2. 3. 4. CATHODE ANODE GATE ANODE STYLE 4: PIN 1. 2. 3. 4. MAIN TERMINAL 1 MAIN TERMINAL 2 GATE MAIN TERMINAL 2 STYLE 5: PIN 1. 2. 3. 4. GATE DRAIN SOURCE DRAIN STYLE 6: PIN 1. 2. 3. 4. ANODE CATHODE ANODE CATHODE STYLE 7: PIN 1. 2. 3. 4. CATHODE ANODE CATHODE ANODE STYLE 8: PIN 1. 2. 3. 4. CATHODE ANODE EXTERNAL TRIP/DELAY ANODE STYLE 9: PIN 1. 2. 3. 4. GATE COLLECTOR EMITTER COLLECTOR STYLE 10: PIN 1. 2. 3. 4. GATE SOURCE DRAIN SOURCE STYLE 11: PIN 1. 2. 3. 4. DRAIN SOURCE GATE SOURCE STYLE 12: PIN 1. 2. 3. 4. MAIN TERMINAL 1 MAIN TERMINAL 2 GATE NOT CONNECTED DOCUMENT NUMBER: DESCRIPTION: 98ASB42148B TO−220 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS D2PAK 3 CASE 418B−04 ISSUE L DATE 17 FEB 2015 SCALE 1:1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. 418B−01 THRU 418B−03 OBSOLETE, NEW STANDARD 418B−04. C E −B− V W 4 1 2 A S 3 −T− SEATING PLANE K W J G D DIM A B C D E F G H J K L M N P R S V H 3 PL 0.13 (0.005) M T B M VARIABLE CONFIGURATION ZONE N R P L M STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR L M F F F VIEW W−W 1 VIEW W−W 2 VIEW W−W 3 STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN MILLIMETERS MIN MAX 8.64 9.65 9.65 10.29 4.06 4.83 0.51 0.89 1.14 1.40 7.87 8.89 2.54 BSC 2.03 2.79 0.46 0.64 2.29 2.79 1.32 1.83 7.11 8.13 5.00 REF 2.00 REF 0.99 REF 14.60 15.88 1.14 1.40 U L M INCHES MIN MAX 0.340 0.380 0.380 0.405 0.160 0.190 0.020 0.035 0.045 0.055 0.310 0.350 0.100 BSC 0.080 0.110 0.018 0.025 0.090 0.110 0.052 0.072 0.280 0.320 0.197 REF 0.079 REF 0.039 REF 0.575 0.625 0.045 0.055 STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 4: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 5: STYLE 6: PIN 1. CATHODE PIN 1. NO CONNECT 2. ANODE 2. CATHODE 3. CATHODE 3. ANODE 4. ANODE 4. CATHODE MARKING INFORMATION AND FOOTPRINT ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42761B D2PAK 3 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com D2PAK 3 CASE 418B−04 ISSUE L DATE 17 FEB 2015 GENERIC MARKING DIAGRAM* xx xxxxxxxxx AWLYWWG xxxxxxxxG AYWW AYWW xxxxxxxxG AKA IC Standard Rectifier xx A WL Y WW G AKA = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package = Polarity Indicator *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. SOLDERING FOOTPRINT* 10.49 8.38 16.155 2X 3.504 2X 1.016 5.080 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98ASB42761B D2PAK 3 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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