NTB90N02, NTP90N02
Power MOSFET
90 Amps, 24 Volts
N−Channel D2PAK and TO−220
Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
circuits.
http://onsemi.com
Features
RDS(on) TYP
V(BR)DSS
ID MAX
• Pb−Free Packages are Available
•
•
•
•
5.0 m @ 10 V
24 V
Typical Applications
Power Supplies
Converters
Power Motor Controls
Bridge Circuits
N−Channel
D
G
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Drain−to−Source Voltage
Symbol
Value
Unit
S
VDSS
24
Vdc
MARKING
DIAGRAMS
Gate−to−Source Voltage
− Continuous
VGS
20
Drain Current
− Continuous @ TA = 25°C
− Single Pulse (tp = 10 s)
ID
IDM
90*
200
A
A
PD
85
0.66
W
W/°C
TJ, Tstg
−55 to +150
°C
EAS
733
mJ
Total Power Dissipation @ TA = 25°C
Derate above 25°C
Operating and Storage Temperature
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 28 Vdc, VGS = 10 Vdc,
L = 5.0 mH, IL(pk) = 17 A, RG = 25 )
Thermal Resistance
Junction−to−Case
Junction−to−Ambient (Note 1)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
90 A
7.5 m @ 4.5 V
Vdc
4
Drain
4
TO−220AB
CASE 221A
STYLE 5
1
2
NTx90N02
AYWW
2
Drain
°C/W
RJC
RJA
1.55
70
TL
260
3
Source
1
Gate
3
4
Drain
°C
4
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. When surface mounted to an FR4 board using 1″ pad size, (Cu Area 1.127 in2).
2. When surface mounted to an FR4 board using minimum recommended pad
size, (Cu Area 0.412 in2).
*Chip current capability limited by package.
1
2
D2PAK
CASE 418B
STYLE 2
NTx90N02
AYWW
3
1
Gate
NTx90N02
x
A
Y
WW
2
Drain
3
Source
= Device Code
= P or B
= Assembly Location
= Year
= Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
Semiconductor Components Industries, LLC, 2005
March, 2005 − Rev. 2
1
Publication Order Number:
NTB90N02/D
NTB90N02, NTP90N02
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Symbol
Min
Typ
Max
24
−
27
25
−
−
−
−
−
−
1.0
10
−
−
±100
1.0
−
1.9
−3.8
3.0
−
−
−
−
−
5.0
7.5
5.0
7.5
5.8
9.0
5.8
9.0
gFS
−
25
−
mhos
Ciss
−
2120
−
pF
Coss
−
900
−
Crss
−
360
−
td(on)
−
16
−
tr
−
90
−
td(off)
−
28
−
tf
−
60
−
QT
−
29
−
Q1
−
8.0
−
Q2
−
20
−
(IS = 2.3 Adc, VGS = 0 Vdc)
(IS = 40 Adc, VGS = 0 Vdc) (Note 3)
(IS = 2.3 Adc, VGS = 0 Vdc, TJ = 150°C)
VSD
−
−
−
0.75
1.2
0.65
1.0
−
−
Vdc
(IS = 2.3 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s) (Note 3)
trr
−
40
−
ns
ta
−
21
−
tb
−
18
−
QRR
−
0.036
−
Characteristic
Unit
OFF CHARACTERISTICS
V(BR)DSS
Drain−to−Source Breakdown Voltage (Note 3)
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(VDS = 24 Vdc, VGS = 0 Vdc)
(VDS = 24 Vdc, VGS = 0 Vdc, TJ = 150°C)
IDSS
Gate−Body Leakage Current (VGS = 20 Vdc, VDS = 0 Vdc)
IGSS
Vdc
mV/°C
Adc
nAdc
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage (Note 3)
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)
VGS(th)
Static Drain−to−Source On−Resistance (Note 3)
(VGS = 10 Vdc, ID = 90 Adc)
(VGS = 4.5 Vdc, ID = 40 Adc)
(VGS = 10 Vdc, ID = 20 Adc)
(VGS = 4.5 Vdc, ID = 20 Adc)
RDS(on)
Forward Transconductance (Note 3) (VDS = 15 Vdc, ID = 10 Adc)
Vdc
mV/°C
m
DYNAMIC CHARACTERISTICS
(VDS = 20 Vdc, VGS = 0 Vdc,
f=1
1.0
0 MHz)
Input Capacitance
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS (Note 4)
(VDD = 20 Vdc, ID = 20 Adc,
VGS = 4
4.5
5 Vdc
Vdc, RG = 2
2.5
5 )
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Gate Charge
(VDS = 20 Vdc, ID = 20 Adc,
VGS = 4.5
4 5 Vdc) (Note 3)
ns
nC
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
Reverse Recovery Time
Reverse Recovery Stored Charge
3. Pulse Test: Pulse Width ≤ 300 s, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.
http://onsemi.com
2
C
NTB90N02, NTP90N02
100
ID, DRAIN CURRENT (AMPS)
4.4 V
4.6 V
8V
80
TJ = 25°C
4.2 V
4.8 V
5V
70
60
6.5 V
50
4V
5.2 V
6V
ID, DRAIN CURRENT (AMPS)
9V
90
3.8 V
3.6 V
40
30
3.4 V
20
3.2 V
10
VGS = 3.0 V
0
0.5
1
1.5
2
2.5
3.5
3
4
VDS ≥ 24 V
TJ = 25°C
TJ = 125°C
TJ = −55°C
2
3
4
5
6
VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.07
ID = 10 A
TJ = 25°C
0.06
0.05
0.04
0.03
0.02
0.01
0
0
2
4
6
8
10
RDS(on), DRAIN−TO−SOURCE RESISTANCE ()
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
0.015
TJ = 25°C
VGS = 4.5 V
0.01
VGS = 10 V
0.005
0
55
60
65
70
75
80
85
90
VGS, GATE−TO−SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance versus
Gate−To−Source Voltage
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
0.015
1000
VGS = 0 V
ID = 90 A
VDS = 4.5 V
0.0125
0.001
0.0075
ID = 10 A
VDS = 10 V
0.005
0.0025
0
−50
−25
0
25
50
75
100
TJ = 125°C
100
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
RDS(on), DRAIN−TO−SOURCE RESISTANCE ()
0
160
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
125
150
TJ = 100°C
10
1
TJ = 25°C
0.1
0.01
4
8
12
16
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−To−Source Leakage
Current versus Voltage
http://onsemi.com
3
20
VGS = 0 V
TJ = 25°C
4000
3000
Ciss
2000
Coss
1000
Crss
0
−8 −6 −4 −2 0 2 4
VGS VDS
6
8 10 12 14 16 18 20 22 24
10
28
QT
8
20
VGS
VD
6
16
Q1
4
Q2
12
8
2
ID = 1.0 A
TJ = 25°C
0
0
10
20
30
40
4
0
50
Qg, TOTAL GATE CHARGE (nC)
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage versus Total Charge
1000
90
IS, SOURCE CURRENT (AMPS)
VDD = 20 V
ID = 20 A
VGS = 10 V
t, TIME (ns)
24
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
5000
VGS, GATE−TO−SOURCE VOLTAGE (V)
NTB90N02, NTP90N02
tr
100
tf
td(off)
td(on)
10
80
70
60
50
40
30
20
10
0
0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00
1
1
10
VGS = 0 V
TJ = 25°C
100
RG, GATE RESISTANCE ()
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
Figure 10. Diode Forward Voltage versus
Current
ORDERING INFORMATION
Package
Shipping†
NTP90N02
TO−220AB
50 Units / Rail
NTP90N02G
TO−220AB
(Pb−Free)
50 Units / Rail
D2PAK
50 Units / Rail
NTB90N02G
D2PAK
(Pb−Free)
50 Units / Rail
NTB90N02T4
D2PAK
800 Tape & Reel
D2PAK
(Pb−Free)
800 Tape & Reel
Device
NTB90N02
NTB90N02T4G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
4
NTB90N02, NTP90N02
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
The capacitance (Ciss) is read from the capacitance curve
at a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
t QIG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr Q2 R210(VGG VGSP)
tf Q2 R2VGSP
where:
VGG = the gate drive voltage, which varies from
zero to VGG
RG = the gate drive resistance and Q2 and VGSP
are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current
is not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network.
The equations are:
td(on) RG Ciss In [VGG(VGG VGSP)]
td(off) RG Ciss In (VGGVGSP)
http://onsemi.com
5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−220
CASE 221A
ISSUE AK
DATE 13 JAN 2022
SCALE 1:1
STYLE 1:
PIN 1.
2.
3.
4.
BASE
COLLECTOR
EMITTER
COLLECTOR
STYLE 2:
PIN 1.
2.
3.
4.
BASE
EMITTER
COLLECTOR
EMITTER
STYLE 3:
PIN 1.
2.
3.
4.
CATHODE
ANODE
GATE
ANODE
STYLE 4:
PIN 1.
2.
3.
4.
MAIN TERMINAL 1
MAIN TERMINAL 2
GATE
MAIN TERMINAL 2
STYLE 5:
PIN 1.
2.
3.
4.
GATE
DRAIN
SOURCE
DRAIN
STYLE 6:
PIN 1.
2.
3.
4.
ANODE
CATHODE
ANODE
CATHODE
STYLE 7:
PIN 1.
2.
3.
4.
CATHODE
ANODE
CATHODE
ANODE
STYLE 8:
PIN 1.
2.
3.
4.
CATHODE
ANODE
EXTERNAL TRIP/DELAY
ANODE
STYLE 9:
PIN 1.
2.
3.
4.
GATE
COLLECTOR
EMITTER
COLLECTOR
STYLE 10:
PIN 1.
2.
3.
4.
GATE
SOURCE
DRAIN
SOURCE
STYLE 11:
PIN 1.
2.
3.
4.
DRAIN
SOURCE
GATE
SOURCE
STYLE 12:
PIN 1.
2.
3.
4.
MAIN TERMINAL 1
MAIN TERMINAL 2
GATE
NOT CONNECTED
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42148B
TO−220
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
D2PAK 3
CASE 418B−04
ISSUE L
DATE 17 FEB 2015
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 418B−01 THRU 418B−03 OBSOLETE,
NEW STANDARD 418B−04.
C
E
−B−
V
W
4
1
2
A
S
3
−T−
SEATING
PLANE
K
W
J
G
D
DIM
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
S
V
H
3 PL
0.13 (0.005)
M
T B
M
VARIABLE
CONFIGURATION
ZONE
N
R
P
L
M
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
L
M
F
F
F
VIEW W−W
1
VIEW W−W
2
VIEW W−W
3
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
MILLIMETERS
MIN
MAX
8.64
9.65
9.65 10.29
4.06
4.83
0.51
0.89
1.14
1.40
7.87
8.89
2.54 BSC
2.03
2.79
0.46
0.64
2.29
2.79
1.32
1.83
7.11
8.13
5.00 REF
2.00 REF
0.99 REF
14.60 15.88
1.14
1.40
U
L
M
INCHES
MIN
MAX
0.340 0.380
0.380 0.405
0.160 0.190
0.020 0.035
0.045 0.055
0.310 0.350
0.100 BSC
0.080
0.110
0.018 0.025
0.090
0.110
0.052 0.072
0.280 0.320
0.197 REF
0.079 REF
0.039 REF
0.575 0.625
0.045 0.055
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 4:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 5:
STYLE 6:
PIN 1. CATHODE
PIN 1. NO CONNECT
2. ANODE
2. CATHODE
3. CATHODE
3. ANODE
4. ANODE
4. CATHODE
MARKING INFORMATION AND FOOTPRINT ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42761B
D2PAK 3
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
D2PAK 3
CASE 418B−04
ISSUE L
DATE 17 FEB 2015
GENERIC
MARKING DIAGRAM*
xx
xxxxxxxxx
AWLYWWG
xxxxxxxxG
AYWW
AYWW
xxxxxxxxG
AKA
IC
Standard
Rectifier
xx
A
WL
Y
WW
G
AKA
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
= Polarity Indicator
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
SOLDERING FOOTPRINT*
10.49
8.38
16.155
2X
3.504
2X
1.016
5.080
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42761B
D2PAK 3
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Email Requests to: orderlit@onsemi.com
onsemi Website: www.onsemi.com
◊
TECHNICAL SUPPORT
North American Technical Support:
Voice Mail: 1 800−282−9855 Toll Free USA/Canada
Phone: 011 421 33 790 2910
Europe, Middle East and Africa Technical Support:
Phone: 00421 33 790 2910
For additional information, please contact your local Sales Representative