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onsemi and and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or
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notice. The information herein is provided “as-is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality,
or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws,
regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/
or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application
by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized
for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for
implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative
Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. Other names and brands may be claimed as the property of others.
NTD15N06
Power MOSFET
15 Amps, 60 Volts
N−Channel DPAK
Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
circuits.
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15 AMPERES
60 VOLTS
RDS(on) = 76 mW (TYP)
Features
• Pb−Free Packages are Available
N−Channel
Applications
•
•
•
•
D
Power Supplies
Converters
Power Motor Controls
Bridge Circuits
G
S
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
60
Vdc
Drain−to−Gate Voltage (RGS = 1.0 MW)
VDGR
60
Vdc
Gate−to−Source Voltage
− Continuous
− Non−repetitive (tpv10 ms)
Drain Current
− Continuous @ TA = 25°C
− Continuous @ TA = 100°C
− Single Pulse (tpv10 ms)
Total Power Dissipation @ TJ = 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C (Note 1)
Total Power Dissipation @ TA = 25°C (Note 2)
Operating and Storage Temperature Range
Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, L = 1.0 mH,
IL(pk) = 11 A, VDS = 60 Vdc)
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient (Note 1)
− Junction−to−Ambient (Note 2)
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
Vdc
VGS
VGS
"20
"30
ID
ID
15
10
45
Adc
PD
48
0.32
2.1
1.5
W
W/°C
W
W
−55 to
+175
°C
August, 2006 − Rev. 3
4
1 2
YWW
15
N06G
DPAK
CASE 369C
STYLE 2
3
4
IDM
TJ, Tstg
EAS
mJ
61
1
2
3
15
N06
Y
W
G
3.13
71.4
100
TL
260
= Device Code
= Specific Device
= Year
= Work Week
Pb−Free Package
ORDERING INFORMATION
Device
RqJC
RqJA
RqJA
YWW
15
N06G
DPAK−3
CASE 369D
STYLE 2
Apk
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. When surface mounted to an FR4 board using 0.5 sq in pad size.
2. When surface mounted to an FR4 board using the minimum recommended
pad size.
© Semiconductor Components Industries, LLC, 2006
MARKING
DIAGRAMS
1
NTD15N06
Package
Shipping†
DPAK
75 Units / Rail
NTD15N06G
DPAK
(Pb−Free)
75 Units / Rail
NTD15N06−1
DPAK−3
75 Units / Rail
DPAK−3
(Pb−Free)
75 Units / Rail
DPAK
2500/Tape & Reel
DPAK
(Pb−Free)
2500/Tape & Reel
NTD15N06−1G
NTD15N06T4
NTD15N06T4G
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Publication Order Number:
NTD15N06/D
NTD15N06
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
60
−
68
54.4
−
−
−
−
−
−
1.0
10
−
−
±100
2.0
−
2.9
6.3
4.0
−
−
76
90
−
−
1.2
1.08
1.62
−
gFS
−
6.7
−
Mhos
pF
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage (Note 3)
(VGS = 0 Vdc, ID = 250 mAdc)
Temperature Coefficient (Positive)
V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C)
IDSS
Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc)
IGSS
Vdc
mV/°C
mAdc
nAdc
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage (Note 3)
(VDS = VGS, ID = 250 mAdc)
Threshold Temperature Coefficient (Negative)
VGS(th)
Static Drain−to−Source On−Resistance (Note 3)
(VGS = 10 Vdc, ID = 7.5 Adc)
RDS(on)
Static Drain−to−Source On−Voltage (Note 3)
(VGS = 10 Vdc, ID = 15 Adc)
(VGS = 10 Vdc, ID = 7.5 Adc, TJ = 150°C)
VDS(on)
Forward Transconductance (Note 3) (VDS = 7.0 Vdc, ID = 6.0 Adc)
Vdc
mV/°C
mW
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Transfer Capacitance
Ciss
−
325
450
Coss
−
108
150
Crss
−
34
70
td(on)
−
10
15
tr
−
25
70
td(off)
−
14
50
tf
−
13
50
QT
−
12
20
Q1
−
4.1
−
Q2
−
4.5
−
VSD
−
−
0.96
0.83
1.15
−
Vdc
trr
−
35
−
ns
ta
−
27
−
tb
−
7.4
−
QRR
−
0.050
−
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
(VDD = 48 Vdc, ID = 15 Adc,
VGS = 10 Vdc, RG = 9.1 W) (Note 3)
Fall Time
Gate Charge
(VDS = 48 Vdc, ID = 15 Adc,
VGS = 10 Vdc) (Note 3)
ns
nC
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(IS = 15 Adc, VGS = 0 Vdc) (Note 3)
(IS = 15 Adc, VGS = 0 Vdc, TJ = 150°C)
Reverse Recovery Time
(IS = 15 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/ms) (Note 3)
Reverse Recovery Stored Charge
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperatures.
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2
mC
NTD15N06
ID, DRAIN CURRENT (AMPS)
32
8V
VDS ≥ 10 V
7V
24
6.5 V
6V
16
5.5 V
8
5V
4.5 V
0
0.2
1
2
3
5
4
TJ = 25°C
0.08
TJ = −55°C
0.04
4
4
8
12
16
20
24
28
32
0.2
5
8
7
6
VGS = 15 V
0.16
0.12
TJ = 100°C
0.08
TJ = 25°C
TJ = −55°C
0.04
0
0
4
8
12
16
20
24
28
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus Drain Current
Figure 4. On−Resistance versus Drain Current
1000
ID = 7.5 A
VGS = 10 V
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
TJ = −55°C
Figure 2. Transfer Characteristics
0.12
1.8
TJ = 100°C
Figure 1. On−Region Characteristics
TJ = 100°C
2
TJ = 25°C
8
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
VGS = 10 V
0
16
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0.16
0
24
0
3
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
9V
VGS = 10 V
ID, DRAIN CURRENT (AMPS)
32
1.6
1.4
1.2
1
32
VGS = 0 V
TJ = 150°C
100
10
TJ = 100°C
0.8
0.6
−50 −25
0
25
50
75
100
125
150
175
1
0
10
20
30
40
50
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
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3
60
NTD15N06
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
900
VDS = 0 V
C, CAPACITANCE (pF)
800
700
VGS = 0 V
TJ = 25°C
Ciss
600
500
400
Crss
Ciss
300
200
Coss
100
Crss
0
10
5
VGS
0
VDS
10
5
15
20
25
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
100
12
10
VGS
8
Q1
6
Q2
4
2
0
VDS = 30 V
ID = 15 A
VGS = 10 V
QT
t, TIME (ns)
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
NTD15N06
tr
td(off)
10
tf
td(on)
ID = 15 A
TJ = 25°C
0
2
8
10
4
6
QG, TOTAL GATE CHARGE (nC)
1
12
1
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
10
RG, GATE RESISTANCE (W)
100
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
IS, SOURCE CURRENT (AMPS)
16
VGS = 0 V
TJ = 25°C
12
8
4
0
0.6
0.68
0.76
0.84
0.92
1
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous ID can safely be assumed to
equal the values indicated.
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 ms. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) − TC)/(RqJC).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
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5
NTD15N06
ID, DRAIN CURRENT (AMPS)
100
VGS = 20 V
SINGLE PULSE
TC = 25°C
10 ms
10
100 ms
1 ms
10 ms
1
0.1
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
(NORMALIZED)
0.1
dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1
10
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
100
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
SAFE OPERATING AREA
80
ID = 11 A
60
40
20
0
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
1.0
25
50
75
100
125
150
175
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
D = 0.5
0.2
0.1
0.1
P(pk)
0.05
0.02
0.01
t1
t2
DUTY CYCLE, D = t1/t2
SINGLE PULSE
0.01
0.00001
0.0001
0.001
0.01
t, TIME (ms)
RqJC(t) = r(t) RqJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) RqJC(t)
0.1
Figure 13. Thermal Response
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 14. Diode Reverse Recovery Waveform
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6
1
10
NTD15N06
PACKAGE DIMENSIONS
DPAK
CASE 369C−01
ISSUE O
−T−
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
SEATING
PLANE
4
Z
A
S
1
2
INCHES
DIM MIN
MAX
A 0.235 0.245
B 0.250 0.265
C 0.086 0.094
D 0.027 0.035
E 0.018 0.023
F 0.037 0.045
G
0.180 BSC
H 0.034 0.040
J
0.018 0.023
K 0.102 0.114
L
0.090 BSC
R 0.180 0.215
S 0.025 0.040
U 0.020
−−−
V 0.035 0.050
Z 0.155
−−−
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
E
R
3
U
K
F
J
L
H
D
G
2 PL
0.13 (0.005)
M
T
SOLDERING FOOTPRINT*
6.20
0.244
3.0
0.118
2.58
0.101
5.80
0.228
1.6
0.063
6.172
0.243
SCALE 3:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
MILLIMETERS
MIN
MAX
5.97
6.22
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.14
4.58 BSC
0.87
1.01
0.46
0.58
2.60
2.89
2.29 BSC
4.57
5.45
0.63
1.01
0.51
−−−
0.89
1.27
3.93
−−−
NTD15N06
DPAK−3 (SINGLE GAUGE)
CASE 369D−01
ISSUE B
C
B
V
E
R
4
Z
A
S
1
2
3
−T−
SEATING
PLANE
K
J
F
D
G
H
M
DIM
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
0.155
−−−
MILLIMETERS
MIN
MAX
5.97
6.35
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.14
2.29 BSC
0.87
1.01
0.46
0.58
8.89
9.65
4.45
5.45
0.63
1.01
0.89
1.27
3.93
−−−
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
3 PL
0.13 (0.005)
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
T
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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For additional information, please contact your local
Sales Representative
NTD15NO6/D
