NTD23N03RT4G

NTD23N03R Power MOSFET 23 A, 25 V, N−Channel DPAK Features • • • • • • Planar HD3e Process for Fast Switching Performance Low RDS(on) to Minimize Conduction Loss Low Ciss to Minimize Driver Loss Low Gate Charge Optimized for High Side Switching Requirements in High−Efficiency DC−DC Converters Pb−Free Packages are Available http://onsemi.com V(BR)DSS RDS(on) TYP ID MAX 25 V 32 mW 23 A N−CHANNEL D MAXIMUM RATINGS (TJ = 25°C unless otherwise specified) Value Unit VDSS 25 Vdc Gate−to−Source Voltage − Continuous VGS ±20 Vdc Thermal Resistance, Junction−to−Case Total Power Dissipation @ TC = 25°C Drain Current − Continuous @ TC = 25°C, Chip − Continuous @ TC = 25°C, Limited by Package − Single Pulse RqJC PD 5.6 22.3 °C/W W ID ID 23 17.1 A A IDM 40 A Thermal Resistance, Junction−to−Ambient (Note 1) Total Power Dissipation @ TA = 25°C Drain Current − Continuous @ TA = 25°C RqJA 76 °C/W PD ID 1.64 4.5 W A Thermal Resistance, Junction−to−Ambient (Note 2) Total Power Dissipation @ TA = 25°C Drain Current − Continuous @ TA = 25°C RqJA 110 °C/W PD ID 1.14 3.8 W A Operating and Storage Temperature Range TJ, Tstg −55 to 150 °C Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds TL 260 °C Drain−to−Source Voltage Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. When surface mounted to an FR4 board using 0.5 sq in pad size. 2. When surface mounted to an FR4 board using minimum recommended pad size. G S MARKING DIAGRAMS 4 Drain 4 1 2 3 DPAK CASE 369AA (Surface Mounted) STYLE 2 AYWW T23 N03G Symbol 2 1 3 Drain Gate Source 4 Drain 4 1 2 DPAK−3 CASE 369D (Straight Lead) STYLE 2 AYWW T23 N03G Parameter 3 1 2 3 Gate Drain Source T23N03 A Y WW G = Device Code = Assembly Location = Year = Work Week = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. © Semiconductor Components Industries, LLC, 2009 March, 2009 − Rev. 5 1 Publication Order Number: NTD23N03R/D NTD23N03R ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Characteristics Symbol Min Typ Max 25 − 28 − − − − − − − 1.0 10 − − ±100 1.0 − 1.8 − 2.0 − − − 50.3 32.3 60 45 − 13 − Ciss − 225 − Coss − 108 − Crss − 48 − td(on) − 2.0 − tr − 14.9 − td(off) − 9.9 − tf − 2.0 − QT − 3.76 − Q1 − 1.7 − Q2 − 1.6 − − − 0.87 0.74 1.2 − trr − 8.7 − ta − 5.2 − tb − 3.5 − QRR − 0.003 − Unit OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage (Note 3) (VGS = 0 Vdc, ID = 250 mAdc) Temperature Coefficient (Positive) V(br)DSS Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 150°C) IDSS Gate−Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/°C mAdc nAdc ON CHARACTERISTICS (Note 3) Gate Threshold Voltage (Note 3) (VDS = VGS, ID = 250 mAdc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain−to−Source On−Resistance (Note 3) (VGS = 4.5 Vdc, ID = 6 Adc) (VGS = 10 Vdc, ID = 6 Adc) RDS(on) Forward Transconductance (Note 3) (VDS = 10 Vdc, ID = 6 Adc) gFS Vdc mV/°C mW Mhos DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 20 Vdc, VGS = 0 V, f = 1 MHz) Transfer Capacitance pF SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time (VGS = 10 Vdc, VDD = 10 Vdc, ID = 6 Adc, RG = 3 W) Fall Time Gate Charge (VGS = 4.5 Vdc, ID = 6 Adc, VDS = 10 Vdc) (Note 3) ns nC SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (IS = 6 Adc, VGS = 0 Vdc) (Note 3) (IS = 6 Adc, VGS = 0 Vdc, TJ = 125°C) Reverse Recovery Time (IS = 6 Adc, VGS = 0 Vdc, dIS/dt = 100 A/ms) (Note 3) Reverse Recovery Stored Charge 3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 VSD Vdc ns mC NTD23N03R 4V 5V 12 ID, DRAIN CURRENT (AMPS) 16 3.5 V 8 3V 4 VGS = 2.5 V 0 2 6 4 8 12 8 TJ = 25°C 4 TJ = −55°C TJ = 125°C 0 1 2 3 4 5 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics VGS = 10 V 0.16 0.12 0.08 TJ = 125°C TJ = 25°C 0.04 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 16 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 0.20 0 VDS ≥ 10 V 0 10 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 20 4.5 V 8V 6V TJ = −55°C 0 4 12 8 16 20 6 0.20 VGS = 4.5 V 0.16 0.12 TJ = 125°C 0.08 TJ = 25°C 0.04 0 TJ = −55°C 0 4 8 12 16 20 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance versus Drain Current and Temperature Figure 4. On−Resistance versus Drain Current and Temperature 10,000 1.8 1.6 VGS = 0 V ID = 6 A VGS = 10 V IDSS, LEAKAGE (nA) ID, DRAIN CURRENT (AMPS) 20 10 V 1.4 1.2 1 1000 TJ = 150°C TJ = 125°C 100 0.8 0.6 −50 −25 0 25 50 75 100 125 150 10 0 5 10 15 20 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current versus Voltage http://onsemi.com 3 25 400 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) NTD23N03R TJ = 25°C VDS = 0 V VGS = 0 V C, CAPACITANCE (pF) Ciss 300 Crss Ciss 200 Coss 100 Crss 10 5 10 15 20 QT 4 Q2 Q1 2 ID = 6 A TJ = 25°C 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 Qg, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation Figure 8. Gate−to−Source and Drain−to−Source Voltage versus Total Charge 10 VDS = 10 V ID = 6 A VGS = 10 V tr td(off) 10 td(on) tf 1 10 VGS = 0 V 8 6 4 TJ = 150°C 2 TJ = 25°C 0 100 0 0.2 0.4 0.6 0.8 RG, GATE RESISTANCE (W) VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure 10. Diode Forward Voltage versus Current 100 ID, DRAIN CURRENT (AMPS) 1 VGS 6 GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) 100 t, TIME (ns) VGS 0 VDS 5 IS, SOURCE CURRENT (AMPS) 0 8 VGS = 20 V SINGLE PULSE TC = 25°C 10 10 ms 100 ms 1 ms 10 ms 1 0.1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 dc 10 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 11. Maximum Rated Forward Biased Safe Operating Area http://onsemi.com 4 100 1.0 NTD23N03R r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 10 D = 0.5 0.2 1 0.1 P(pk) 0.05 t1 0.01 t2 DUTY CYCLE, D = t1/t2 SINGLE PULSE 0.1 0.00001 0.0001 0.001 0.01 t, TIME (s) 0.1 1 10 Figure 12. Thermal Response ORDERING INFORMATION Package Shipping† NTD23N03RG DPAK (Pb−Free) 75 Units/Rail NTD23N03R−1G DPAK−3 (Pb−Free) 75 Units/Rail DPAK 2500 Tape & Reel DPAK (Pb−Free) 2500 Tape & Reel Device NTD23N03RT4 NTD23N03RT4G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 5 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS IPAK CASE 369D−01 ISSUE C SCALE 1:1 C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. E R 4 Z A S 1 2 3 −T− SEATING PLANE K J F D G DATE 15 DEC 2010 H 3 PL 0.13 (0.005) M DIM A B C D E F G H J K R S V Z INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 −−− T MARKING DIAGRAMS STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE Discrete YWW xxxxxxxx STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR xxxxxxxxx A lL Y WW DOCUMENT NUMBER: DESCRIPTION: 98AON10528D Integrated Circuits xxxxx ALYWW x = Device Code = Assembly Location = Wafer Lot = Year = Work Week Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. IPAK (DPAK INSERTION MOUNT) PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DPAK (SINGLE GUAGE) CASE 369AA−01 ISSUE B 4 1 2 DATE 03 JUN 2010 3 SCALE 1:1 A E b3 c2 B Z D 1 L4 A 4 L3 2 b2 H DETAIL A 3 c b 0.005 (0.13) e M H C L2 GAUGE PLANE C L L1 DETAIL A A1 ROTATED 905 CW STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE SOLDERING FOOTPRINT* 6.20 0.244 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. C 2.58 0.102 5.80 0.228 3.00 0.118 1.60 0.063 INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.030 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.108 REF 0.020 BSC 0.035 0.050 −−− 0.040 0.155 −−− MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.76 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.74 REF 0.51 BSC 0.89 1.27 −−− 1.01 3.93 −−− GENERIC MARKING DIAGRAM* XXXXXXG ALYWW YWW XXX XXXXXG IC Discrete XXXXXX A L Y WW G 6.17 0.243 SCALE 3:1 SEATING PLANE DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON13126D DPAK (SINGLE GAUGE) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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