NTD40N03RT4G

NTD40N03R Power MOSFET 45 A, 25 V, N−Channel DPAK Features • • • • • • Planar HD3e Process for Fast Switching Performance Low RDS(on) to Minimize Conduction Loss Low Ciss to Minimize Driver Loss Low Gate Charge Optimized for High Side Switching Requirements in High−Efficiency DC−DC Converters These are Pb−Free Devices http://onsemi.com 45 AMPERES, 25 VOLTS RDS(on) = 12.6 mW (Typ) N−CHANNEL D MAXIMUM RATINGS (TJ = 25°C unless otherwise specified) Parameter Symbol Value Unit Drain−to−Source Voltage VDSS 25 Vdc Gate−to−Source Voltage − Continuous VGS ±20 Vdc Thermal Resistance − Junction−to−Case Total Power Dissipation @ TC = 25°C Drain Current − Continuous @ TC = 25°C, Chip − Continuous @ TA = 25°C, Limited by Wires − Single Pulse (tp ≤ 10 ms) RqJC PD 3.0 50 °C/W W ID ID ID 45 32 100 A A A Thermal Resistance − Junction−to−Ambient (Note 1) − Total Power Dissipation @ TA = 25°C − Drain Current − Continuous @ TA = 25°C RqJA 71.4 °C/W PD ID 2.1 9.2 W A 3 Thermal Resistance − Junction−to−Ambient (Note 2) − Total Power Dissipation @ TA = 25°C − Drain Current − Continuous @ TA = 25°C RqJA 100 °C/W PD ID 1.5 7.8 W A CASE 369AA DPAK (Surface Mount) STYLE 2 TJ, Tstg −55 to 175 °C TL 260 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. When surface mounted to an FR4 board using 0.5 sq. in pad size. 2. When surface mounted to an FR4 board using minimum recommended pad size. 4 4 1 2 1 2 3 CASE 369D DPAK (Straight Lead) STYLE 2 MARKING DIAGRAM & PIN ASSIGNMENTS 4 Drain 4 Drain 1 Gate 2 Drain Y WW T40N03 G YWW T40 N03G Maximum Lead Temperature for Soldering Purposes, 1/8 in from case for 10 seconds S YWW T40 N03G Operating and Storage Temperature Range G 3 Source 1 Gate 2 Drain 3 Source = Year = Work Week = Device Code = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. © Semiconductor Components Industries, LLC, 2010 July, 2010 − Rev. 7 1 Publication Order Number: NTD40N03R/D NTD40N03R ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Characteristics Symbol Min Typ Max 25 − 28 − − − − − − − 1.0 10 − − ±100 1.0 − 1.7 − 2.0 − − − 18.6 12.6 23 16.5 − 20 − Ciss − 584 − Coss − 254 − Crss − 99 − td(on) − 4.5 − tr − 19.5 − td(off) − 16.7 − tf − 3.5 − QT − 5.78 − Q1 − 2.1 − Q2 − 2.5 − − − 0.85 0.71 1.2 − trr − 20.4 − ta − 8.25 − tb − 12.1 − QRR − 0.007 − Unit OFF CHARACTERISTICS V(br)DSS Drain−to−Source Breakdown Voltage (Note 3) (VGS = 0 Vdc, ID = 250 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 150°C) IDSS Gate−Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/°C mAdc nAdc ON CHARACTERISTICS (Note 3) Gate Threshold Voltage (Note 3) (VDS = VGS, ID = 250 mAdc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain−to−Source On−Resistance (Note 3) (VGS = 4.5 Vdc, ID = 10 Adc) (VGS = 10 Vdc, ID = 10 Adc) RDS(on) Forward Transconductance (Note 3) (VDS = 10 Vdc, ID = 10 Adc) gFS Vdc mV/°C mW Mhos DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 20 Vdc, VGS = 0 V, f = 1 MHz) Transfer Capacitance pF SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time (VGS = 10 Vdc, VDD = 10 Vdc, ID = 10 Adc, RG = 3 W) Fall Time Gate Charge (VGS = 4.5 Vdc, ID = 10 Adc, VDS = 10 Vdc) (Note 3) ns nC SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (IS = 10 Adc, VGS = 0 Vdc) (Note 3) (IS = 10 Adc, VGS = 0 Vdc, TJ = 125°C) Reverse Recovery Time (IS = 10 Adc, VGS = 0 Vdc, dIS/dt = 100 A/ms) (Note 3) Reverse Recovery Stored Charge 3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 VSD Vdc ns mC NTD40N03R 10 V 20 3.5 V 8V 16 VDS ≥ 10 V 3.4 V 6V 4V 12 3.2 V 8 3V 4 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) 20 2.8 V 16 12 8 TJ = 25°C 4 TJ = 125°C VGS = 2.6 V 0 2 4 8 6 10 1 2 3 4 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics VGS = 10 V 0.032 0.024 TJ = 150°C 0.016 TJ = 125°C TJ = 25°C 0.008 TJ = −55°C 4 0 8 12 16 20 TJ = 150°C 0.032 TJ = 125°C 0.024 TJ = 25°C 0.016 TJ = −55°C 0.008 VGS = 4.5 V 0 0 4 8 12 16 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance versus Drain Current and Temperature Figure 4. On−Resistance versus Drain Current and Temperature VGS = 0 V ID = 10 A VGS = 10 V 1.4 1.2 1 TJ = 150°C 1000 TJ = 125°C 0.8 0.6 −50 20 10,000 1.8 1.6 5 0.040 IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 0 TJ = −55°C VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 0.040 0 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0 −25 0 25 50 75 100 125 150 100 0 5 10 15 20 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current versus Voltage http://onsemi.com 3 25 Ciss 800 Crss 600 Ciss 400 Coss 200 Crss 10 VGS 0 VDS 5 5 10 15 20 VGS 6 QT 4 Q2 Q1 2 ID = 10 A TJ = 25°C 0 0 2 4 6 8 Qg, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation Figure 8. Gate−to−Source and Drain−to−Source Voltage versus Total Charge 100 20 VDS = 10 V ID = 10 A VGS = 10 V tr td(off) 10 td(on) tf 1 8 GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) IS, SOURCE CURRENT (AMPS) 0 t, TIME (ns) TJ = 25°C VDS = 0 V VGS = 0 V 1 10 18 VGS = 0 V 16 TJ = 25°C 14 12 10 8 6 4 2 0 100 0 0.2 0.4 0.6 0.8 RG, GATE RESISTANCE (W) VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure 10. Diode Forward Voltage versus Current 100 I D, DRAIN CURRENT (AMPS) C, CAPACITANCE (pF) 1000 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) NTD40N03R SINGLE PULSE VGS = 20 V TC = 25°C 10 ms 100 ms 10 1 ms 1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 10 ms dc 10 1 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 11. Maximum Rated Forward Biased Safe Operating Area http://onsemi.com 4 100 1.0 r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) NTD40N03R 1.0 D = 0.5 0.2 0.1 P(pk) 0.1 0.05 0.01 0.02 t1 0.01 SINGLE PULSE 0.00001 0.0001 t2 DUTY CYCLE, D = t1/t2 0.001 0.01 t, TIME (s) 0.1 RqJC(t) = r(t) RqJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RqJC(t) 1 10 Figure 12. Thermal Response ORDERING INFORMATION Package Shipping† NTD40N03R−1G DPAK (Straight Lead) (Pb−Free) 75 Units/Rail NTD40N03RT4G DPAK (Pb−Free) 2500 Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 5 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS IPAK CASE 369D−01 ISSUE C SCALE 1:1 C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. E R 4 Z A S 1 2 3 −T− SEATING PLANE K J F D G DATE 15 DEC 2010 H 3 PL 0.13 (0.005) M DIM A B C D E F G H J K R S V Z INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 −−− T MARKING DIAGRAMS STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE Discrete YWW xxxxxxxx STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR xxxxxxxxx A lL Y WW DOCUMENT NUMBER: DESCRIPTION: 98AON10528D Integrated Circuits xxxxx ALYWW x = Device Code = Assembly Location = Wafer Lot = Year = Work Week Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. IPAK (DPAK INSERTION MOUNT) PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DPAK (SINGLE GUAGE) CASE 369AA−01 ISSUE B 4 1 2 DATE 03 JUN 2010 3 SCALE 1:1 A E b3 c2 B Z D 1 L4 A 4 L3 2 b2 H DETAIL A 3 c b 0.005 (0.13) e M H C L2 GAUGE PLANE C L L1 DETAIL A A1 ROTATED 905 CW STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE SOLDERING FOOTPRINT* 6.20 0.244 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. C 2.58 0.102 5.80 0.228 3.00 0.118 1.60 0.063 INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.030 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.108 REF 0.020 BSC 0.035 0.050 −−− 0.040 0.155 −−− MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.76 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.74 REF 0.51 BSC 0.89 1.27 −−− 1.01 3.93 −−− GENERIC MARKING DIAGRAM* XXXXXXG ALYWW YWW XXX XXXXXG IC Discrete XXXXXX A L Y WW G 6.17 0.243 SCALE 3:1 SEATING PLANE DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON13126D DPAK (SINGLE GAUGE) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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