NTD4809N-35G

NTD4809N, NVD4809N MOSFET – Power, Single, N-Channel, DPAK/IPAK 30 V, 58 A Features http://onsemi.com Low RDS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses AEC Q101 Qualified − NVD4809N These Devices are Pb−Free and are RoHS Compliant RDS(on) MAX V(BR)DSS ID MAX 9.0 mW @ 10 V 30 V 58 A 14 mW @ 4.5 V D Applications • CPU Power Delivery • DC−DC Converters • Low Side Switching N−Channel G MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Value Unit Drain−to−Source Voltage VDSS 30 V Gate−to−Source Voltage VGS "20 V ID 13.1 A TA = 25°C TA = 85°C 10.1 TA = 25°C PD 2.63 W Continuous Drain Current (RqJA) (Note 2) TA = 25°C ID 9.6 A Power Dissipation (RqJA) (Note 2) Steady State TA = 85°C 7.4 TA = 25°C PD 1.4 W Continuous Drain Current (RqJC) (Note 1) TC = 25°C ID 58 A Power Dissipation (RqJC) (Note 1) TC = 25°C PD 52 W TA = 25°C IDM 130 A TA = 25°C IDmaxPkg 45 A TJ, Tstg −55 to 175 °C IS 43 A Drain to Source dV/dt dV/dt 6.0 V/ns Single Pulse Drain−to−Source Avalanche Energy (VDD = 24 V, VGS = 10 V, L = 1.0 mH, IL(pk) = 13.5 A, RG = 25 W) EAS 91.0 mJ Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) TL 260 °C Pulsed Drain Current TC = 85°C tp=10ms Current Limited by Package Operating Junction and Storage Temperature Source Current (Body Diode) 4 1 2 Power Dissipation (RqJA) (Note 1) 45 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 4 4 3 DPAK CASE 369AA (Bent Lead) STYLE 2 1 2 2 3 3 IPAK IPAK CASE 369D CASE 369AD (Straight Lead) (Straight Lead DPAK) STYLE 2 STYLE 2 1 MARKING DIAGRAMS & PIN ASSIGNMENTS 4 Drain 4 Drain AYWW 48 09NG Continuous Drain Current (RqJA) (Note 1) S AYWW 48 09NG Symbol Parameter 4 Drain AYWW 48 09NG • • • • • 2 1 2 3 1 Drain 3 Gate Source Gate Drain Source 1 2 3 Gate Drain Source A Y WW 4809N G = Assembly Location* = Year = Work Week = Device Code = Pb−Free Package * The Assembly Location code (A) is front side optional. In cases where the Assembly Location is stamped in the package, the front side assembly code may be blank. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. © Semiconductor Components Industries, LLC, 2014 May, 2019 − Rev. 14 1 Publication Order Number: NTD4809N/D NTD4809N, NVD4809N THERMAL RESISTANCE MAXIMUM RATINGS Symbol Value Unit Junction−to−Case (Drain) Parameter RqJC 2.9 °C/W Junction−to−TAB (Drain) RqJC−TAB 3.5 Junction−to−Ambient − Steady State (Note 1) RqJA 57.1 Junction−to−Ambient − Steady State (Note 2) RqJA 107.2 1. Surface−mounted on FR4 board using 1 in sq pad size, 1 oz Cu. 2. Surface−mounted on FR4 board using the minimum recommended pad size. ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameter Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 30 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current Gate−to−Source Leakage Current IDSS V 25 VGS = 0 V, VDS = 24 V mV/°C TJ = 25°C 1.0 TJ = 125°C 10 IGSS VDS = 0 V, VGS = ±20 V VGS(TH) VGS = VDS, ID = 250 mA mA ±100 nA 2.5 V ON CHARACTERISTICS (Note 3) Gate Threshold Voltage Negative Threshold Temperature Coefficient Drain−to−Source On Resistance Forward Transconductance VGS(TH)/TJ RDS(on) gFS 1.5 5.7 VGS = 10 to 11.5 V ID = 30 A 7.0 ID = 15 A 7.0 VGS = 4.5 V ID = 30 A 12 ID = 15 A 11 VDS = 15 V, ID = 15 A mV/°C 9.0 mW 14 9.0 S 1456 pF CHARGES AND CAPACITANCES Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge QG(TOT) Threshold Gate Charge QG(TH) Gate−to−Source Charge QGS Gate−to−Drain Charge Total Gate Charge VGS = 0 V, f = 1.0 MHz, VDS = 12 V 200 11 VGS = 4.5 V, VDS = 15 V, ID = 30 A QGD QG(TOT) 315 13 nC 2.5 4.8 5.0 VGS = 11.5 V, VDS = 15 V, ID = 30 A 25 nC 12.3 ns SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(on) tr td(off) VGS = 4.5 V, VDS = 15 V, ID = 15 A, RG = 3.0 W tf 21.3 15.1 5.3 Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 NTD4809N, NVD4809N ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) (continued) Parameter Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Symbol Test Condition Min Typ td(on) 7.0 tr 22.7 td(off) VGS = 11.5 V, VDS = 15 V, ID = 15 A, RG = 3.0 W tf Max Unit ns 25.3 2.8 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time VSD TJ = 25°C 0.95 TJ = 125°C 0.83 tRR Charge Time ta Discharge Time tb Reverse Recovery Time VGS = 0 V, IS = 30 A 19.5 VGS = 0 V, dIs/dt = 100 A/ms, IS = 30 A 1.2 V ns 10.7 8.8 QRR 9.2 nC Source Inductance LS 2.49 nH Drain Inductance, DPAK LD 0.0164 Drain Inductance, IPAK LD Gate Inductance LG 3.46 Gate Resistance RG 2.4 PACKAGE PARASITIC VALUES TA = 25°C 1.88 W Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 3 NTD4809N, NVD4809N TYPICAL PERFORMANCE CURVES 100 6V 6.5 V 5.5 V 120 TJ = 25°C 5V 90 80 4.5 V 70 60 4.2 V 50 40 4V 3.8 V 30 20 3.6 V 3.4 V 3.2 V 0 1 4 3 2 5 60 40 TJ = 125°C TJ = 25°C 20 TJ = −55°C 0 1 2 3 4 6 5 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics ID = 30 A TJ = 25°C 0.040 0.035 0.030 0.025 0.020 0.015 0.010 0.005 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 80 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 0.045 0 VDS ≥ 10 V 100 0 3 4 6 5 7 8 9 10 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 10 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 7V 0.020 TJ = 25°C 0.015 VGS = 4.5 V 0.010 VGS = 11.5 V 0.005 0 10 15 20 25 30 35 40 50 45 55 60 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance vs. Gate−to−Source Voltage Figure 4. On−Resistance vs. Drain Current and Gate Voltage 100,000 2.0 VGS = 0 V ID = 30 A VGS = 10 V TJ = 175°C 10,000 IDSS, LEAKAGE (nA) ID, DRAIN CURRENT (AMPS) 110 ID, DRAIN CURRENT (AMPS) 120 1.5 1.0 0.5 −50 −25 1000 TJ = 125°C 100 10 0 25 50 75 100 125 150 175 5 10 15 20 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Drain Voltage http://onsemi.com 4 25 NTD4809N, NVD4809N C, CAPACITANCE (pF) 2500 VDS = 0 V VGS = 0 V TJ = 25°C Ciss 2000 VGS , GATE−TO−SOURCE VOLTAGE (VOLTS) TYPICAL PERFORMANCE CURVES Ciss 1500 Crss 1000 500 Coss 0 10 Crss 5 VGS 0 VDS 5 10 15 25 20 12 9 8 7 6 5 3 2 Figure 8. Gate−To−Source and Drain−To−Source Voltage vs. Total Charge 30 IS, SOURCE CURRENT (AMPS) VDD = 15 V ID = 30 A VGS = 11.5 V t, TIME (ns) 100 td(off) 1 tr td(on) tf 1 ID = 30 A 0 V < VGS < 11.5 V TJ = 25°C 1 0 0 1 2 3 4 5 6 7 8 9 1011121314151617181920212223242526 QG, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation 10 10 RG, GATE RESISTANCE (OHMS) VGS = 0 V 25 15 10 5 0 0.5 100 1 ms 0.1 0.01 0.01 10 ms RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 dc 1 10 100 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) ID, DRAIN CURRENT (AMPS) 100 ms VGS = 20 V SINGLE PULSE TA = 25°C 0.7 0.8 1.0 0.9 Figure 10. Diode Forward Voltage vs. Current 10 ms 10 0.6 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) 1000 100 TJ = 25°C 20 Figure 9. Resistive Switching Time Variation vs. Gate Resistance 1 Q2 Q1 4 GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) 1000 QT 11 10 120 ID = 15 A 100 80 60 40 20 0 25 Figure 11. Maximum Rated Forward Biased Safe Operating Area 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 5 175 NTD4809N, NVD4809N TYPICAL PERFORMANCE CURVES I D, DRAIN CURRENT (AMPS) 100 25°C 100°C 125°C 10 1 0.1 10 100 PULSE WIDTH (ms) 1 1000 Figure 13. Avalanche Characteristics 100 r(t) (°C/W) D = 0.5 10 0.2 0.1 0.05 1 0.02 0.01 0.1 SINGLE PULSE 0.01 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 t, TIME (s) Figure 14. Thermal Response ORDERING INFORMATION Package Shipping† NTD4809NT4G DPAK (Pb−Free) 2500 / Tape & Reel NTD4809N−1G IPAK (Pb−Free) 75 Units/Rail NTD4809N−35G IPAK Trimmed Lead (3.5 ± 0.15 mm) (Pb−Free) 75 Units/Rail NVD4809NT4G DPAK (Pb−Free) 2500 / Tape & Reel Order Number †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 6 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS IPAK CASE 369D−01 ISSUE C SCALE 1:1 C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. E R 4 Z A S 1 2 3 −T− SEATING PLANE K J F D G DATE 15 DEC 2010 H 3 PL 0.13 (0.005) M DIM A B C D E F G H J K R S V Z INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 −−− T MARKING DIAGRAMS STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE Discrete YWW xxxxxxxx STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR xxxxxxxxx A lL Y WW DOCUMENT NUMBER: DESCRIPTION: 98AON10528D Integrated Circuits xxxxx ALYWW x = Device Code = Assembly Location = Wafer Lot = Year = Work Week Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. IPAK (DPAK INSERTION MOUNT) PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DPAK (SINGLE GUAGE) CASE 369AA−01 ISSUE B 4 1 2 DATE 03 JUN 2010 3 SCALE 1:1 A E b3 c2 B Z D 1 L4 A 4 L3 2 b2 H DETAIL A 3 c b 0.005 (0.13) e M H C L2 GAUGE PLANE C L L1 DETAIL A A1 ROTATED 905 CW STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE SOLDERING FOOTPRINT* 6.20 0.244 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. C 2.58 0.102 5.80 0.228 3.00 0.118 1.60 0.063 INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.030 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.108 REF 0.020 BSC 0.035 0.050 −−− 0.040 0.155 −−− MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.76 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.74 REF 0.51 BSC 0.89 1.27 −−− 1.01 3.93 −−− GENERIC MARKING DIAGRAM* XXXXXXG ALYWW YWW XXX XXXXXG IC Discrete XXXXXX A L Y WW G 6.17 0.243 SCALE 3:1 SEATING PLANE DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON13126D DPAK (SINGLE GAUGE) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS 3.5 MM IPAK, STRAIGHT LEAD CASE 369AD ISSUE B DATE 18 APR 2013 SCALE 1:1 E E3 L2 E2 A1 D2 D L1 L T SEATING PLANE NOTES: 1.. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2.. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD GATE OR MOLD FLASH. A A1 b1 2X e A2 3X E2 b 0.13 M T D2 DIM A A1 A2 b b1 D D2 E E2 E3 e L L1 L2 MILLIMETERS MIN MAX 2.19 2.38 0.46 0.60 0.87 1.10 0.69 0.89 0.77 1.10 5.97 6.22 4.80 −−− 6.35 6.73 4.57 5.45 4.45 5.46 2.28 BSC 3.40 3.60 −−− 2.10 0.89 1.27 GENERIC MARKING DIAGRAMS* OPTIONAL CONSTRUCTION STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR Discrete AYWW XXX XXXXXG XXXXXX A L Y WW G Integrated Circuits XXXXXXG ALYWW = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. DOCUMENT NUMBER: DESCRIPTION: 98AON23319D Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 3.5 MM IPAK, STRAIGHT LEAD PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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