NTD4858N
MOSFET – Power, Single,
N-Channel, DPAK/IPAK
25 V, 73 A
Features
http://onsemi.com
Trench Technology
Low RDS(on) to Minimize Conduction Losses
Low Capacitance to Minimize Driver Losses
Optimized Gate Charge to Minimize Switching Losses
These are Pb−Free Devices
V(BR)DSS
RDS(ON) MAX
ID MAX
6.2 mW @ 10 V
25 V
73 A
9.3 mW @ 4.5 V
Applications
D
• VCORE Applications
• DC−DC Converters
• High/Low Side Switching
N−CHANNEL MOSFET
G
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Gate−to−Source Voltage
Value
Unit
VDSS
25
V
VGS
±20
V
ID
14
A
Continuous Drain
Current RqJA
(Note 1)
TA = 25°C
Power Dissipation
RqJA (Note 1)
TA = 25°C
PD
2.0
W
Continuous Drain
Current RqJA
(Note 2)
TA = 25°C
ID
11.2
A
Power Dissipation
RqJA (Note 2)
TA = 85°C
Steady
State
TA = 85°C
8.7
TA = 25°C
PD
1.3
W
Continuous Drain
Current RqJC
(Note 1)
TC = 25°C
ID
73
A
Power Dissipation
RqJC (Note 1)
TC = 25°C
PD
54.5
W
TA = 25°C
IDM
146
A
TA = 25°C
IDmaxPkg
45
A
TJ,
TSTG
−55 to
+175
°C
IS
45
A
Drain to Source dV/dt
dV/dt
6
V/ns
Single Pulse Drain−to−Source Avalanche
Energy (TJ = 25°C, VDD = 50 V, VGS = 10 V,
IL = 15 Apk, L = 1.0 mH, RG = 25 W)
EAS
112.5
mJ
TL
260
°C
Pulsed Drain
Current
TC = 85°C
tp=10ms
Current Limited by Package
Operating Junction and Storage
Temperature
Source Current (Body Diode)
Lead Temperature for Soldering Purposes
(1/8” from case for 10 s)
4
1 2
10.9
3
DPAK
CASE 369AA
(Bent Lead)
STYLE 2
1
2
2 3
3
IPAK
IPAK
CASE 369D
CASE 369AD
(Straight Lead) (Straight Lead
DPAK) STYLE 2
STYLE 2
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1
MARKING DIAGRAMS
& PIN ASSIGNMENTS
4
Drain
56
4
4
4
Drain
AYWW
48
58NG
Drain−to−Source Voltage
S
Symbol
AYWW
48
58NG
Parameter
4
Drain
AYWW
48
58NG
•
•
•
•
•
2
1 2 3
1 Drain 3
Gate Source Gate Drain Source 1 2 3
Gate Drain Source
A
Y
WW
4858N
G
= Assembly Location*
= Year
= Work Week
= Device Code
= Pb−Free Package
* The Assembly Location code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package, the front side assembly
code may be blank.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
May, 2019 − Rev. 3
1
Publication Order Number:
NTD4858N/D
NTD4858N
THERMAL RESISTANCE MAXIMUM RATINGS
Symbol
Value
Unit
Junction−to−Case (Drain)
Parameter
RqJC
2.75
°C/W
Junction−to−TAB (Drain)
RqJC−TAB
3.5
Junction−to−Ambient – Steady State (Note 1)
RqJA
73.5
Junction−to−Ambient – Steady State (Note 2)
RqJA
116
1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
25
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/
TJ
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate−to−Source Leakage Current
IDSS
V
22
VGS = 0 V,
VDS = 20 V
mV/°C
TJ = 25°C
1.0
TJ = 125°C
10
IGSS
VDS = 0 V, VGS = ±20 V
VGS(TH)
VGS = VDS, ID = 250 mA
mA
±100
nA
2.5
V
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
Negative Threshold Temperature
Coefficient
VGS(TH)/TJ
Drain−to−Source On Resistance
RDS(on)
Forward Transconductance
gFS
1.45
5.3
mV/°C
VGS = 10 V
ID = 30 A
5.2
6.2
VGS = 4.5 V
ID = 30 A
7.3
9.3
VDS = 1.5 V, ID = 15 A
55
mW
S
CHARGES AND CAPACITANCES
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
200
Total Gate Charge
QG(TOT)
12.8
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
Total Gate Charge
1563
VGS = 0 V, f = 1.0 MHz, VDS = 12 V
VGS = 4.5 V, VDS = 15 V, ID = 30 A
QGD
QG(TOT)
405
1.3
4.7
pF
19.2
nC
5.2
VGS = 10 V, VDS = 15 V, ID = 30 A
25.7
nC
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(ON)
tr
td(OFF)
12.6
VGS = 4.5 V, VDS = 15 V,
ID = 15 A, RG = 3.0 W
tf
20.2
16.4
ns
5.1
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
4. Switching characteristics are independent of operating junction temperatures.
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2
NTD4858N
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) (continued)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(ON)
tr
td(OFF)
7.7
VGS = 11.5 V, VDS = 15 V,
ID = 15 A, RG = 3.0 W
tf
17.3
ns
23.8
2.8
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
VSD
TJ = 25°C
0.87
TJ = 125°C
0.73
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V,
IS = 30 A
1.2
V
11.6
VGS = 0 V, dIS/dt = 100 A/ms,
IS = 30 A
7.8
ns
3.7
QRR
3.0
nC
Source Inductance
LS
2.49
nH
Drain Inductance, DPAK
LD
0.0164
Drain Inductance, IPAK
LD
Gate Inductance
LG
3.46
Gate Resistance
RG
0.7
PACKAGE PARASITIC VALUES
TA = 25°C
1.88
W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
4. Switching characteristics are independent of operating junction temperatures.
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3
NTD4858N
TYPICAL PERFORMANCE CURVES
90
3.8 V
90
TJ = 25°C
4V
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
80
3.6 V
70
60
3.4 V
50
40
3.2 V
30
20
3.0 V
10
2.8 V
0
1
2
3
4
40
30
TJ = 125°C
20
TJ = 25°C
10
TJ = −55°C
1
2
3
4
5
Figure 2. Transfer Characteristics
0.030
0.025
0.020
0.015
0.010
0.005
3
4
5
6
7
8
9
10
11
0.010
TJ = 25°C
0.009
VGS = 4.5 V
0.008
0.007
0.006
VGS = 11.5 V
0.005
0.004
0.003
0.002
10
20
30
40
50
60
70
80
90
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
1.8
10000
VGS = 0 V
ID = 30 A
VGS = 10 V
1000
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
50
Figure 1. On−Region Characteristics
0.035
1.6
60
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
ID = 30 A
TJ = 25°C
2
70
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0.040
0
VDS ≥ 10 V
80
0
5
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
10 V
1.4
1.2
1.0
0.8
0.6
−50
−25
0
25
50
75
100
125
150
175
TJ = 150°C
TJ = 125°C
100
10
1
0.1
TJ = 25°C
5
10
15
20
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Drain Voltage
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4
25
NTD4858N
2000
C, CAPACITANCE (pF)
VGS = 0 V
Ciss
1800
VGS , GATE−TO−SOURCE VOLTAGE (VOLTS)
TYPICAL PERFORMANCE CURVES
TJ = 25°C
1600
1400
1200
1000
Coss
800
600
400
200
0
0
Crss
2.5
5
7.5
10
12.5
15
17.5
20
DRAIN−TO−SOURCE VOLTAGE (VOLTS)
10
8
6
Q1
2
0
0
IS, SOURCE CURRENT (AMPS)
td(off)
tf
100
tr
td(on)
10
10
RG, GATE RESISTANCE (OHMS)
8
12
16
20
24
28
VGS = 0 V
25
20
15
10
5
100 ms
1 ms
VGS = 20 V
SINGLE PULSE
TC = 25°C
10 ms
dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1
0.7
0.8
0.9
Figure 10. Diode Forward Voltage vs. Current
10 ms
10
0.6
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
10
100
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
100
TJ = 25°C
0
0.5
100
1000
I D, DRAIN CURRENT (AMPS)
4
QG, TOTAL GATE CHARGE (nC)
Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
0.1
0.1
ID = 30 A
VDD = 15 V
TJ = 25°C
30
VDD = 15 V
ID = 30 A
VGS = 11.5 V
1
Q2
Figure 8. Gate−To−Source and Drain−To−Source
Voltage vs. Total Charge
1000
t, TIME (ns)
VGS
4
Figure 7. Capacitance Variation
1
1
QT
120
ID = 15 A
100
80
60
40
20
0
25
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
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5
175
NTD4858N
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
(NORMALIZED)
TYPICAL PERFORMANCE CURVES
1.0
D = 0.5
0.2
0.1
0.1
0.05
P(pk)
0.02
0.01
SINGLE PULSE
0.01
1.0E-05
1.0E-04
t1
t2
DUTY CYCLE, D = t1/t2
1.0E-03
1.0E-02
t, TIME (ms)
RqJC(t) = r(t) RqJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) RqJC(t)
1.0E-01
1.0E+00
1.0E+01
Figure 13. Thermal Response
ORDERING INFORMATION
Package
Shipping†
NTD4858NT4G
DPAK
(Pb−Free)
2500 / Tape & Reel
NTD4858N−1G
IPAK
(Pb−Free)
75 Units / Rail
NTD4858N−35G
IPAK Trimmed Lead
(3.5 ± 0.15 mm)
(Pb−Free)
75 Units / Rail
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
IPAK
CASE 369D−01
ISSUE C
SCALE 1:1
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
E
R
4
Z
A
S
1
2
3
−T−
SEATING
PLANE
K
J
F
D
G
DATE 15 DEC 2010
H
3 PL
0.13 (0.005)
M
DIM
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
0.155
−−−
MILLIMETERS
MIN
MAX
5.97
6.35
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.14
2.29 BSC
0.87
1.01
0.46
0.58
8.89
9.65
4.45
5.45
0.63
1.01
0.89
1.27
3.93
−−−
T
MARKING
DIAGRAMS
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
STYLE 5:
PIN 1. GATE
2. ANODE
3. CATHODE
4. ANODE
STYLE 6:
PIN 1. MT1
2. MT2
3. GATE
4. MT2
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 4:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
Discrete
YWW
xxxxxxxx
STYLE 7:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
xxxxxxxxx
A
lL
Y
WW
DOCUMENT NUMBER:
DESCRIPTION:
98AON10528D
Integrated
Circuits
xxxxx
ALYWW
x
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
IPAK (DPAK INSERTION MOUNT)
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DPAK (SINGLE GUAGE)
CASE 369AA−01
ISSUE B
4
1 2
DATE 03 JUN 2010
3
SCALE 1:1
A
E
b3
c2
B
Z
D
1
L4
A
4
L3
2
b2
H
DETAIL A
3
c
b
0.005 (0.13)
e
M
H
C
L2
GAUGE
PLANE
C
L
L1
DETAIL A
A1
ROTATED 905 CW
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 5:
PIN 1. GATE
2. ANODE
3. CATHODE
4. ANODE
STYLE 6:
PIN 1. MT1
2. MT2
3. GATE
4. MT2
STYLE 7:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 4:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
SOLDERING FOOTPRINT*
6.20
0.244
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
C
2.58
0.102
5.80
0.228
3.00
0.118
1.60
0.063
INCHES
MIN
MAX
0.086 0.094
0.000 0.005
0.025 0.035
0.030 0.045
0.180 0.215
0.018 0.024
0.018 0.024
0.235 0.245
0.250 0.265
0.090 BSC
0.370 0.410
0.055 0.070
0.108 REF
0.020 BSC
0.035 0.050
−−− 0.040
0.155
−−−
MILLIMETERS
MIN
MAX
2.18
2.38
0.00
0.13
0.63
0.89
0.76
1.14
4.57
5.46
0.46
0.61
0.46
0.61
5.97
6.22
6.35
6.73
2.29 BSC
9.40 10.41
1.40
1.78
2.74 REF
0.51 BSC
0.89
1.27
−−−
1.01
3.93
−−−
GENERIC
MARKING DIAGRAM*
XXXXXXG
ALYWW
YWW
XXX
XXXXXG
IC
Discrete
XXXXXX
A
L
Y
WW
G
6.17
0.243
SCALE 3:1
SEATING
PLANE
DIM
A
A1
b
b2
b3
c
c2
D
E
e
H
L
L1
L2
L3
L4
Z
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer
to device data sheet for actual part
marking.
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13126D
DPAK (SINGLE GAUGE)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
3.5 MM IPAK, STRAIGHT LEAD
CASE 369AD
ISSUE B
DATE 18 APR 2013
SCALE 1:1
E
E3
L2
E2
A1
D2
D
L1
L
T
SEATING
PLANE
NOTES:
1.. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2.. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30mm FROM TERMINAL TIP.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD GATE OR MOLD FLASH.
A
A1
b1
2X
e
A2
3X
E2
b
0.13
M
T
D2
DIM
A
A1
A2
b
b1
D
D2
E
E2
E3
e
L
L1
L2
MILLIMETERS
MIN
MAX
2.19
2.38
0.46
0.60
0.87
1.10
0.69
0.89
0.77
1.10
5.97
6.22
4.80
−−−
6.35
6.73
4.57
5.45
4.45
5.46
2.28 BSC
3.40
3.60
−−−
2.10
0.89
1.27
GENERIC MARKING
DIAGRAMS*
OPTIONAL
CONSTRUCTION
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
STYLE 5:
PIN 1. GATE
2. ANODE
3. CATHODE
4. ANODE
STYLE 6:
PIN 1. MT1
2. MT2
3. GATE
4. MT2
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 4:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
STYLE 7:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
Discrete
AYWW
XXX
XXXXXG
XXXXXX
A
L
Y
WW
G
Integrated
Circuits
XXXXXXG
ALYWW
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
DOCUMENT NUMBER:
DESCRIPTION:
98AON23319D
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