NTD4905N

NTD4905N Power MOSFET Features 30 V, 67 A, Single N−Channel, DPAK/IPAK • • • • Low RDS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses These are Pb−Free Devices http://onsemi.com V(BR)DSS 30 V RDS(on) MAX 4.5 mW @ 10 V 7.0 mW @ 4.5 V D ID MAX 67 A Applications • CPU Power Delivery • DC−DC Converters MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Parameter Drain−to−Source Voltage Gate−to−Source Voltage Continuous Drain Current (RqJA) (Note 1) Power Dissipation (RqJA) (Note 1) Continuous Drain Current (RqJA) (Note 2) Power Dissipation (RqJA) (Note 2) Continuous Drain Current (RqJC) (Note 1) Power Dissipation (RqJC) (Note 1) Pulsed Drain Current tp=10ms Current Limited by Package TA = 25°C TA = 100°C TA = 25°C TA = 25°C Steady State TA = 100°C TA = 25°C TC = 25°C TC = 100°C TC = 25°C TA = 25°C TA = 25°C PD IDM IDmaxPkg TJ, Tstg IS dV/dt EAS PD ID PD ID Symbol VDSS VGS ID Value 30 "20 16.3 11.5 2.63 12 8.3 1.4 66 47 44 264 90 − 55 to 175 40 6.5 61 W A A °C A V/ns mJ W A W A Unit V V A G S 4 4 12 N−Channel 4 3 1 CASE 369AA DPAK (Bent Lead) STYLE 2 2 3 CASE 369AD CASE 369D IPAK IPAK (Straight Lead) (Straight Lead DPAK) 23 1 MARKING DIAGRAMS & PIN ASSIGNMENTS 4 Drain YWW 49 05NG 4 Drain YWW 49 05NG 4 Drain Operating Junction and Storage Temperature Source Current (Body Diode) Drain to Source dV/dt Single Pulse Drain−to−Source Avalanche Energy (TJ = 25°C, VDD = 50 V, VGS = 10 V, L = 0.1 mH, IL(pk) = 35 A, RG = 25 W) Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) 2 1 23 1 Drain 3 Gate Source Gate Drain Source 1 2 3 Gate Drain Source Y WW 4905N G = Year = Work Week = Device Code = Pb−Free Package TL 260 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. © Semiconductor Components Industries, LLC, 2009 June, 2009 − Rev. 0 1 Publication Order Number: NTD4905N/D YWW 49 05NG NTD4905N THERMAL RESISTANCE MAXIMUM RATINGS Parameter Junction−to−Case (Drain) Junction−to−Tab (Drain) Junction−to−Ambient − Steady State (Note 1) Junction−to−Ambient − Steady State (Note 2) 1. Surface−mounted on FR4 board using 1 in sq pad size, 1 oz Cu. 2. Surface−mounted on FR4 board using the minimum recommended pad size. Symbol RqJC RqJC−TAB RqJA RqJA Value 3.4 4.3 57 109 Unit °C/W ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameter OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage Drain−to−Source Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current Gate−to−Source Leakage Current ON CHARACTERISTICS (Note 3) Gate Threshold Voltage Negative Threshold Temperature Coefficient Drain−to−Source On Resistance VGS(TH) VGS(TH)/TJ RDS(on) VGS = 10 V VGS = 4.5 V Forward Transconductance CHARGES AND CAPACITANCES Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Threshold Gate Charge Gate−to−Source Charge Gate−to−Drain Charge Total Gate Charge SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(on) tr td(off) tf td(on) tr td(off) tf VGS = 10 V, VDS = 15 V, ID = 15 A, RG = 3.0 W VGS = 4.5 V, VDS = 15 V, ID = 15 A, RG = 3.0 W 13.8 20.5 21.3 5.4 9.7 19.7 27.8 3.6 ns ns Ciss Coss Crss QG(TOT) QG(TH) QGS QGD QG(TOT) VGS = 10 V, VDS = 15 V, ID = 30 A VGS = 4.5 V, VDS = 15 V, ID = 30 A 2340 VGS = 0 V, f = 1.0 MHz, VDS = 15 V 763 27 14 3.7 6.8 2.2 33 nC nC pF gFS ID = 30 A ID = 15 A ID = 30 A ID = 15 A VDS = 1.5 V, ID = 30 A VGS = VDS, ID = 250 mA 1.0 1.6 4.0 3.9 3.9 5.4 5.4 65 S 7.0 4.5 2.2 V mV/°C mW V(BR)DSS V(BR)DSS/TJ IDSS IGSS VGS = 0 V, VDS = 24 V TJ = 25°C TJ = 125°C VGS = 0 V, ID = 250 mA 30 15 1.0 10 "100 nA V mV/°C mA Symbol Test Condition Min Typ Max Unit VDS = 0 V, VGS = "20 V 3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 NTD4905N ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameter DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage VSD tRR ta tb QRR LS LD LD LG RG TA = 25°C VGS = 0 V, dIs/dt= 100 A/ms, IS = 30 A VGS = 0 V, IS = 30 A TJ = 25°C TJ = 125°C 0.86 0.74 37.5 19 18.5 31 nC ns 1.1 V Symbol Test Condition Min Typ Max Unit Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Time PACKAGE PARASITIC VALUES Source Inductance (Note 5) Drain Inductance, DPAK Drain Inductance, IPAK (Note 5) Gate Inductance (Note 5) Gate Resistance 5. Assume terminal length of 110 mils. 2.85 0.0164 1.88 4.9 1.0 2.0 nH W http://onsemi.com 3 NTD4905N TYPICAL PERFORMANCE CURVES 110 100 ID, DRAIN CURRENT (AMPS) 90 80 70 60 50 40 30 20 10 0 110 ID, DRAIN CURRENT (AMPS) 4 V to 6 V TJ = 25°C 3.8 V 3.6 V 3.4 V 3.2 V 3.0 V 2.8 V 2.6 V 2.4 V 0 1 2 3 4 5 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 100 90 80 70 60 50 40 30 20 10 0 TJ = −55°C 2 2.5 3 3.5 4 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) TJ = 125°C TJ = 25°C VDS ≥ 10 V 10 V Figure 1. On−Region Characteristics RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0.015 0.013 0.011 0.009 0.007 0.005 0.003 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0.007 Figure 2. Transfer Characteristics ID = 30 A TJ = 25°C TJ = 25°C 0.006 VGS = 4.5 V 0.005 0.004 VGS = 10 V 3 4 5 6 7 8 9 10 0.003 20 30 40 50 60 70 80 90 100 110 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance vs. Gate−to−Source Voltage RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 −50 −25 10 0 25 50 75 100 125 150 175 5 10,000 ID = 30 A VGS = 10 V IDSS, LEAKAGE (nA) 1000 Figure 4. On−Resistance vs. Drain Current and Gate Voltage VGS = 0 V TJ = 150°C TJ = 125°C 100 TJ = 85°C 10 15 20 25 30 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Drain Voltage http://onsemi.com 4 NTD4905N TYPICAL PERFORMANCE CURVES 2800 2400 C, CAPACITANCE (pF) 2000 1600 1200 800 400 0 Crss 0 5 10 15 20 25 30 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Coss Ciss 12 11 10 9 8 7 6 5 4 3 2 1 0 QGS VGS QGD VDD = 15 V VGS = 10 V ID = 30 A TJ = 25°C 0 5 10 15 20 25 30 QG, TOTAL GATE CHARGE (nC) 35 40 TJ = 25°C VGS = 0 V VGS , GATE−TO−SOURCE VOLTAGE (VOLTS) QT 3600 3200 1000 Figure 7. Capacitance Variation Figure 8. Gate−To−Source and Drain−To−Source Voltage vs. Total Charge 30 IS, SOURCE CURRENT (AMPS) VGS = 0 V 25 20 15 10 5 0 0.4 TJ = 25°C 0.8 0.9 0.5 0.6 0.7 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) 1.0 TJ = 125°C td(off) tf tr td(on) VDD = 15 V ID = 15 A VGS = 10 V t, TIME (ns) 100 10 1 1 10 RG, GATE RESISTANCE (OHMS) 100 Figure 9. Resistive Switching Time Variation vs. Gate Resistance EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) 1000 I D, DRAIN CURRENT (AMPS) 70 60 50 40 30 20 10 0 25 Figure 10. Diode Forward Voltage vs. Current ID = 35 A 100 10 ms 10 100 ms VGS = 10 V SINGLE PULSE TC = 25°C RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 100 1 ms 10 ms dc 1 0.1 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) 175 Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 5 NTD4905N TYPICAL PERFORMANCE CURVES 100 50% (DUTY CYCLE) 20% 10% 5.0% 2.0% 1.0% 10 R(t) (C/W) 1.0 0.1 SINGLE PULSE 0.01 PSi TAB-A 0.001 0.000001 0.00001 0.0001 0.001 0.01 PULSE TIME (s) 0.1 1.0 10 100 1000 Figure 13. FET Thermal Response 90 80 70 60 GFS (S) 50 40 30 20 10 0 0 VDS = 1.5 V 10 20 30 50 40 ID (A) 60 70 80 90 Figure 14. GFS vs ID ORDERING INFORMATION Order Number NTD4905NT4G NTD4905N−1G NTD4905N−35G Package DPAK (Pb−Free) IPAK (Pb−Free) IPAK Trimmed Lead (Pb−Free) Shipping† 2500 / Tape & Reel 75 Units / Rail 75 Units / Rail †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 6 NTD4905N PACKAGE DIMENSIONS DPAK CASE 369AA−01 ISSUE A −T− B V R 4 SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.025 0.035 0.018 0.024 0.030 0.045 0.386 0.410 0.018 0.023 0.090 BSC 0.180 0.215 0.024 0.040 0.020 −−− 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.63 0.89 0.46 0.61 0.77 1.14 9.80 10.40 0.46 0.58 2.29 BSC 4.57 5.45 0.60 1.01 0.51 −−− 0.89 1.27 3.93 −−− C E S A 1 2 3 Z H U F L D 2 PL J DIM A B C D E F H J L R S U V Z 0.13 (0.005) M T SOLDERING FOOTPRINT* 6.20 0.244 3.0 0.118 2.58 0.101 5.80 0.228 1.6 0.063 6.172 0.243 SCALE 3:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 NTD4905N PACKAGE DIMENSIONS IPAK (STRAIGHT LEAD DPAK) CASE 369D−01 ISSUE B E Z DIM A B C D E F G H J K R S V Z B V R 4 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 −−− S −T− SEATING PLANE A 1 2 3 K F D G 3 PL J H M 0.13 (0.005) T STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN E L2 E3 3.5 MM IPAK, STRAIGHT LEAD CASE 369AD−01 ISSUE O A A1 E2 L1 D L b1 2X D2 NOTES: 1.. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2.. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD GATE OR MOLD FLASH. DIM A A1 A2 b b1 D D2 E E2 E3 e L L1 L2 MILLIMETERS MIN MAX 2.19 2.38 0.46 0.60 0.87 1.10 0.69 0.89 0.77 1.10 5.97 6.22 4.80 −−− 6.35 6.73 4.70 −−− 4.45 5.46 2.28 BSC 3.40 3.60 −−− 2.10 0.89 1.27 T SEATING PLANE A1 A2 3X e b 0.13 M E2 D2 T OPTIONAL CONSTRUCTION ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. 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