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Is Now
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www.onsemi.com
onsemi and and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or
subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi
product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without
notice. The information herein is provided “as-is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality,
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regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/
or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application
by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized
for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for
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subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative
Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. Other names and brands may be claimed as the property of others.
NTD4913N
Power MOSFET
30 V, 32 A, Single N−Channel, DPAK/IPAK
Features
•
•
•
•
Low RDS(on) to Minimize Conduction Losses
Low Capacitance to Minimize Driver Losses
Optimized Gate Charge to Minimize Switching Losses
These are Pb−Free Devices
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V(BR)DSS
RDS(ON) MAX
Applications
ID MAX
10.5 mW @ 10 V
• CPU Power Delivery
• DC−DC Converters
30 V
32 A
15 mW @ 4.5 V
D
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
30
V
Gate−to−Source Voltage
VGS
±20
V
ID
10.5
A
Continuous Drain
Current RqJA
(Note 1)
TA = 25°C
TA = 100°C
S
N−CHANNEL MOSFET
7.4
Power Dissipation
RqJA (Note 1)
TA = 25°C
PD
2.5
W
Continuous Drain
Current RqJA
(Note 2)
TA = 25°C
ID
7.7
A
TA = 25°C
4
5.4
PD
1.36
W
1 2
1
3
TC = 25°C
ID
TC = 100°C
Power Dissipation
RqJC (Note 1)
tp=10ms
Current Limited by Package
A
32
23
TC = 25°C
PD
24
W
TA = 25°C
IDM
132
A
TA = 25°C
IDmaxPkg
60
A
TJ,
TSTG
−55 to
+175
°C
Operating Junction and Storage
Temperature
Source Current (Body Diode)
IS
20
A
Drain to Source dV/dt
dV/dt
8.0
V/ns
Single Pulse Drain−to−Source Avalanche
Energy (TJ = 25°C, VDD = 50 V, VGS = 10 V,
IL = 21 Apk, L = 0.1 mH, RG = 25 W)
EAS
22
mJ
TL
260
°C
Lead Temperature for Soldering Purposes
(1/8” from case for 10 s)
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
CASE 369AA
DPAK
(Bent Lead)
STYLE 2
2 3
1
2
3
CASE 369AC
CASE 369D
3 IPAK
IPAK
(Straight Lead) (Straight Lead
DPAK)
MARKING DIAGRAMS
& PIN ASSIGNMENTS
4
Drain
4
Drain
AYWW
49
13NG
Continuous Drain
Current RqJC
(Note 1)
Pulsed Drain
Current
TA = 100°C
4
4
AYWW
49
13NG
Power Dissipation
RqJA (Note 2)
Steady
State
G
4
Drain
AYWW
49
13NG
Parameter
2
1 2 3
1 Drain 3
Gate Source Gate Drain Source 1 2 3
Gate Drain Source
A
Y
WW
4913N
G
= Assembly Location
= Year
= Work Week
= Device Code
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
May, 2014 − Rev. 2
1
Publication Order Number:
NTD4913N/D
NTD4913N
THERMAL RESISTANCE MAXIMUM RATINGS
Symbol
Value
Junction−to−Case (Drain)
Parameter
RqJC
6.2
Junction−to−TAB (Drain)
RqJC−TAB
4.3
Junction−to−Ambient – Steady State (Note 3)
RqJA
59
Junction−to−Ambient – Steady State (Note 4)
RqJA
110
Unit
°C/W
3. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.
4. Surface−mounted on FR4 board using the minimum recommended pad size.
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
30
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/
TJ
Parameter
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate−to−Source Leakage Current
IDSS
V
15
VGS = 0 V,
VDS = 24 V
mV/°C
TJ = 25 °C
1
TJ = 125°C
10
IGSS
VDS = 0 V, VGS = ±20 V
VGS(TH)
VGS = VDS, ID = 250 mA
mA
±100
nA
2.2
V
ON CHARACTERISTICS (Note 5)
Gate Threshold Voltage
Negative Threshold Temperature
Coefficient
VGS(TH)/TJ
Drain−to−Source On Resistance
RDS(on)
VGS = 10 V
gFS
1.67
4.0
VGS = 4.5 V
Forward Transconductance
1.0
ID = 30 A
8.2
ID = 15 A
8.2
ID = 30 A
12.5
ID = 15 A
12.5
VDS = 1.5 V, ID = 30 A
39
mV/°C
10.5
15
mW
S
CHARGES AND CAPACITANCES
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
12.5
Total Gate Charge
QG(TOT)
6.2
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
Total Gate Charge
QG(TOT)
1013
VGS = 0 V, f = 1.0 MHz, VDS = 15 V
370
pF
1.7
VGS = 4.5 V, VDS = 15 V; ID = 30 A
3.7
nC
0.9
VGS = 10 V, VDS = 15 V;
ID = 30 A
13
nC
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(ON)
tr
td(OFF)
10
VGS = 4.5 V, VDS = 15 V,
ID = 15 A, RG = 3.0 W
tf
21
14.7
ns
2.3
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
7. Assume terminal length of 110 mils.
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2
NTD4913N
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SWITCHING CHARACTERISTICS (Note 6)
Turn−On Delay Time
Rise Time
td(ON)
tr
Turn−Off Delay Time
Fall Time
td(OFF)
7.1
VGS = 10 V, VDS = 15 V,
ID = 15 A, RG = 3.0 W
tf
18
ns
19
1.7
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
VSD
TJ = 25°C
0.92
TJ = 125°C
0.70
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V,
IS = 30 A
1.1
V
26
VGS = 0 V, dIs/dt = 100 A/ms,
IS = 30 A
14
ns
12
QRR
15
nC
Source Inductance (Note 7)
LS
2.99
nH
Drain Inductance, DPAK
LD
0.0164
Drain Inductance, IPAK (Note 7)
LD
Gate Inductance (Note 7)
LG
4.9
Gate Resistance
RG
1.0
PACKAGE PARASITIC VALUES
TA = 25°C
1.88
2.0
W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
6. Switching characteristics are independent of operating junction temperatures.
7. Assume terminal length of 110 mils.
ORDERING INFORMATION
Package
Shipping†
NTD4913NT4G
DPAK
(Pb−Free)
2500 / Tape & Reel
NTD4913N−1G
DPAK−3
(Pb−Free)
75 Units / Rail
NTD4913N−35G
IPAK Trimmed Lead
(3.5 ±0.15 mm)
(Pb−Free)
75 Units / Rail
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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3
NTD4913N
TYPICAL CHARACTERISTICS
10 V
50
7V
ID, DRAIN CURRENT (A)
45
VGS = 3.8 V
5.0
4.5
40
55
4.0 V
3.4 V
35
30
3.2 V
25
3.0 V
20
15
2.8 V
10
2.6 V
2.4 V
5
0
0
1
2
3
40
35
30
25
15
TJ = −55°C
2.0
2.5
3.0
3.5
4.0
4.5
VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
ID = 30 A
TJ = 25°C
0.022
0.020
0.018
0.016
0.014
0.012
0.010
0.008
4.0
5.0
6.0
7.0
8.0
9.0
VGS (V)
10
0.015
0.014
TJ = 25°C
0.013
VGS = 4.5 V
0.012
0.011
0.010
0.009
VGS = 10 V
0.008
0.007
0.006
0.005
0.004
15
20
25
30
35
40
45
50
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. VGS
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
2.2
10,000
VGS = 0 V
ID = 30 A
VGS = 10 V
1.8
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
TJ = 125°C
10
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
0.024
2.0
TJ = 25°C
20
4
0.026
3.0
VDS = 10 V
45
5
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
50
TJ = 25°C
3.6 V
ID, DRAIN CURRENT (A)
55
1.6
1.4
1.2
1.0
TJ = 150°C
1000
TJ = 125°C
100
TJ = 85°C
0.8
0.6
−50 −25
10
0
25
50
75
100
125
150
175
5
10
15
20
25
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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4
30
NTD4913N
C, CAPACITANCE (pF)
1400
VGS, GATE−TO−SOURCE VOLTAGE (V)
TYPICAL CHARACTERISTICS
VGS = 0 V
TJ = 25°C
1200
Ciss
1000
800
600
Coss
400
200
Crss
0
0
5
10
15
20
25
15.0
13.5
9.0
7.5
Qgd
6.0
Qgs
4.5
VDD = 15 V
VGS = 10 V
ID = 30 A
3.0
1.5
0
30
1
0
2
3
4
5
6
7
8
9 10 11 12 13 14 15
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Qg, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
30
VGS = 0 V
100
IS, SOURCE CURRENT (A)
VDD = 15 V
ID = 15 A
VGS = 10 V
t, TIME (ns)
QT
10.5
1000
td(off)
tf
tr
td(on)
10
25
20
15
TJ = 125°C
10
5
TJ = 25°C
0
1
1
10
0
100
0.2
0.4
0.6
0.8
1.0
1.2
RG, GATE RESISTANCE (W)
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
EAS, SINGLE PULSE DRAIN−TO−
SOURCE AVALANCHE ENERGY (mJ)
1000
ID, DRAIN CURRENT (A)
TJ = 25°C
12.0
100
10 ms
10
100 ms
1 ms
VGS = 10 V
Single Pulse
TC = 25°C
RDS(on) Limit
Thermal Limit
Package Limit
1
0.1
0.1
10 ms
dc
1
10
25
ID = 21 A
20
15
10
5
0
25
100
50
75
100
125
150
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
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5
175
NTD4913N
TYPICAL CHARACTERISTICS
100
R(t) (°C/W)
10
Duty Cycle = 50%
20%
10%
5%
2%
1
1%
0.1
Single Pulse
0.01
Psi Tab−A
0.000001
0.00001
0.0001
0.001
0.1
0.01
1
10
PULSE TIME (sec)
Figure 13. FET Thermal Response
45
40
VDS = 1.5 V
35
30
GFS (S)
0.001
25
20
15
10
5
0
0
5
10
15
20
25
ID (A)
Figure 14. GFS vs. ID
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6
30
35
40
100
1000
NTD4913N
PACKAGE DIMENSIONS
DPAK (SINGLE GUAGE)
CASE 369AA
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
C
A
A
E
b3
c2
B
4
L3
Z
D
1
2
H
DETAIL A
3
DIM
A
A1
b
b2
b3
c
c2
D
E
e
H
L
L1
L2
L3
L4
Z
L4
b2
e
c
b
0.005 (0.13)
M
C
H
L2
GAUGE
PLANE
C
L
SEATING
PLANE
A1
L1
DETAIL A
ROTATED 905 CW
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
SOLDERING FOOTPRINT*
6.20
0.244
2.58
0.102
5.80
0.228
3.00
0.118
1.60
0.063
INCHES
MIN
MAX
0.086 0.094
0.000 0.005
0.025 0.035
0.030 0.045
0.180 0.215
0.018 0.024
0.018 0.024
0.235 0.245
0.250 0.265
0.090 BSC
0.370 0.410
0.055 0.070
0.108 REF
0.020 BSC
0.035 0.050
−−− 0.040
0.155
−−−
6.17
0.243
SCALE 3:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
7
MILLIMETERS
MIN
MAX
2.18
2.38
0.00
0.13
0.63
0.89
0.76
1.14
4.57
5.46
0.46
0.61
0.46
0.61
5.97
6.22
6.35
6.73
2.29 BSC
9.40 10.41
1.40
1.78
2.74 REF
0.51 BSC
0.89
1.27
−−−
1.01
3.93
−−−
NTD4913N
PACKAGE DIMENSIONS
3 IPAK, STRAIGHT LEAD
CASE 369AC
ISSUE O
B
V
NOTES:
1.. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2.. CONTROLLING DIMENSION: INCH.
3. SEATING PLANE IS ON TOP OF
DAMBAR POSITION.
4. DIMENSION A DOES NOT INCLUDE
DAMBAR POSITION OR MOLD GATE.
C
E
R
DIM
A
B
C
D
E
F
G
H
J
K
R
V
W
A
SEATING PLANE
K
W
F
J
G
H
D
3 PL
0.13 (0.005) W
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.043
0.090 BSC
0.034 0.040
0.018 0.023
0.134 0.142
0.180 0.215
0.035 0.050
0.000 0.010
MILLIMETERS
MIN
MAX
5.97
6.22
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.09
2.29 BSC
0.87
1.01
0.46
0.58
3.40
3.60
4.57
5.46
0.89
1.27
0.000
0.25
IPAK
CASE 369D
ISSUE C
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
E
R
4
Z
A
S
1
2
3
−T−
SEATING
PLANE
K
J
F
H
D
G
DIM
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
0.155
−−−
MILLIMETERS
MIN
MAX
5.97
6.35
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.14
2.29 BSC
0.87
1.01
0.46
0.58
8.89
9.65
4.45
5.45
0.63
1.01
0.89
1.27
3.93
−−−
3 PL
0.13 (0.005)
M
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
T
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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For additional information, please contact your local
Sales Representative
NTD4913N/D
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