NTD5414N, NVD5414N
Power MOSFET
24 A, 60 V Single N−Channel DPAK
Features
•
•
•
•
•
Low RDS(on)
High Current Capability
Avalanche Energy Specified
NVD Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
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V(BR)DSS
RDS(ON) MAX
60 V
37 mW @ 10 V
Applications
•
•
•
•
ID MAX
(Note 1)
24 A
N−Channel
LED Lighting and LED Backlight Drivers
DC−DC Converters
DC Motor Drivers
Power Supplies Secondary Side Synchronous Rectification
D
G
MAXIMUM RATINGS (TJ = 25°C Unless otherwise specified)
Parameter
S
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
60
V
Gate−to−Source Voltage − Continuous
VGS
$20
V
Gate−to−Source Voltage − Nonrepetitive
(TP < 10 ms)
VGS
$30
V
3
A
DPAK
CASE 369AA
STYLE 2
Continuous Drain
Current RqJC
(Note 1)
Steady
State
Power Dissipation
RqJC (Note 1)
Steady
State
TC = 25°C
ID
TC = 100°C
24
4
1 2
16
55
W
MARKING DIAGRAMS
& PIN ASSIGNMENT
IDM
75
A
TJ, Tstg
−55 to
+175
°C
4
Drain
IS
24
A
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 50 Vdc, VGS = 10 V, IL(pk) = 24 A,
L = 0.3 mH, RG = 25 W)
EAS
86.4
mJ
Lead Temperature for Soldering
Purposes, 1/8″ from Case for 10 Seconds
TL
Pulsed Drain Current
tp = 10 ms
Operating and Storage Temperature Range
Source Current (Body Diode)
2
1
3
Drain
Gate
Source
°C
260
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL RESISTANCE RATINGS
Parameter
Junction−to−Case (Drain) Steady State
(Note 1)
Symbol
Max
Unit
RqJC
2.7
°C/W
RqJA
58.6
August, 2014 − Rev. 2
A
Y
WW
5414N
G
= Assembly Location*
= Year
= Work Week
= Specific Device Code
= Pb−Free Device
* The Assembly Location code (A) is front side
optional. In cases where the Assembly Location is
stamped in the package, the front side assembly
code may be blank.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
1. Surface mounted on FR4 board using 1 sq in pad size,
(Cu Area 1.127 sq in [1 oz] including traces).
© Semiconductor Components Industries, LLC, 2014
AYWW
54
14NG
PD
TC = 25°C
1
Publication Order Number:
NTD5414N/D
NTD5414N, NVD5414N
ELECTRICAL CHARACTERISTICS (TJ = 25°C Unless otherwise specified)
Characteristics
Symbol
Test Condition
Min
V(BR)DSS
VDS = 0 V, ID = 250 mA
60
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
Drain−to−Source Breakdown Voltage Temperature Coefficient
Zero Gate Voltage Drain Current
Gate−Body Leakage Current
V(BR)DSS/TJ
IDSS
V
67.3
VGS = 0 V
VDS = 60 V
mV/°C
TJ = 25°C
1.0
TJ = 150°C
50
IGSS
VDS = 0 V, VGS = $20 V
VGS(th)
VGS = VDS, ID = 250 mA
$100
mA
nA
ON CHARACTERISTICS (Note 2)
Gate Threshold Voltage
Negative Threshold Temperature Coefficient
VGS(th)/TJ
2.0
3.2
Drain−to−Source On−Voltage
VDS(on)
VGS = 10 V, ID = 12 A, 150°C
0.7
Drain−to−Source On−Resistance
RDS(on)
VGS = 10 V, ID = 24 A
28.4
gFS
VDS = 15 V, ID = 20 A
24
Input Capacitance
Ciss
800
Output Capacitance
Coss
VDS = 25 V, VGS = 0 V,
f = 1 MHz
Forward Transconductance
4.0
0.74
VGS = 10 V, ID = 24 A
0.7
V
mV/°C
1.16
V
37
mW
S
CHARGES, CAPACITANCES & GATE RESISTANCE
Transfer Capacitance
Crss
1200
pF
48
nC
165
75
VGS = 10 V, VDS = 48 V,
ID = 24 A
Total Gate Charge
QG(TOT)
25
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
4.8
Gate−to−Drain Charge
QGD
11.3
1.1
SWITCHING CHARACTERISTICS, VGS = 10 V (Note 3)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(on)
tr
VGS = 10 V, VDD = 48 V,
ID = 24 A, RG = 9.1 W
ns
12
58
td(off)
47
tf
69
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage (Note 2)
VSD
VGS = 0 V
IS = 24 A
TJ = 25°C
0.92
TJ = 125°C
0.8
IS = 24 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/ms
Reverse Recovery Time
trr
Charge Time
ta
Discharge Time
tb
14
QRR
76
Reverse Recovery Stored Charge
45.7
1.15
V
ns
31.7
nC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
3. Switching characteristics are independent of operating junction temperatures.
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2
NTD5414N, NVD5414N
TYPICAL PERFORMANCE CURVES
40
40
10 V
TJ = 25°C
6V
7V
25
20
5V
15
4.8 V
10
4.5 V
1
2
3
4
30
25
20
TJ = 125°C
15
10
TJ = 25°C
5
VGS = 4.2 V
0
0
TJ = −55°C
0
5
2
3
4
5
6
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
VGS, GATE−TO−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.08
ID = 24 A
TJ = 25°C
0.07
0.06
0.05
0.04
0.03
0.02
5
6
7
8
9
10
0.040
TJ = 25°C
VGS = 10 V
0.030
0.020
0.010
10
15
25
20
35
30
40
45
VGS, GATE−TO−SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
1000
2.5
VGS = 0 V
ID = 24 A
VGS = 10 V
TJ = 150°C
2.0
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
ID, DRAIN CURRENT (A)
5.5 V
30
5
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
VDS ≥ 10 V
35
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
ID, DRAIN CURRENT (A)
35
1.5
1.0
0.5
−50
−25
0
25
50
75
100
125
150
175
100
TJ = 125°C
10
5
10
15
20
25
30
35
40
45
50
55 60
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
NTD5414N, NVD5414N
VGS = 0 V
TJ = 25°C
1500
C, CAPACITANCE (pF)
VGS, GATE−TO−SOURCE VOLTAGE (V)
TYPICAL PERFORMANCE CURVES
1000
Ciss
500
Coss
Crss
0
0
10
20
30
40
50
10
QT
8
Q1
6
Q2
4
2
ID = 24 A
TJ = 25°C
0
0
60
5
Figure 7. Capacitance Variation
IS, SOURCE CURRENT (A)
100
t, TIME (ns)
20
25
25
VDD = 48 V
ID = 24 A
VGS = 10 V
tf
td(off)
tr
td(on)
10
1
10
VGS = 0 V
TJ = 25°C
20
15
10
5
0
0.4
1
100
0.5
0.6
0.7
0.8
0.9
1.0
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
RG, GATE RESISTANCE (W)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
90
0 V ≤ VGS ≤ 10 V
Single Pulse
TC = 25°C
1 ms
100 ms
10 ms
10 ms
dc
10
1
RDS(on) Limit
Thermal Limit
Package Limit
0.1
0.1
ID = 24 A
80
AVALANCHE ENERGY (mJ)
ID, DRAIN CURRENT (A)
15
Figure 8. Gate−to−Source Voltage vs. Total
Charge
1000
100
10
Qg, TOTAL GATE CHARGE (nC)
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
1
10
70
60
50
40
30
20
10
0
25
100
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
50
75
100
125
150
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
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4
175
NTD5414N, NVD5414N
TYPICAL PERFORMANCE CURVES
100
D = 0.5
10
r(t), (°C/W)
1
0.2
0.1
0.05
0.02
0.01
0.1
0.01
Single Pulse
Surface−Mounted on FR4 Board using 1 sq in pad size, 1 oz Cu
0.001
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
t, PULSE TIME (s)
Figure 13. Thermal Response
ORDERING INFORMATION
Package
Shipping†
NTD5414NT4G
DPAK
(Pb−Free)
2500 / Tape & Reel
NVD5414NT4G*
DPAK
(Pb−Free)
2500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NVD Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP
Capable.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DPAK (SINGLE GUAGE)
CASE 369AA−01
ISSUE B
4
1 2
DATE 03 JUN 2010
3
SCALE 1:1
A
E
b3
c2
B
Z
D
1
L4
A
4
L3
2
b2
H
DETAIL A
3
c
b
0.005 (0.13)
e
M
H
C
L2
GAUGE
PLANE
C
L
L1
DETAIL A
A1
ROTATED 905 CW
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 5:
PIN 1. GATE
2. ANODE
3. CATHODE
4. ANODE
STYLE 6:
PIN 1. MT1
2. MT2
3. GATE
4. MT2
STYLE 7:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 4:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
SOLDERING FOOTPRINT*
6.20
0.244
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
C
2.58
0.102
5.80
0.228
3.00
0.118
1.60
0.063
INCHES
MIN
MAX
0.086 0.094
0.000 0.005
0.025 0.035
0.030 0.045
0.180 0.215
0.018 0.024
0.018 0.024
0.235 0.245
0.250 0.265
0.090 BSC
0.370 0.410
0.055 0.070
0.108 REF
0.020 BSC
0.035 0.050
−−− 0.040
0.155
−−−
MILLIMETERS
MIN
MAX
2.18
2.38
0.00
0.13
0.63
0.89
0.76
1.14
4.57
5.46
0.46
0.61
0.46
0.61
5.97
6.22
6.35
6.73
2.29 BSC
9.40 10.41
1.40
1.78
2.74 REF
0.51 BSC
0.89
1.27
−−−
1.01
3.93
−−−
GENERIC
MARKING DIAGRAM*
XXXXXXG
ALYWW
YWW
XXX
XXXXXG
IC
Discrete
XXXXXX
A
L
Y
WW
G
6.17
0.243
SCALE 3:1
SEATING
PLANE
DIM
A
A1
b
b2
b3
c
c2
D
E
e
H
L
L1
L2
L3
L4
Z
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer
to device data sheet for actual part
marking.
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13126D
DPAK (SINGLE GAUGE)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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