NTD78N03-035

NTD78N03 Power MOSFET 25 V, 78 A, Single N−Channel, DPAK Features • Low RDS(on) • Optimized Gate Charge • Pb−Free Packages are Available http://onsemi.com V(BR)DSS Applications • Desktop VCORE • DC−DC Converters • Low Side Switch RDS(on) TYP ID MAX 4.6 @ 10 V 25 V 78 A 6.5 @ 4.5 V D MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Parameter Drain−to−Source Voltage Gate−to−Source Voltage Continuous Drain Current (Note 1) TC = 25°C Power Dissipation (Note 1) TC = 25°C Unit 25 V VGS "20 V ID 14.8 A TC = 85°C N−Channel G S 11.5 PD 2.3 4 W 4 4 ID TC = 85°C A 11.4 1 2 8.8 TC = 25°C PD 1.4 W Continuous Drain Current (RqJC) TC = 25°C ID 78 A Power Dissipation (RqJC) TC = 25°C Pulsed Drain Current Current Limited by Package TC = 85°C tp = 10 ms TA = 25°C Drain to Source dV/dt Operating Junction and Storage Temperature Source Current (Body Diode) 56 PD 64 W IDM 210 A IDmaxPkg 45 A dV/dt 8.0 V/ns TJ, Tstg −55 to 175 °C IS 78 A Single Pulse Drain−to−Source Avalanche Energy (VDD = 24 V, VGS = 10 V, L = 5.0 mH, IL(pk) = 17 A, RG = 25 W) EAS 722.5 mJ Lead Temperature for Soldering Purposes (1/8″ from case for 10 seconds) TL 260 °C Junction−to−Case (Drain) RqJC 1.95 °C/W Junction−to−Ambient − Steady State (Note 1) RqJA 65 Junction−to−Ambient − Steady State (Note 2) RqJA 110 THERMAL RESISTANCE Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface−mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces). 2. Surface−mounted on FR4 board using the minimum recommended pad size. © Semiconductor Components Industries, LLC, 2006 September, 2006 − Rev. 6 1 1 3 1 2 3 CASE 369AA CASE 369D DPAK DPAK (Bend Lead) (Straight Lead) STYLE 2 STYLE 2 2 3 CASE 369AD IPAK (Straight Lead) MARKING DIAGRAMS & PIN ASSIGNMENTS 4 Drain 4 Drain 4 Drain YWW 78 N03G TC = 25°C Steady State YWW 78 N03G Power Dissipation (Note 2) Value VDSS YWW 78 N03G Continuous Drain Current (Note 2) Symbol 2 1 2 3 1 Drain 3 Gate Source Gate Drain Source 1 2 3 Gate Drain Source Y WW 78N03 G = Year = Work Week = Device Code = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. Publication Order Number: NTD78N03/D NTD78N03 ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 25 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ Parameter Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current Gate−to−Source Leakage Current IDSS V 24 VGS = 0 V, VDS = 20 V mV/°C TJ = 25°C 1.5 TJ = 125°C 10 IGSS VDS = 0 V, VGS = "20 V VGS(TH) VGS = VDS, ID = 250 mA mA "100 nA 3.0 V ON CHARACTERISTICS (Note 3) Gate Threshold Voltage Negative Threshold Temperature Coefficient Drain−to−Source On Resistance Forward Transconductance VGS(TH)/TJ 1.0 1.6 −5.0 RDS(on) mV/°C VGS = 10 V, ID = 78 A 4.6 6.0 VGS = 4.5 V, ID = 36 A 6.5 7.8 VDS = 10 V, ID = 15 A 22 gFS mW S CHARGES, CAPACITANCES AND GATE RESISTANCE Input Capacitance Ciss 1920 VGS = 0 V, f = 1.0 MHz, VDS = 12 V Output Capacitance Coss Reverse Transfer Capacitance Crss 420 Total Gate Charge QG(TOT) 25.5 Threshold Gate Charge QG(TH) Gate−to−Source Charge QGS Gate−to−Drain Charge QGD VGS = 4.5 V, VDS = 20 V, ID = 20 A 2250 960 pF 35 2.4 nC 5.3 18.2 SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(on) 11 tr 68 td(off) VGS = 4.5 V, VDS = 20 V, ID = 20 A, RG = 3.0 W tf ns 23 42 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage VSD Reverse Recovery Time tRR Charge Time ta Discharge Time tb Reverse Recovery Time VGS = 0 V, IS = 20 A TJ = 25°C 0.83 TJ = 125°C 0.7 1.0 V 39 VGS = 0 V, dIs/dt = 100 A/ms, IS = 20 A 17.8 ns 21 QRR 33 Source Inductance LS 2.49 Drain Inductance LD nC PACKAGE PARASITIC VALUES 0.02 Ta = 25C Gate Inductance LG 3.46 Gate Resistance RG 1.0 3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 nH W NTD78N03 100 VGS = 4 V 80 3.8 V 4.5 V 5V 3.6 V 9V 3.4 V 70 60 50 3.2 V 40 30 3V 20 TJ = 25°C 10 2.6 V 0 0 4 2 6 8 10 Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics 0.01 VGS = 10 V 0.008 TJ = 125°C 0.007 0.006 TJ = 25°C 0.005 0.004 0.003 TJ = −55°C 0.002 20 30 40 50 60 70 80 TJ = 25°C 0.01 VGS = 4.5 V VGS = 10 V 0.005 0 55 60 65 70 75 80 ID, DRAIN CURRENT (A) Figure 3. On−Resistance versus Drain Current and Temperature Figure 4. On−Resistance versus Drain Current and Gate Voltage 3 2.5 0.015 ID, DRAIN CURRENT (A) 100000 VGS = 0 V ID = 78 A VDS = 4.5 V 10000 IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 0.001 6 5 VGS, GATE−TO−SOURCE VOLTAGE (V) 0.009 0 10 160 150 VDS ≥ 10 V 140 130 120 110 100 90 80 70 60 50 TJ = 125°C 40 30 TJ = 25°C 20 TJ = −55°C 10 0 1 2 0 3 4 VDS, DRAIN−TO−SOURCE VOLTAGE (V) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) 90 2 1.5 1 TJ = 150°C TJ = 125°C 1000 100 0.5 0 −50 −25 0 25 50 75 100 125 150 175 10 5 10 15 20 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−To−Source Leakage Current versus Voltage http://onsemi.com 3 25 VDS = 0 V VGS = 0 V TJ = 25°C C, CAPACITANCE (pF) 5000 Ciss 4000 Crss 3000 2000 Ciss 1000 Coss 0 10 Crss 5 VGS 0 VDS 5 10 15 20 25 8 20 QT VDS 15 6 VGS 4 10 Q2 Q1 5 2 ID = 20 A TJ = 25°C 0 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 6000 VGS, GATE−TO−SOURCE VOLTAGE (V) NTD78N03 0 5 10 15 20 25 30 0 35 Qg, TOTAL GATE CHARGE (nC) GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V) Figure 8. Gate−to−Source and Drain−to−Source Voltage versus Total Charge Figure 7. Capacitance Variation 80 1000 t, TIME (ns) 100 IS, SOURCE CURRENT (AMPS) VDS = 20 V ID = 20 A VGS = 4.5 V tr tf td(off) td(on) 10 10 RG, GATE RESISTANCE (OHMS) 100 Figure 9. Resistive Switching Time Variation versus Gate Resistance EAS, SINGLE PULSE DRAIN−TO− SOURCE AVALANCHE ENERGY (mJ) I D, DRAIN CURRENT (AMPS) 10 ms 100 100 ms 1 ms VGS = 20 V SINGLE PULSE TC = 25°C 1 10 ms dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 0.1 50 40 30 20 10 0.6 0.7 0.8 0.9 1.0 1.1 VSD, SOURCE−TO−DRAIN VOLTAGE (V) 1.2 Figure 10. Diode Forward Voltage versus Current 1000 10 60 0 0.5 1 1 VGS = 0 V 70 T = 25°C J 1 10 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 100 Figure 11. Maximum Rated Forward Biased Safe Operating Area 800 ID = 78 A 700 600 500 400 300 200 100 0 25 50 75 100 125 150 TJ, STARTING JUNCTION TEMPERATURE (°C) 175 Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 4 NTD78N03 di/dt IS trr ta tb TIME 0.25 IS tp IS Figure 13. Diode Reverse Recovery Waveform Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE 1000 MOUNTED TO MINIMUM RECOMMENDED FOOTPRINT DUTY CYCLE 100 D = 0.5 0.2 0.1 0.05 0.02 0.01 10 1 P(pk) t1 0.1 t2 DUTY CYCLE, D = t1/t2 SINGLE PULSE RqJA(t) = r(t) RqJA D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TA = P(pk) RqJA(t) 0.01 1E−05 1E−04 1E−03 1E−02 1E−01 t, TIME (seconds) 1E+00 1E+01 1E+02 1E+03 Figure 14. Thermal Response − Various Duty Cycles ORDERING INFORMATION Package Shipping † DPAK 75 Units/Rail NTD78N03G DPAK (Pb−Free) 75 Units/Rail NTD78N03T4 DPAK Order Number NTD78N03 NTD78N03T4G DPAK (Pb−Free) NTD78N03−1 DPAK Straight Lead NTD78N03−1G DPAK Straight Lead (Pb−Free) NTD78N03−35 DPAK−3 Straight Lead (3.5 " 0.15 mm) NTD78N03−35G DPAK−3 Straight Lead (3.5 " 0.15 mm) (Pb−Free) 2500 Tape & Reel 75 Units/Rail 75 Units/Rail †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 5 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS IPAK CASE 369D−01 ISSUE C SCALE 1:1 C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. E R 4 Z A S 1 2 3 −T− SEATING PLANE K J F D G DATE 15 DEC 2010 H 3 PL 0.13 (0.005) M DIM A B C D E F G H J K R S V Z INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 −−− T MARKING DIAGRAMS STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE Discrete YWW xxxxxxxx STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR xxxxxxxxx A lL Y WW DOCUMENT NUMBER: DESCRIPTION: 98AON10528D Integrated Circuits xxxxx ALYWW x = Device Code = Assembly Location = Wafer Lot = Year = Work Week Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. IPAK (DPAK INSERTION MOUNT) PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DPAK (SINGLE GUAGE) CASE 369AA−01 ISSUE B 4 1 2 DATE 03 JUN 2010 3 SCALE 1:1 A E b3 c2 B Z D 1 L4 A 4 L3 2 b2 H DETAIL A 3 c b 0.005 (0.13) e M H C L2 GAUGE PLANE C L L1 DETAIL A A1 ROTATED 905 CW STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE SOLDERING FOOTPRINT* 6.20 0.244 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE. 5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY. 6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H. C 2.58 0.102 5.80 0.228 3.00 0.118 1.60 0.063 INCHES MIN MAX 0.086 0.094 0.000 0.005 0.025 0.035 0.030 0.045 0.180 0.215 0.018 0.024 0.018 0.024 0.235 0.245 0.250 0.265 0.090 BSC 0.370 0.410 0.055 0.070 0.108 REF 0.020 BSC 0.035 0.050 −−− 0.040 0.155 −−− MILLIMETERS MIN MAX 2.18 2.38 0.00 0.13 0.63 0.89 0.76 1.14 4.57 5.46 0.46 0.61 0.46 0.61 5.97 6.22 6.35 6.73 2.29 BSC 9.40 10.41 1.40 1.78 2.74 REF 0.51 BSC 0.89 1.27 −−− 1.01 3.93 −−− GENERIC MARKING DIAGRAM* XXXXXXG ALYWW YWW XXX XXXXXG IC Discrete XXXXXX A L Y WW G 6.17 0.243 SCALE 3:1 SEATING PLANE DIM A A1 b b2 b3 c c2 D E e H L L1 L2 L3 L4 Z = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON13126D DPAK (SINGLE GAUGE) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS 3.5 MM IPAK, STRAIGHT LEAD CASE 369AD ISSUE B DATE 18 APR 2013 SCALE 1:1 E E3 L2 E2 A1 D2 D L1 L T SEATING PLANE NOTES: 1.. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2.. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD GATE OR MOLD FLASH. A A1 b1 2X e A2 3X E2 b 0.13 M T D2 DIM A A1 A2 b b1 D D2 E E2 E3 e L L1 L2 MILLIMETERS MIN MAX 2.19 2.38 0.46 0.60 0.87 1.10 0.69 0.89 0.77 1.10 5.97 6.22 4.80 −−− 6.35 6.73 4.57 5.45 4.45 5.46 2.28 BSC 3.40 3.60 −−− 2.10 0.89 1.27 GENERIC MARKING DIAGRAMS* OPTIONAL CONSTRUCTION STYLE 1: PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 5: PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE STYLE 6: PIN 1. MT1 2. MT2 3. GATE 4. MT2 STYLE 3: PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE STYLE 4: PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE STYLE 7: PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR Discrete AYWW XXX XXXXXG XXXXXX A L Y WW G Integrated Circuits XXXXXXG ALYWW = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. DOCUMENT NUMBER: DESCRIPTION: 98AON23319D Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 3.5 MM IPAK, STRAIGHT LEAD PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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