NTD78N03R-35G

NTD78N03R Power MOSFET Features 25 V, 85 A, Single N−Channel, DPAK • Low RDS(on) to Minimize Conduction Losses • Optimized Gate Charge to Minimize Switching Losses • Pb−Free Packages are Available Applications http://onsemi.com V(BR)DSS 25 V RDS(on) TYP 5.0 @ 11.5 V 7.5 @ 4.5 V D ID MAX 85 A • VCORE Applications • DC−DC Converters • Optimized for Low Side Switching MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Parameter Drain−to−Source Voltage Gate−to−Source Voltage Continuous Drain Current (RqJA) (Note 1) Power Dissipation (RqJA) (Note 1) Continuous Drain Current (RqJA) (Note 2) Power Dissipation (RqJA) (Note 2) Continuous Drain Current (RqJC) Power Dissipation (RqJC) Pulsed Drain Current Current Limited by Package Steady State TA = 25°C TA = 85°C TA = 25°C TA = 25°C TA = 85°C TA = 25°C TC = 25°C TC = 85°C TC = 25°C tp = 10 ms TA = 25°C PD IDM IDmaxPkg TJ, Tstg IS dV/dt EAS PD ID PD ID Symbol VDSS VGS ID Value 25 "20 14.7 11.4 2.3 11.3 8.8 1.4 85 66 76.9 98 32 − 55 to 175 77 8.0 75 W A A °C A V/ns mJ W A W Unit V V A G S 4 4 N−Channel 4 A 12 3 1 1 2 23 CASE 369C DPAK (Bend Lead) STYLE 2 3 CASE 369D DPAK (Straight Lead) STYLE 2 CASE 369AC 3 IPAK (Straight Lead) MARKING DIAGRAMS & PIN ASSIGNMENTS 4 Drain YWW 78 N03RG 3 Source 1 Gate Y = Year WW = Work Week 78N03R= Device Code G = Pb−Free Package 3 Source 2 Drain Publication Order Number: NTD78N03R/D 4 Drain YWW 78 N03RG 1 Gate 2 Drain Operating Junction and Storage Temperature Source Current (Body Diode) Drain to Source dV/dt Single Pulse Drain−to−Source Avalanche Energy (VDD = 24 V, VGS = 10 V, L = 5.0 mH, IL(pk) = 5.5 A, RG = 25 W) Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) TL 260 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface−mounted on FR4 board using 1 in sq pad size, 1 oz Cu. 2. Surface−mounted on FR4 board using the minimum recommended pad size. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. © Semiconductor Components Industries, LLC, 2006 August, 2006 − Rev. 4 1 NTD78N03R THERMAL RESISTANCE MAXIMUM RATINGS Parameter Junction−to−Case (Drain) Junction−to−Ambient − Steady State (Note 3) Junction−to−Ambient − Steady State (Note 4) Symbol RqJC RqJA RqJA Value 1.95 65 110 Unit °C/W ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameter OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage Drain−to−Source Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current V(BR)DSS V(BR)DSS/TJ IDSS IGSS VGS(TH) VGS(TH)/TJ RDS(on) VGS = 10V to 11.5 V VGS = 4.5 V Forward Transconductance gFS ID = 30 A ID = 15 A ID = 30 A ID = 15 A VDS = 15 V, ID = 10 A CHARGES, CAPACITANCES AND GATE RESISTANCE Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Threshold Gate Charge Gate−to−Source Charge Gate−to−Drain Charge SWITCHING CHARACTERISTICS (Note 6) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Time 3. 4. 5. 6. VSD tRR ta tb QRR VGS = 0 V, dIs/dt = 100 A/ms, IS = 20 A VGS = 0 V, IS = 30 A TJ = 25°C 0.8 38 16.5 22 31 nC 1.0 V ns td(on) tr td(off) tf VGS = 4.5 V, VDS = 20 V, ID = 20 A, RG = 2.5 W 11 75 18 17 ns Ciss Coss Crss QG(TOT) QG(TH) QGS QGD VGS = 4.5 V, VDS = 20 V, ID = 20 A 1794 VGS = 0 V, f = 1.0 MHz, VDS = 12 V 882 373 19.4 0.8 2.9 12.4 24 nC pF VGS = 0 V, VDS = 20 V TJ = 25°C TJ = 125°C VGS = 0 V, ID = 250 mA 25 10 1.5 10 "100 nA V mV/°C mA Symbol Test Condition Min Typ Max Unit Gate−to−Source Leakage Current ON CHARACTERISTICS (Note 5) Gate Threshold Voltage Negative Threshold Temperature Coefficient Drain−to−Source On Resistance VDS = 0 V, VGS = "20 V VGS = VDS, ID = 250 mA 1.0 1.7 −5.3 5.0 4.9 7.5 7.2 23 3.0 V mV/°C 5.8 5.7 9.0 8.5 mW S Surface−mounted on FR4 board using 1 in sq pad size, 1 oz Cu. Surface−mounted on FR4 board using the minimum recommended pad size. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 NTD78N03R 120 ID, DRAIN CURRENT (AMPS) 100 80 60 40 20 0 3V 2.6 V 2.4 V 0 1 2 3 4 5 6 7 8 9 10 10 V TJ = 25°C 6V 4.5 V 3.5 V 120 ID, DRAIN CURRENT (AMPS) VGS = 4 V 100 80 60 40 TJ = 125°C 20 0 0 TJ = −55°C 1 2 3 4 5 6 7 8 VGS, GATE−TO−SOURCE VOLTAGE (V) TJ = 25°C VDS ≥ 10 V VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 1. On−Region Characteristics RDS(on), DRAIN−TO−SOURCE RESISTANCE (mΩ) Figure 2. Transfer Characteristics 11.50 ID = 30 A TJ = 25°C RDS(on), DRAIN−TO−SOURCE RESISTANCE (Ω) 0.01 TJ = 25°C 0.008 VGS = 4.5 V 0.006 VGS = 10 V 0.004 10.25 9.00 7.75 6.50 5.25 4.00 3 4 5 6 7 8 9 10 0.002 10 15 20 ID, DRAIN CURRENT (A) 25 30 VGS, GATE−TO−SOURCE VOLTAGE (V) Figure 3. On−Resistance versus Gate−to−Source Voltage RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 2 1.8 1.6 1.4 1.2 1 0.8 0.6 −50 −25 0 25 50 75 100 125 150 175 100 2 ID = 30 A VGS = 10 V to 11.5V IDSS, LEAKAGE (nA) 10000 100000 Figure 4. On−Resistance versus Drain Current and Gate Voltage VGS = 0 V TJ = 175°C 1000 TJ = 100°C 4 6 8 10 12 14 16 18 20 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−To−Source Leakage Current versus Voltage http://onsemi.com 3 NTD78N03R VGS, GATE−TO−SOURCE VOLTAGE (V) 3500 3000 C iss C, CAPACITANCE (pF) 2500 2000 1500 1000 500 0 20 Crss 15 10 5 VGS 0 VDS 5 10 15 20 25 Crss Coss Ciss VDS = 0 V VGS = 0 V TJ = 25°C 5 4 3 2 1 0 QT VDS Q1 Q2 VGS 20 16 12 8 4 0 20 VDS, DRAIN−TO−SOURCE VOLTAGE (V) ID = 20 A TJ = 25°C 0 4 8 12 16 Qg, TOTAL GATE CHARGE (nC) GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V) Figure 7. Capacitance Variation Figure 8. Gate−to−Source and Drain−to−Source Voltage versus Total Charge 1000 40 IS, SOURCE CURRENT (AMPS) VDS = 15 V ID = 20 A VGS = 4.5 V 35 30 25 20 15 10 5 0 0.3 0.6 0.9 VSD, SOURCE−TO−DRAIN VOLTAGE (V) 1.2 VGS = 0 V TJ = 25°C t, TIME (ns) 100 tr tf td(off) 10 td(on) 1 10 RG, GATE RESISTANCE (OHMS) 100 Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure 10. Diode Forward Voltage versus Current http://onsemi.com 4 NTD78N03R ORDERING INFORMATION Order Number NTD78N03R NTD78N03RG NTD78N03RT4 NTD78N03RT4G NTD78N03R−1 NTD78N03R−1G NTD78N03R−35 NTD78N03R−35G Package DPAK DPAK (Pb−Free) DPAK DPAK (Pb−Free) DPAK Straight Lead DPAK Straight Lead (Pb−Free) DPAK Straight Lead (3.5 " 0.15 mm) DPAK Straight Lead (3.5 " 0.15 mm) (Pb−Free) 75 Units/Rail 2500 Tape & Reel 75 Units/Rail Shipping† †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 5 NTD78N03R PACKAGE DIMENSIONS DPAK CASE 369C−01 ISSUE O −T− B V R 4 SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.180 BSC 0.034 0.040 0.018 0.023 0.102 0.114 0.090 BSC 0.180 0.215 0.025 0.040 0.020 −−− 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 4.58 BSC 0.87 1.01 0.46 0.58 2.60 2.89 2.29 BSC 4.57 5.45 0.63 1.01 0.51 −−− 0.89 1.27 3.93 −−− C E S A 1 2 3 Z U K F L D G 2 PL J H 0.13 (0.005) M DIM A B C D E F G H J K L R S U V Z T SOLDERING FOOTPRINT* 6.20 0.244 2.58 0.101 5.80 0.228 1.6 0.063 6.172 0.243 3.0 0.118 SCALE 3:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 6 NTD78N03R PACKAGE DIMENSIONS DPAK CASE 369D−01 ISSUE B B V R 4 C E Z NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. DIM A B C D E F G H J K R S V Z INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 −−− S −T− SEATING PLANE A 1 2 3 K F D G 3 PL J H M 0.13 (0.005) T STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN http://onsemi.com 7 NTD78N03R PACKAGE DIMENSIONS 3 IPAK, STRAIGHT LEAD CASE 369AC−01 ISSUE O NOTES: 1.. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2.. CONTROLLING DIMENSION: INCH. 3. SEATING PLANE IS ON TOP OF DAMBAR POSITION. 4. DIMENSION A DOES NOT INCLUDE DAMBAR POSITION OR MOLD GATE. DIM A B C D E F G H J K R V W INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.043 0.090 BSC 0.034 0.040 0.018 0.023 0.134 0.142 0.180 0.215 0.035 0.050 0.000 0.010 MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.09 2.29 BSC 0.87 1.01 0.46 0.58 3.40 3.60 4.57 5.46 0.89 1.27 0.000 0.25 B V R C E A SEATING PLANE W F G K J D H 3 PL 0.13 (0.005) W ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 8 NTD78N03R/D