NTD85N02R
Power MOSFET, 85 A, 24 V,
N-Channel DPAK/IPAK
Features
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Planar HD3e Process for Fast Switching Performance
Low RDS(on) to Minimize Conduction Losses
Low Capacitance to Minimize Driver Losses
Low Gate Charge to Minimize Switching Losses
Pb−Free Packages are Available
V(BR)DSS
RDS(ON) MAX
ID MAX
24 V
5.2 m V
85 A
Applications
N−Channel
D
• CPU Power Delivery
• DC−DC Converters
• Low Side Switching
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Symbol
Parameter
G
Value
Unit
Drain−to−Source Voltage
VDSS
24
V
Gate−to−Source Voltage
VGS
±20
V
ID
17
A
Continuous Drain
Current RJA
(Note 1)
TA = 25°C
Power Dissipation
RJA (Note 1)
TA = 25°C
PD
2.4
W
Continuous Drain
Current RJA
(Note 2)
TA = 25°C
ID
12
A
Power Dissipation
RJA (Note 2)
TA = 85°C
Steady
State
TA = 85°C
W
Continuous Drain
Current RJC
(Note 1)
TC = 25°C
ID
85
A
Power Dissipation
RJC (Note 1)
TC = 25°C
PD
78.1
W
TA = 25°C, tp = 10s
IDM
192
A
TC = 85°C
TA = 25°C
45
A
TJ,
TSTG
−55 to
+150
°C
IS
78
A
Drain to Source dV/dt
dV/dt
6
V/ns
Single Pulse Drain−to−Source Avalanche
Energy TJ = 25°C, VDD = 30 V, VGS = 10 V,
IL = 13 Apk, L = 1.0 mH, RG = 25
EAS
85
mJ
TL
260
°C
Lead Temperature for Soldering Purposes
(1/8” from case for 10 s)
January, 2007 − Rev. 9
1
2
3
DPAK−3
CASE 369D
STYLE 2
MARKING DIAGRAM
& PIN ASSIGNMENTS
4
1
2
3
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
© Semiconductor Components Industries, LLC, 2007
DPAK
CASE 369AA
STYLE2
58
IDmaxPkg
Source Current (Body Diode)
1
1 2
3
1.25
Operating Junction and Storage
Temperature
4
8.8
PD
Current Limited by Package
4
12
TA = 25°C
Pulsed Drain
Current
S
YWW
85
N02G
Y
WW
85N02R
G
4
1 Gate
2 Drain
3 Source
4 Drain
= Year
= Work Week
= Specific Device Code
= Pb−Free Package
YWW
85
N02G
•
•
•
•
•
1
2
3
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
Publication Order Number:
NTD85N02R/D
NTD85N02R
THERMAL RESISTANCE MAXIMUM RATINGS
Symbol
Value
Unit
Junction−to−Case (Drain)
Parameter
RJC
1.6
°C/W
Junction−to−TAB (Drain)
RJC−TAB
3.5
Junction−to−Ambient – Steady State (Note 1)
RJA
52
Junction−to−Ambient – Steady State (Note 2)
RJA
100
1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 A
24
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/
TJ
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate−to−Source Leakage Current
IDSS
28
V
20.5
VGS = 0 V,
VDS = 24 V
mV/°C
TJ = 25 °C
1.5
TJ = 125°C
10
IGSS
VDS = 0 V, VGS = ±20 V
VGS(TH)
VGS = VDS, ID = 250 A
A
±100
nA
2.0
V
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
Negative Threshold Temperature
Coefficient
VGS(TH)/TJ
Drain−to−Source on Resistance
RDS(ON)
Forward Transconductance
1.0
1.5
4
VGS = 10 V
ID = 20 A
4.8
VGS = 4.5 V
ID = 20 A
6.5
gFS
VDS = 10 V, ID = 15 A
38
mV/°C
5.2
m
S
CHARGES AND CAPACITANCES
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
359
Total Gate Charge
QG(TOT)
17.7
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
Gate−to−Drain Charge
Total Gate Charge
QGS
2050
VGS = 0 V, f = 1.0 MHz, VDS = 20 V
pF
1.6
VGS = 5.0 V, VDS = 10 V; ID = 10 A
QGD
QG(TOT)
871
2.6
nC
7.1
VGS = 10 V, VDS = 10 V;
ID = 10 A
35.1
nC
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(ON)
tr
td(OFF)
6.3
VGS = 10 V, VDS = 10 V,
ID = 30 A, RG = 3.0
tf
77
25
12
3. Pulse Test: pulse width v 300 s, duty cycle v 2%.
4. Switching characteristics are independent of operating junction temperatures.
http://onsemi.com
2
ns
NTD85N02R
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Typ
Max
TJ = 25°C
0.81
1.0
TJ = 125°C
0.65
Unit
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
Reverse Recovery Time
Charge Time
VSD
tRR
ta
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V,
IS = 30 A
V
37.5
VGS = 0 V, dIS/dt = 100 A/s,
IS = 20 A
16.8
ns
20.7
QRR
27
nC
Source Inductance
LS
2.49
nH
Drain Inductance, DPAK
LD
0.0164
Drain Inductance, IPAK*
LD
PACKAGE PARASITIC VALUES
TA = 25°C
1.88
Gate Inductance
LG
3.46
Gate Resistance
RG
1.2
*Assume standoff of 110 mils.
ORDERING INFORMATION
Device
NTD85N02R
NTD85N02RG
Package
DPAK
DPAK
(Pb−Free)
NTD85N02R−001
IPAK
NTD85N02R−1G
IPAK
(Pb−Free)
NTD85N02RT4
NTD85N02RT4G
Shipping †
75 Units / Rail
800 / Tape & Reel
DPAK
DPAK
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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3
NTD85N02R
160
4.4 V
5V
3.8 V
6V
120
VDS ≥ 10 V
VGS = 4 V
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
160
10 V
3.6 V
3.4 V
3.2 V
80
3V
2.8 V
40
2.6 V
2.4 V
0
TJ = 25°C
40
TJ = 125°C
TJ = −55°C
2
4
6
8
10
0
1
2
3
4
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
RDS(on), DRAIN−TO−SOURCE RESISTANCE ()
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
0.018
VGS = 10 V
0.014
0.010
TJ = 125°C
0.006
TJ = 25°C
TJ = −55°C
0.002
0
40
120
80
160
6
5
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0.018
VGS = 4.5 V
0.014
TJ = 125°C
0.010
TJ = 25°C
0.006
TJ = −55°C
0.002
0
80
40
120
160
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus Drain Current
and Temperature
Figure 4. On−Resistance versus Drain Current
and Temperature
100,000
1.8
1.6
VGS = 0 V
ID = 40 A
VGS = 10 V
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE ()
80
0
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
120
TJ = 150°C
10,000
1.4
1.2
1.0
TJ = 125°C
1000
0.8
0.6
−50
100
−25
0
25
50
75
100
125
150
0
5
10
15
20
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
http://onsemi.com
4
25
NTD85N02R
POWER MOSFET SWITCHING
VGS , GATE−TO−SOURCE VOLTAGE (VOLTS)
4800
C, CAPACITANCE (pF)
TJ = 25°C
4000
Ciss
3200
Crss
2400
Ciss
1600
Coss
800
Crss
VDS = 0 V VGS = 0 V
0
10
0
5
VGS
10
5
15
20
VDS
6
QT
VGS
4
Q1
2
ID = 10 A
TJ = 25°C
0
0
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
4
8
12
16
QG, TOTAL GATE CHARGE (nC)
20
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 7. Capacitance Variation
80
100
IS, SOURCE CURRENT (AMPS)
1000
tr
td(off)
tf
10
td(on)
VDS = 10 V
ID = 40 A
VGS = 10 V
VGS = 0 V
70
60
50
40
30
20
10
TJ = 25°C
0
1
1
10
RG, GATE RESISTANCE (OHMS)
0
100
0.2
0.4
0.6
0.8
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
1000
10 s
100
100 s
1 ms
10
1
VGS = 20 V
SINGLE PULSE
TC = 25°C
10 ms
dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0.1
1.0
Figure 10. Diode Forward Voltage versus Current
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
I D, DRAIN CURRENT (AMPS)
t, TIME (ns)
Q2
1
10
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
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5
100
NTD85N02R
EFFECTIVE TRANSIENT THERMAL RESISTANCE
(NORMALIZED)
10
Normalized to RJC at Steady State
1
r(t),
0.1
0.01
0.00001
0.001
0.0001
0.01
0.1
1
10
t, TIME (s)
Figure 12. Thermal Response
EFFECTIVE TRANSIENT THERMAL RESPONSE
(NORMALIZED)
10
Normalized to RJA at Steady State,
1″ square Cu Pad, Cu Area 1.127 in2,
3 x 3 inch FR4 board
1
r(t),
0.1
0.01
0.00001
0.0001
0.001
0.01
0.1
1
t, TIME (s)
Figure 13. Thermal Response
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6
10
100
1000
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
IPAK
CASE 369D−01
ISSUE C
SCALE 1:1
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
E
R
4
Z
A
S
1
2
3
−T−
SEATING
PLANE
K
J
F
D
G
DATE 15 DEC 2010
H
3 PL
0.13 (0.005)
M
DIM
A
B
C
D
E
F
G
H
J
K
R
S
V
Z
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.018 0.023
0.037 0.045
0.090 BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.180 0.215
0.025 0.040
0.035 0.050
0.155
−−−
MILLIMETERS
MIN
MAX
5.97
6.35
6.35
6.73
2.19
2.38
0.69
0.88
0.46
0.58
0.94
1.14
2.29 BSC
0.87
1.01
0.46
0.58
8.89
9.65
4.45
5.45
0.63
1.01
0.89
1.27
3.93
−−−
T
MARKING
DIAGRAMS
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
STYLE 5:
PIN 1. GATE
2. ANODE
3. CATHODE
4. ANODE
STYLE 6:
PIN 1. MT1
2. MT2
3. GATE
4. MT2
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 4:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
Discrete
YWW
xxxxxxxx
STYLE 7:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
xxxxxxxxx
A
lL
Y
WW
DOCUMENT NUMBER:
DESCRIPTION:
98AON10528D
Integrated
Circuits
xxxxx
ALYWW
x
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
IPAK (DPAK INSERTION MOUNT)
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DPAK (SINGLE GUAGE)
CASE 369AA−01
ISSUE B
4
1 2
DATE 03 JUN 2010
3
SCALE 1:1
A
E
b3
c2
B
Z
D
1
L4
A
4
L3
2
b2
H
DETAIL A
3
c
b
0.005 (0.13)
e
M
H
C
L2
GAUGE
PLANE
C
L
L1
DETAIL A
A1
ROTATED 905 CW
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
STYLE 3:
PIN 1. ANODE
2. CATHODE
3. ANODE
4. CATHODE
STYLE 5:
PIN 1. GATE
2. ANODE
3. CATHODE
4. ANODE
STYLE 6:
PIN 1. MT1
2. MT2
3. GATE
4. MT2
STYLE 7:
PIN 1. GATE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
STYLE 4:
PIN 1. CATHODE
2. ANODE
3. GATE
4. ANODE
SOLDERING FOOTPRINT*
6.20
0.244
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DIMENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
C
2.58
0.102
5.80
0.228
3.00
0.118
1.60
0.063
INCHES
MIN
MAX
0.086 0.094
0.000 0.005
0.025 0.035
0.030 0.045
0.180 0.215
0.018 0.024
0.018 0.024
0.235 0.245
0.250 0.265
0.090 BSC
0.370 0.410
0.055 0.070
0.108 REF
0.020 BSC
0.035 0.050
−−− 0.040
0.155
−−−
MILLIMETERS
MIN
MAX
2.18
2.38
0.00
0.13
0.63
0.89
0.76
1.14
4.57
5.46
0.46
0.61
0.46
0.61
5.97
6.22
6.35
6.73
2.29 BSC
9.40 10.41
1.40
1.78
2.74 REF
0.51 BSC
0.89
1.27
−−−
1.01
3.93
−−−
GENERIC
MARKING DIAGRAM*
XXXXXXG
ALYWW
YWW
XXX
XXXXXG
IC
Discrete
XXXXXX
A
L
Y
WW
G
6.17
0.243
SCALE 3:1
SEATING
PLANE
DIM
A
A1
b
b2
b3
c
c2
D
E
e
H
L
L1
L2
L3
L4
Z
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer
to device data sheet for actual part
marking.
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13126D
DPAK (SINGLE GAUGE)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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