NTD95N02R-1G

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Other names and brands may be claimed as the property of others. NTD95N02R Power MOSFET 95 Amps, 24 Volts N−Channel DPAK Features http://onsemi.com High Power and Current Handling Capability Fast Switching Performance Low RDS(on) to Minimize Conduction Loss Low Gate Charge to Minimize Switching Losses Pb−Free Packages are Available V(BR)DSS RDS(ON) TYP 4.5 mW @ 10 V 24 V 5.9 mW @ 4.5 V 95 A *ID MAX in the product summary table is continuous and steady at 25°C. Applications D CPU Motherboard Vcore Applications High Frequency DC−DC Converters Motor Drives Bridge Circuits G S MAXIMUM RATINGS (TJ = 25°C unless otherwise specified) Parameter Drain−to−Source Voltage Symbol Value Unit VDSS 24 V Gate−to−Source Voltage VGS ±20 V Thermal Resistance, Junction−to−Case Total Power Dissipation @ TA = 25°C Drain Current – − Continuous @ TA= 25°C, Limited by Package − Continuous @ TA= 25°C, Limited by Wires RqJC PD 1.45 86 °C/W W ID ID 95 32 A A Thermal Resistance, Junction−to− Ambient (Note 1) − Total Power Dissipation @ TA = 25°C − Drain Current − Continuous @ TA= 25°C RqJA 52 °C/W PD ID 2.4 15.8 W A Thermal Resistance, Junction−to−Ambient (Note 2) − Total Power Dissipation @ TA = 25°C − Drain Current − Continuous @ TA= 25°C RqJA 100 °C/W PD ID 1.25 12 W A Operating Junction and Storage Temperature TJ, TSTG −55 to 150 °C IS 45 A Single Pulse Drain−to−Source Avalanche Energy – (VDD = 25 V, VG = 10, IPK = 13 A, L = 1 mH, RG= 25 W) EAS 84 mJ Lead Temperature for Soldering Purposes (1/8 in from case for 10 seconds) TL Continuous Source Current (Body Diode) MARKING DIAGRAMS & PIN ASSIGNMENTS 4 Drain 4 1 2 3 DPAK CASE 369AA (Surface Mount) STYLE 2 2 1 3 Drain Gate Source 4 Drain 4 1 DPAK CASE 369D (Straight Lead) STYLE 2 2 3 °C 260 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces). 2. Surface mounted on FR4 board using the minimum recommended pad size (Cu area = 0.412 in sq). YWW T95 N02RG • • • • ID MAX* YWW T95 N02RG • • • • • 1 2 3 Gate Drain Source Y WW T95N02R G = Year = Work Week = Device Code = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. © Semiconductor Components Industries, LLC, 2006 July, 2006 − Rev. 3 1 Publication Order Number: NTD95N02R/D NTD95N02R THERMAL RESISTANCE RATINGS Symbol Value Unit Junction−to−Case (Drain) Parameter RqJC 1.45 °C/W Junction−to−Ambient – Steady State (Note 3) RqJA 52 Junction−to−Ambient – Steady State (Note 4) RqJA 100 3. Surface mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces). 4. Surface mounted on FR4 board using the minimum recommended pad size (Cu area = 0.412 in sq). ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameter Symbol Test Condition Min Typ Max Unit Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 24 29 V Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/T 15 mV/°C OFF CHARACTERISTICS J Zero Gate Voltage Drain Current IDSS VGS = 0 V, VDS = 20 V TJ = 25°C TJ = 125°C IGSS VDS = 0 V, VGS = ±20 V VGS(TH) VGS = VDS, ID = 250 mA Gate−to−Source Leakage 1.5 mA 10 ±100 nA 2.0 V ON CHARACTERISTICS (Note 5) Gate Threshold Voltage Negative Threshold Temperature Coefficient VGS(TH)/TJ Drain−to−Source On−Resistance RDS(on) Forward Transconductance gFS 1.0 5.0 mV/°C mW VGS = 4.5 V, ID = 10 A 5.9 8.0 VGS = 10 V, ID = 20 A 4.5 5.0 VGS = 10 V, ID = 10 A 30 S 2400 pF CHARGES, CAPACITANCES AND GATE RESISTANCE Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS 390 QT 21 Total Gate Charge QGS VGS = 0 V, f = 1.0 MHz, VDS = 20 V VGS = 4.5 V, VDS = 10 V; ID = 10 A 1020 nC 4.4 QGD 9.1 td(on) 10 SWITCHING CHARACTERISTICS Turn−on Delay Time Rise Time Turn−off Time tr td(off) Fall Time VGS = 10 V, VDD = 10 V, ID = 30 A, RG = 3 W tf ns 82 26 70 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage VSD Reverse Recovery Time tRR 45 Charge Time Ta 20 Discharge Time Tb Reverse Recovery Charge VGS = 0 V, IS = 20 A TJ = 25°C VGS = 0 V, dISD/dt = 100 A/ms, IS = 20 A QRR 0.83 http://onsemi.com 2 V ns 30 50 5. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 1.2 nC NTD95N02R TYPICAL CHARACTERISTICS 160 TJ = 25°C 4.2 V 4.0 V 140 120 3.6 V 100 3.4 V 80 3.2 V 60 3.0 V 40 2.8 V 2.6 V 2.4 V 20 0 2 1 3 4 5 6 8 7 9 10 120 100 80 TJ = 100°C 60 TJ = 25°C 40 TJ = −55°C 0 1 2 3 4 Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics 0.006 0.005 0.004 4 5 6 7 8 9 10 6 5 VGS, GATE−TO−SOURCE VOLTAGE (V) 0.007 0.016 TJ = 25°C 0.014 0.012 0.010 VGS = 4.5 V 0.008 0.006 0.004 VGS = 10 V 0.002 10 30 50 70 90 110 130 150 170 VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A) Figure 3. On−Resistance versus Gate−to−Source Voltage Figure 4. On−Resistance versus Drain Current and Gate Voltage 1.8 100000 ID = 95 A VGS = 10 V VGS = 0 V IDSS, LEAKAGE (nA) 1.6 140 0 ID = 95 A TJ = 25°C 3 160 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 0.008 0.003 180 20 0.009 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0 VDS w 10 V 200 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) ID, DRAIN CURRENT (A) 220 VGS = 10 V 7.0 V 5.0 V ID, DRAIN CURRENT (A) 200 180 TJ = 150°C 10000 1.4 1.2 1.0 1000 TJ = 100°C 0.8 0.6 −50 −25 0 25 50 75 100 125 150 100 2 TJ, JUNCTION TEMPERATURE (°C) Figure 5. On−Resistance Variation with Temperature 4 6 8 10 12 14 16 18 VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 6. Drain−to−Source Leakage Current versus Voltage http://onsemi.com 3 20 NTD95N02R 4500 C, CAPACITANCE (pF) VGS = 0 V VDS = 0 V TJ = 25°C CISS 4000 3500 3000 CISS 2500 CRSS 2000 1500 COSS 1000 CRSS 500 0 10 5 VGS 0 VDS 5 10 15 20 6 12 5 QT 4 VDS QGS 3 8 VGS QGD 2 4 1 0 ID = 10 A TJ = 25°C 0 4 8 12 16 20 0 24 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 5000 VGS, GATE−TO−SOURCE VOLTAGE (V) TYPICAL CHARACTERISTICS Qg, TOTAL GATE CHARGE (nC) GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V) Figure 7. Capacitance Variation Figure 8. Gate−to−Source and Drain−to−Source Voltage versus Total Charge 1000 100 VDS = 10 V ID = 30 A VGS = 10 V IS, SOURCE CURRENT (A) tr tf 100 t, TIME (ns) 90 td(off) 10 td(on) 80 VGS = 0 V TJ = 25°C 70 60 50 40 30 20 10 1 1 10 0 0.4 100 RG, GATE RESISTANCE (W) 0.6 0.8 1.0 1.2 VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure 10. Diode Forward Voltage versus Current ORDERING INFORMATION Package Shipping † DPAK 75 Units / Rail DPAK (Pb−Free) 75 Units / Rail DPAK 75 Units / Rail DPAK (Pb−Free) 75 Units / Rail DPAK 2500 Units / Tape & Reel DPAK (Pb−Free) 2500 Units / Tape & Reel Device NTD95N02R NTD95N02RG NTD95N02R−001 NTD95N02R−001G NTD95N02RT4 NTD95N02RT4G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 4 NTD95N02R PACKAGE DIMENSIONS DPAK (SINGLE GUAGE) CASE 369AA−01 ISSUE A −T− C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. SEATING PLANE E R 4 A S 1 2 DIM A B C D E F H J L R S U V Z Z H 3 U F J L D 2 PL 0.13 (0.005) M INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.025 0.035 0.018 0.024 0.030 0.045 0.386 0.410 0.018 0.023 0.090 BSC 0.180 0.215 0.024 0.040 0.020 −−− 0.035 0.050 0.155 −−− STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN T SOLDERING FOOTPRINT* 6.20 0.244 2.58 0.101 5.80 0.228 3.0 0.118 1.6 0.063 6.172 0.243 SCALE 3:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 5 MILLIMETERS MIN MAX 5.97 6.22 6.35 6.73 2.19 2.38 0.63 0.89 0.46 0.61 0.77 1.14 9.80 10.40 0.46 0.58 2.29 BSC 4.57 5.45 0.60 1.01 0.51 −−− 0.89 1.27 3.93 −−− NTD95N02R PACKAGE DIMENSIONS DPAK CASE 369D−01 ISSUE B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. C B E R 4 Z A S 1 2 3 −T− SEATING PLANE K J F H D G 3 PL 0.13 (0.005) M DIM A B C D E F G H J K R S V Z INCHES MIN MAX 0.235 0.245 0.250 0.265 0.086 0.094 0.027 0.035 0.018 0.023 0.037 0.045 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.180 0.215 0.025 0.040 0.035 0.050 0.155 −−− MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.46 0.58 0.94 1.14 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.45 0.63 1.01 0.89 1.27 3.93 −−− STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN T ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 6 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NTD95N02R/D