NTGD4161PT1G

NTGD4161P Power MOSFET −30 V, −2.3 A, Dual P−Channel, TSOP−6 Features • • • • • Fast Switching Speed Low Gate Charge Low RDS(on) Independently Connected Devices to Provide Design Flexibility This is a Pb−Free Device http://onsemi.com V(BR)DSS RDS(on) Max 160 mW @ −10 V Applications • Load Switch • Battery Protection • Portable Devices Like PDAs, Cellular Phones and Hard Drives −30 V 280 mW @ −4.5 V P−Channel (MOSFET1) D1 MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Parameter Symbol Value Unit Drain−to−Source Voltage VDSS −30 V Gate−to−Source Voltage VGS ±20 V ID −2.1 A Continuous Drain Current (Note 1) Power Dissipation (Note 1) Steady State TA = 25°C t≤5s TA = 25°C Steady State TA = 25°C TA = 85°C Steady State Power Dissipation (Note 2) Pulsed Drain Current G1 G2 −2.3 PD S1 W 1.1 ID TA = 85°C TA = 25°C tp = 10 ms 1 0.6 W IDM −10 A TJ, TSTG −55 to 150 °C Source Current (Body Diode) IS −0.8 A Lead Temperature for Soldering Purposes (1/8” from case for 10 s) TL 260 °C Operating Junction and Storage Temperature D1 S1 D2 A −1.5 −1.1 PD S2 MARKING DIAGRAM 1.3 TA = 25°C D2 −1.5 t≤5s Continuous Drain Current (Note 2) P−Channel (MOSFET2) S8 MG G TSOP−6 CASE 318G STYLE 13 S8 M G G1 S2 G2 = Specific Device Code = Date Code* = Pb−Free Package (Note: Microdot may be in either location) THERMAL RESISTANCE RATINGS Parameter Junction−to−Ambient − Steady State (Note 1) Symbol Max Unit RqJA 115 °C/W *Date Code orientation may vary depending upon manufacturing location. ORDERING INFORMATION Junction−to−Ambient − Steady State (Note 2) 225 Junction−to−Ambient − t ≤ 5 s (Note 1) 95 Device Package Shipping † 40 NTGD4161PT1G TSOP−6 (Pb−Free) 3000 / Tape & Reel Junction−to−Case − Steady State (Note 1) RqJC Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. When surface mounted to an FR4 board using 1 in. pad size (Cu. area = 1.2 in2 [1 oz] including traces) 2. When surface mounted to an FR4 board using minimum recommended pad size (Cu. area = 0.047 in2) © Semiconductor Components Industries, LLC, 2006 September, 2006 − Rev. 1 1 †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Publication Order Number: NTGD4161P/D NTGD4161P ELECTRICAL CHARACTERISTICS (TJ=25°C unless otherwise stated) Parameter Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = −250 mA −30 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current IDSS 22 VGS = 0 V, VDS = −24 V mV/°C TJ = 25°C −1.0 TJ = 125°C −10 IGSS VDS = 0 V, VGS = ±20 V VGS(TH) VGS = VDS, ID = −250 mA Gate−to−Source Leakage Current V mA ±100 nA −3.0 V ON CHARACTERISTICS (Note 3) Gate Threshold Voltage Gate Threshold Temperature Coefficient Drain−to−Source On Resistance VGS(TH)/TJ RDS(on) Forward Transconductance gFS −1.0 −1.9 −4.7 mV/°C VGS = −10 V, ID = −2.1 A 105 160 VGS = −4.5 V, ID = −1.6 A 190 280 VDS = −5.0 V, ID = −2.1 A 2.7 S 281 pF mΩ CHARGES AND CAPACITANCES Input Capacitance CISS VDS = −15 V, f = 1.0 MHz, VGS = 0 V Output Capacitance COSS 50 Reverse Transfer Capacitance CRSS 28 Total Gate Charge QG(TOT) 5.6 Threshold Gate Charge QG(TH) Gate−to−Source Charge QGS Gate−to−Drain Charge QGD 0.90 td(on) 7.1 nC 7.6 14 ns 9.2 23 12.5 20 4.5 12 TJ = 25°C −0.79 −1.2 TJ = 125°C −0.65 VGS = −10 V, VDS = −5.0 V, ID = −2.1A 0.65 1.2 SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time tr td(off) VGS = −4.5 V, VDD = −15 V, ID = −1.0 A, RG = 6.0 Ω tf DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time VSD tRR Charge Time ta Discharge Time tb Reverse Recovery Charge VGS = 0 V, IS = −0.8 A V 8.0 VGS = 0 V, dIS/dt = 100 A/ms, IS = −0.8 A QRR 5.7 3 3. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 ns 2.3 nC NTGD4161P TYPICAL PERFORMANCE CURVES −10 V −4.5 V 5 TJ = 25°C 4 −ID, DRAIN CURRENT (A) −ID, DRAIN CURRENT (A) 5 −4 V 3 −3.8 V −3.6 V 2 −3.4 V −3.2 V 1 0 −3 V −2.8 V 0 1 2 3 4 −VDS, DRAIN−TO−SOURCE VOLTAGE (V) VDS ≥ −3 V 4 3 2 150°C 1 25°C −40°C 0 5 1 2 3 4 −VGS, GATE−TO−SOURCE VOLTAGE (V) Figure 2. Transfer Characteristics 0.5 ID = −2.1 A 0.4 0.3 TJ = 125°C 0.2 TJ = 25°C 0.1 0 3 4 5 6 7 8 9 10 −VGS, GATE−TO−SOURCE VOLTAGE (V) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) Figure 1. On−Region Characteristics 0.4 TJ = 25°C 0.35 0.3 VGS = −4.5 V 0.25 0.2 0.15 0.1 VGS = −10 V 0.05 0 0 1 2 3 4 5 6 −ID, DRAIN CURRENT (A) Figure 3. On−Resistance versus Gate−to−Source Voltage Figure 4. On−Resistance versus Drain Current and Temperature 0.3 1000 VGS = 0 V ID = −1.6 A VGS = −4.5 V 0.2 ID = −2.1 A VGS = −10 V 0.1 0.0 −50 −IDSS, LEAKAGE(nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE 5 TJ = 150°C 100 TJ = 125°C 10 −25 0 25 50 75 100 125 150 0 TJ, JUNCTION TEMPERATURE (°C) 5 10 15 20 25 −VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. On−Resistance Variation with Temperature http://onsemi.com 3 30 NTGD4161P TYPICAL PERFORMANCE CURVES 250 CISS −VGS, GATE−TO−SOURCE VOLTAGE (V) C, CAPACITANCE (pF) 300 TJ = 25°C VGS = 0 V 200 150 100 COSS 50 CRSS 0 0 5 10 15 20 25 10 10 QT 8 8 VGS 6 6 QGS 4 QGD 2 2 ID = −2.1 A TJ = 25°C VDS 0 0 30 1 DRAIN−TO−SOURCE VOLTAGE (V) 2 3 4 0 6 5 QG, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation Figure 8. Gate−to−Source and Drain−to−Source Voltage versus Total Charge 100 0.8 VGS = −10 V Single Pulse TA = 25°C VGS = 0 V 0.7 −ID, DRAIN CURRENT (A) −IS, SOURCE CURRENT (A) 4 −VDS, DRAIN−TO−SOURCE VOLTAGE (V) 350 0.6 0.5 TJ = 150°C 0.4 0.3 TJ = 125°C 0.2 10 100 ms 1 ms 1 10 ms 0.1 RDS(on) Limit Thermal Limit Package Limit TJ = 25°C 0.1 0 0.3 TJ = −40°C 0.4 0.5 0.6 0.7 0.8 0.9 dc 0.01 1.0 0.1 1 10 100 −VSD, SOURCE−TO−DRAIN VOLTAGE (V) −VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 9. Diode Forward Voltage versus Current Figure 10. Maximum Rated Forward Biased Safe Operating Area RqJA, EFFECTIVE TRANSIENT THERMAL RESPONSE (NORMALIZED) 1.0 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 0.001 1E−06 Single Pulse 1E−05 1E−04 1E−03 1E−02 1E−01 t, time (s) Figure 11. FET Thermal Response http://onsemi.com 4 1E+00 1E+01 1E+02 1E+03 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSOP−6 CASE 318G−02 ISSUE V 1 SCALE 2:1 D H ÉÉ ÉÉ 6 E1 1 NOTE 5 5 2 L2 4 GAUGE PLANE E 3 L b SEATING PLANE C DETAIL Z e DIM A A1 b c D E E1 e L L2 M c A 0.05 M DATE 12 JUN 2012 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D AND E1 ARE DETERMINED AT DATUM H. 5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE. A1 DETAIL Z MIN 0.90 0.01 0.25 0.10 2.90 2.50 1.30 0.85 0.20 0° MILLIMETERS NOM MAX 1.00 1.10 0.06 0.10 0.38 0.50 0.18 0.26 3.00 3.10 2.75 3.00 1.50 1.70 0.95 1.05 0.40 0.60 0.25 BSC 10° − STYLE 1: PIN 1. DRAIN 2. DRAIN 3. GATE 4. SOURCE 5. DRAIN 6. DRAIN STYLE 2: PIN 1. EMITTER 2 2. BASE 1 3. COLLECTOR 1 4. EMITTER 1 5. BASE 2 6. COLLECTOR 2 STYLE 3: PIN 1. ENABLE 2. N/C 3. R BOOST 4. Vz 5. V in 6. V out STYLE 4: PIN 1. N/C 2. V in 3. NOT USED 4. GROUND 5. ENABLE 6. LOAD STYLE 5: PIN 1. EMITTER 2 2. BASE 2 3. COLLECTOR 1 4. EMITTER 1 5. BASE 1 6. COLLECTOR 2 STYLE 6: PIN 1. COLLECTOR 2. COLLECTOR 3. BASE 4. EMITTER 5. COLLECTOR 6. COLLECTOR STYLE 7: PIN 1. COLLECTOR 2. COLLECTOR 3. BASE 4. N/C 5. COLLECTOR 6. EMITTER STYLE 8: PIN 1. Vbus 2. D(in) 3. D(in)+ 4. D(out)+ 5. D(out) 6. GND STYLE 9: PIN 1. LOW VOLTAGE GATE 2. DRAIN 3. SOURCE 4. DRAIN 5. DRAIN 6. HIGH VOLTAGE GATE STYLE 10: PIN 1. D(OUT)+ 2. GND 3. D(OUT)− 4. D(IN)− 5. VBUS 6. D(IN)+ STYLE 11: PIN 1. SOURCE 1 2. DRAIN 2 3. DRAIN 2 4. SOURCE 2 5. GATE 1 6. DRAIN 1/GATE 2 STYLE 12: PIN 1. I/O 2. GROUND 3. I/O 4. I/O 5. VCC 6. I/O STYLE 13: PIN 1. GATE 1 2. SOURCE 2 3. GATE 2 4. DRAIN 2 5. SOURCE 1 6. DRAIN 1 STYLE 14: PIN 1. ANODE 2. SOURCE 3. GATE 4. CATHODE/DRAIN 5. CATHODE/DRAIN 6. CATHODE/DRAIN STYLE 15: PIN 1. ANODE 2. SOURCE 3. GATE 4. DRAIN 5. N/C 6. CATHODE STYLE 16: PIN 1. ANODE/CATHODE 2. BASE 3. EMITTER 4. COLLECTOR 5. ANODE 6. CATHODE STYLE 17: PIN 1. EMITTER 2. BASE 3. ANODE/CATHODE 4. ANODE 5. CATHODE 6. COLLECTOR GENERIC MARKING DIAGRAM* RECOMMENDED SOLDERING FOOTPRINT* 6X 0.60 XXXAYWG G 1 6X 3.20 XXX A Y W G 0.95 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98ASB14888C TSOP−6 1 IC 0.95 XXX MG G = Specific Device Code =Assembly Location = Year = Work Week = Pb−Free Package STANDARD XXX = Specific Device Code M = Date Code G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. 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