NTGS3446T1G

NTGS3446 Power MOSFET 20 V, 5.1 A Single N−Channel, TSOP6 Features • • • • • • • Ultra Low RDS(on) Higher Efficiency Extending Battery Life Logic Level Gate Drive Diode Exhibits High Speed, Soft Recovery Avalanche Energy Specified IDSS Specified at Elevated Temperature Pb−Free Package is Available http://onsemi.com V(BR)DSS RDS(on) TYP ID MAX 20 V 36 mW @ 4.5 V 5.1 A N−Channel Applications Drain 1 2 5 6 • Power Management in portable and battery−powered products, i.e. computers, printers, PCMCIA cards, cellular and cordless • Lithium Ion Battery Applications • Notebook PC Gate 3 MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Symbol Value Unit Drain−to−Source Voltage VDSS 20 V Gate−to−Source Voltage VGS ±12 V RqJA Pd 244 0.5 °C/W W ID IDM 2.5 10 A A RqJA Pd 128 1.0 °C/W W ID IDM 3.6 14 A A RqJA Pd 62.5 2.0 °C/W W ID IDM 5.1 20 A A IS 5.1 A Operating and Storage Temperature Range TJ, Tstg −55 to 150 °C Maximum Lead Temperature for Soldering Purposes for 10 seconds TL 260 °C Rating Thermal Resistance Junction−to−Ambient (Note 1) Total Power Dissipation @ TA = 25°C Drain Current − Continuous @ TA = 25°C − Pulsed Drain Current (tp t 10 ms) Thermal Resistance Junction−to−Ambient (Note 2) Total Power Dissipation @ TA = 25°C Drain Current − Continuous @ TA = 25°C − Pulsed Drain Current (tp t 10 ms) Thermal Resistance Junction−to−Ambient (Note 3) Total Power Dissipation @ TA = 25°C Drain Current − Continuous @ TA = 25°C − Pulsed Drain Current (tp t 10 ms) Source Current (Body Diode) Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Minimum FR−4 or G−10PCB, operating to steady state. 2. Mounted onto a 2” square FR−4 board (1” sq. 2 oz. cu. 0.06” thick single−sided), operating to steady state. 3. Mounted onto a 2” square FR−4 board (1” sq. 2 oz. cu. 0.06” thick single−sided), t < 5.0 seconds. © Semiconductor Components Industries, LLC, 2006 January, 2006 − Rev. 5 1 Source 4 MARKING DIAGRAM TSOP−6 CASE 318G STYLE 1 1 446W 1 446 W = Device Code = Work Week PIN ASSIGNMENT Drain Drain Source 6 5 4 1 2 3 Drain Drain Gate ORDERING INFORMATION Device NTGS3446T1 NTGS3446T1G Package Shipping † TSOP−6 3000/Tape & Reel TSOP−6 (Pb−Free) 3000/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Publication Order Number: NTGS3446/D NTGS3446 ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) Symbol Characteristic Min Typ Max Unit 20 − − 22 − − − − − − 1.0 25 − − − − 100 −100 0.6 − 0.85 −2.5 1.2 − − − 36 44 45 55 gFS − 12 − mhos Ciss − 510 750 pF Coss − 200 350 Crss − 60 100 td(on) − 9.0 16 tr − 12 20 td(off) − 35 60 OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage (VGS = 0 Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Collector Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 85°C) IDSS Gate−Body Leakage Current (VGS = ± 12 Vdc, VDS = 0) IGSS(f) IGSS(r) Vdc mV/°C mAdc nAdc ON CHARACTERISTICS (Note 4) Gate Threshold Voltage ID = 0.25 mA, VDS = VGS Temperature Coefficient (Negative) VGS(th) Static Drain−to−Source On−Resistance (VGS = 4.5 Vdc, ID = 5.1 Adc) (VGS = 2.5 Vdc, ID = 4.4 Adc) RDS(on) Forward Transconductance (VDS = 10 Vdc, ID = 5.1 Adc) Vdc mV/°C mW DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 10 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Note 5) Turn−On Delay Time Rise Time Turn−Off Delay Time (VDD = 10 Vdc, ID = 1.0 Adc, VGS = 4.5 Vdc, RG = 6.0 W) Fall Time Gate Charge (VDS = 10 Vdc, ID = 5.1 Adc, VGS = 4.5 Vdc) tf − 20 35 QT − 8.0 15 Qgs − 2.0 − Qgd − 2.0 − − − 0.74 0.66 1.1 − trr − 20 − ta − 11 − tb − 9.0 − QRR − 0.01 − ns nC SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (Note 4) (IS = 1.7 Adc, VGS = 0 Vdc) (IS = 1.7 Adc, VGS = 0 Vdc, TJ = 85°C) Reverse Recovery Time (IS = 1.7 Adc, VGS = 0 Vdc, diS/dt = 100 A/ms) Reverse Recovery Stored Charge 4. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 5. Switching characteristics are independent of operating junction temperature. http://onsemi.com 2 VSD Vdc ns mC NTGS3446 14 VGS = 2.6 V 14 TJ = 25°C VGS = 2.2 V ID, DRAIN CURRENT (A) VGS = 5 V 10 VGS = 2 V VGS = 10 V 8 6 VGS = 1.8 V 4 VGS = 1.6 V 2 0 1 2 3 4 5 6 7 8 6 4 8 9 TJ = −55°C 0 10 2 3 4 VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V) Figure 2. Transfer Characteristics 0.085 0.06 0.035 1 2 3 4 5 6 VGS, GATE−TO−SOURCE VOLTAGE (V) 0.06 5 TJ = 25°C 0.05 VGS = 2.5 V 0.04 VGS = 5.5 V 0.03 0.02 0.01 2 3 4 5 6 7 8 9 10 ID, DRAIN CURRENT (A) Figure 3. On−Resistance versus Gate−To−Source Voltage Figure 4. On−Resistance versus Drain Current and Gate Voltage 1000 1.6 ID = 3.25 A VGS = 4.5 V 1.4 TJ = 150°C IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 1 Figure 1. On−Region Characteristics ID = 3.3 A TJ = 25°C 1.2 1 0.8 0.6 TJ = 25°C TJ = 125°C 0 0.11 0.01 10 2 VGS = 1.4 V 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) VDS w 10 V 12 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) ID, DRAIN CURRENT (A) 12 VGS = 0 V 100 TJ = 100°C −50 −25 0 25 50 75 100 125 150 10 2 4 6 8 10 12 14 16 18 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current versus Voltage http://onsemi.com 3 20 VDS = 0 V TJ = 25°C Ciss 1200 C, CAPACITANCE (pF) VGS = 0 V 1000 800 Crss 600 Ciss 400 Coss 200 0 −10 Crss −5.0 0 VGS 5.0 10 15 20 5 15 QT 4 12 −VDS −VGS 3 ID = 5.1 A TJ = 25°C Qgd Qgs 2 1 0 9 6 3 0 1 VDS 2 3 4 5 6 7 0 8 Qg, TOTAL GATE CHARGE (nC) GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V) Figure 8. Gate−to−Source and Drain−to−Source Voltage versus Total Charge Figure 7. Capacitance Variation 1000 6 IS, SOURCE CURRENT (A) VDS = 10 V ID = 5.1 A VGS = 4.5 V t, TIME (ns) 100 Vf Vr 10 Vd(off) Vd(on) 1 1 10 5 VGS = 0 V TJ = 25°C 4 3 2 1 0 0.2 100 0.4 0.6 0.8 RG, GATE RESISTANCE (W) VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure 10. Diode Forward Voltage versus Current http://onsemi.com 4 1 VDS, DRAIN−TO−SOURCE VOLTAGE 1400 VGS, GATE−TO−SOURCE VOLTAGE (V) NTGS3446 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSOP−6 CASE 318G−02 ISSUE V 1 SCALE 2:1 D H ÉÉ ÉÉ 6 E1 1 NOTE 5 5 2 L2 4 GAUGE PLANE E 3 L b SEATING PLANE C DETAIL Z e DIM A A1 b c D E E1 e L L2 M c A 0.05 M DATE 12 JUN 2012 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D AND E1 ARE DETERMINED AT DATUM H. 5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE. A1 DETAIL Z MIN 0.90 0.01 0.25 0.10 2.90 2.50 1.30 0.85 0.20 0° MILLIMETERS NOM MAX 1.00 1.10 0.06 0.10 0.38 0.50 0.18 0.26 3.00 3.10 2.75 3.00 1.50 1.70 0.95 1.05 0.40 0.60 0.25 BSC 10° − STYLE 1: PIN 1. DRAIN 2. DRAIN 3. GATE 4. SOURCE 5. DRAIN 6. DRAIN STYLE 2: PIN 1. EMITTER 2 2. BASE 1 3. COLLECTOR 1 4. EMITTER 1 5. BASE 2 6. COLLECTOR 2 STYLE 3: PIN 1. ENABLE 2. N/C 3. R BOOST 4. Vz 5. V in 6. V out STYLE 4: PIN 1. N/C 2. V in 3. NOT USED 4. GROUND 5. ENABLE 6. LOAD STYLE 5: PIN 1. EMITTER 2 2. BASE 2 3. COLLECTOR 1 4. EMITTER 1 5. BASE 1 6. COLLECTOR 2 STYLE 6: PIN 1. COLLECTOR 2. COLLECTOR 3. BASE 4. EMITTER 5. COLLECTOR 6. COLLECTOR STYLE 7: PIN 1. COLLECTOR 2. COLLECTOR 3. BASE 4. N/C 5. COLLECTOR 6. EMITTER STYLE 8: PIN 1. Vbus 2. D(in) 3. D(in)+ 4. D(out)+ 5. D(out) 6. GND STYLE 9: PIN 1. LOW VOLTAGE GATE 2. DRAIN 3. SOURCE 4. DRAIN 5. DRAIN 6. HIGH VOLTAGE GATE STYLE 10: PIN 1. D(OUT)+ 2. GND 3. D(OUT)− 4. D(IN)− 5. VBUS 6. D(IN)+ STYLE 11: PIN 1. SOURCE 1 2. DRAIN 2 3. DRAIN 2 4. SOURCE 2 5. GATE 1 6. DRAIN 1/GATE 2 STYLE 12: PIN 1. I/O 2. GROUND 3. I/O 4. I/O 5. VCC 6. I/O STYLE 13: PIN 1. GATE 1 2. SOURCE 2 3. GATE 2 4. DRAIN 2 5. SOURCE 1 6. DRAIN 1 STYLE 14: PIN 1. ANODE 2. SOURCE 3. GATE 4. CATHODE/DRAIN 5. CATHODE/DRAIN 6. CATHODE/DRAIN STYLE 15: PIN 1. ANODE 2. SOURCE 3. GATE 4. DRAIN 5. N/C 6. CATHODE STYLE 16: PIN 1. ANODE/CATHODE 2. BASE 3. EMITTER 4. COLLECTOR 5. ANODE 6. CATHODE STYLE 17: PIN 1. EMITTER 2. BASE 3. ANODE/CATHODE 4. ANODE 5. CATHODE 6. COLLECTOR GENERIC MARKING DIAGRAM* RECOMMENDED SOLDERING FOOTPRINT* 6X 0.60 XXXAYWG G 1 6X 3.20 XXX A Y W G 0.95 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98ASB14888C TSOP−6 1 IC 0.95 XXX MG G = Specific Device Code =Assembly Location = Year = Work Week = Pb−Free Package STANDARD XXX = Specific Device Code M = Date Code G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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