NTGS4111PT1

NTGS4111P Power MOSFET −30 V, −4.7 A, Single P−Channel, TSOP−6 Features • • • • • Leading −30 V Trench Process for Low RDS(on) Low Profile Package Suitable for Portable Applications Surface Mount TSOP−6 Package Saves Board Space Improved Efficiency for Battery Applications Pb−Free Package is Available http://onsemi.com V(BR)DSS −30 V RDS(on) TYP 38 mW @ −10 V 68 mW @ −4.5 V P−Channel 1256 ID MAX −4.7 A Applications • Battery Management and Switching • Load Switching • Battery Protection MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Drain−to−Source Voltage Gate−to−Source Voltage Continuous Drain Current (Note 1) Steady TA = 25°C State TA = 85°C t≤5s Power Dissipation (Note 1) TA = 25°C PD Steady TA = 25°C State t≤5s Continuous Drain Current (Note 2) Power Dissipation (Note 2) Pulsed Drain Current Steady TA = 25°C State TA = 85°C TA = 25°C tp = 10 ms ID Symbol VDSS VGS ID Value −30 ±20 −3.7 −2.7 −4.7 1.25 2.0 −2.6 −1.9 PD IDM TJ, TSTG IS TL 0.63 −15 −55 to 150 −1.7 260 W A °C A °C TG M Unit V V A 4 3 W MARKING DIAGRAM & PIN ASSIGNMENT Drain Drain Source 654 A 1 TSOP−6 CASE 318G STYLE 1 TG M G G 123 Drain Drain Gate = Specific Device Code = Date Code* = Pb−Free Package Operating Junction and Storage Temperature Source Current (Body Diode) Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) G THERMAL RESISTANCE RATINGS Rating Junction−to−Ambient – Steady State (Note 1) Junction−to−Ambient – t ≤ 5 s (Note 1) Junction−to−Ambient – Steady State (Note 2) Symbol RqJA RqJA RqJA Max 100 62.5 200 Unit °C/W (Note: Microdot may be in either location) *Date Code orientation may vary depending upon manufacturing location. ORDERING INFORMATION Device NTGS4111PT1 NTGS4111PT1G Package TSOP−6 Shipping † 3000 / Tape & Reel Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Surface−mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces). 2. Surface−mounted on FR4 board using the minimum recommended pad size (Cu area = 0.006 in sq). TSOP−6 3000 / Tape& Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2006 1 April, 2006 − Rev. 2 Publication Order Number: NTGS4111P/D NTGS4111P ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage Drain−to−Source Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current V(BR)DSS V(BR)DSS/TJ IDSS VGS = 0 V, VDS = −24 V TJ = 25°C TJ = 125°C VGS = 0 V, ID = −250 mA −30 −17 −1.0 −100 ±100 nA V mV/°C mA Symbol Test Condition Min Typ Max Unit Gate−to−Source Leakage Current ON CHARACTERISTICS (Note 3) Gate Threshold Voltage Negative Threshold Temperature Coefficient Drain−to−Source On Resistance IGSS VDS = 0 V, VGS = ±20 V VGS = VDS, ID = −250 mA VGS = −10 V, ID = −3.7 A VGS = −4.5 V, ID = −2.7 A VGS(TH) VGS(TH)/TJ RDS(on) −1.0 5.0 38 68 6.0 −3.0 V mV/°C mW 60 110 Forward Transconductance gFS VDS = −10 V, ID = −3.7 A S CHARGES, CAPACITANCES AND GATE RESISTANCE Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Threshold Gate Charge Gate−to−Source Charge Gate−to−Drain Charge CISS COSS CRSS QG(TOT) QG(TH) QGS QGD VGS = −10 V, VDD = −15 V, ID = −3.7 A VGS = 0 V, f = 1.0 MHz, VDS = −15 V 750 140 130 15.25 0.8 2.6 3.4 32 nC pF SWITCHING CHARACTERISTICS, VGS = −10 V (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(ON) tr td(OFF) tf VGS = −10 V, VDD = −15 V, ID = −1.0 A, RG = 6.0 W 9.0 9.0 38 22 17 18 85 45 ns SWITCHING CHARACTERISTICS, VGS = −4.5 V (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time DRAIN − SOURCE DIODE CHARACTERISTICS Characteristic Forward Diode Voltage Symbol VDS Test Condition VGS = 0 V, IS = −1.0 A TJ = 25°C TJ = 125°C Min Typ −0.76 −0.60 24 VGS = 0 V dIS/dt = 100 A/ms, IS = −1.0 A 9.0 15 12 nC 60 ns Max −1.2 Unit V td(ON) tr td(OFF) tf VGS = −4.5 V, VDD = −15 V, ID = −1.0 A, RG = 6.0 W 11 15 28 22 20 28 56 50 ns Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Charge tRR ta tb QRR 3. Pulse Test: pulse width v 300 ms, duty cycle v 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 NTGS4111P TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) 12 −ID, DRAIN CURRENT (AMPS) 11 10 9 8 7 6 5 4 3 2 1 0 0 0.4 0.8 1.2 TJ = 25°C 1.6 2 2.4 2.8 3.2 −5 V −10V −4.5 V −4.2 V −8 V −6 V −5.5 V −3.6 V −3.4 V −3.2 V −3 V 3.6 4 −3.8 V 12 −4 V −ID, DRAIN CURRENT (AMPS) 11 10 9 8 7 6 5 4 3 2 1 0 1 25°C TJ = −55°C 1.5 2 2.5 3 3.5 4 4.5 −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 5 VDS ≥ −10 V 100°C −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0.1 Figure 2. Transfer Characteristics 0.2 TJ = 25°C ID = −3.7 A TJ = 25°C VGS = −4.5 V 0.05 VGS = −10 V 0.1 0 2 3 4 5 6 7 8 9 10 −VGS, GATE VOLTAGE (VOLTS) 0 2.0 3.0 −ID, DRAIN CURRENT (AMPS) 4.0 Figure 3. On−Resistance vs. Gate−to−Source Voltage 1.5 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) ID = −3.7 A VGS = −10 V 100000 Figure 4. On−Resistance vs. Drain Current and Gate Voltage VGS = 0 V −IDSS, LEAKAGE CURRENT (nA) TJ = 150°C 10000 1.0 1000 TJ = 100°C 0.5 −50 100 −25 0 25 50 75 100 125 150 5 TJ, JUNCTION TEMPERATURE (°C) 10 15 20 25 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 30 Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage http://onsemi.com 3 NTGS4111P TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) TJ = 25°C −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 1400 Ciss 1300 1200 C rss 1100 1000 900 800 700 600 500 400 300 Coss 200 100 VDS = 0 V VGS = 0 V Crss 0 5 5 15 10 0 10 −VGS −VDS 12 QT VDS VGS 10 8 6 4 2 0 0 1 2 QGS QGD 20 C, CAPACITANCE (pF) Ciss 10 20 25 30 0 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Qg, TOTAL GATE CHARGE (nC) ID = −3.7 A TJ = 25°C −GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation Figure 8. Gate−to−Source Voltage vs. Total Gate Charge 100 −IS, SOURCE CURRENT (AMPS) −I D, DRAIN CURRENT (AMPS) 10 VGS = 0 V TJ = 150°C 10 100 ms 1 ms VGS = −20 V SINGLE PULSE TC = 25°C RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 10 ms 1 1 TJ = 100°C TJ = 25°C TJ = −55°C 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 0.1 dc 0.01 0.1 1 10 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 100 0.1 0.3 −VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 9. Maximum Rated Forward Biased Safe Operating Area Rthja(t), EFFECTIVE TRANSIENT THERMAL RESPONSE 1 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 Figure 10. Diode Forward Voltage vs. Current 0.001 Single Pulse 1E−06 1E−05 1E−04 1E−03 1E−02 t, TIME (s) 1E−01 1E+00 1E+01 1E+02 1E+03 0.0001 1E−07 Figure 11. FET Thermal Response http://onsemi.com 4 NTGS4111P PACKAGE DIMENSIONS TSOP−6 CASE 318G−02 ISSUE P D 6 5 1 2 4 3 HE E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MILLIMETERS NOM MAX 1.00 1.10 0.06 0.10 0.38 0.50 0.18 0.26 3.00 3.10 1.50 1.70 0.95 1.05 0.40 0.60 2.75 3.00 10° − INCHES NOM 0.039 0.002 0.014 0.007 0.118 0.059 0.037 0.016 0.108 − b e q 0.05 (0.002) A1 A L c DIM A A1 b c D E e L HE q MIN 0.90 0.01 0.25 0.10 2.90 1.30 0.85 0.20 2.50 0° MIN 0.035 0.001 0.010 0.004 0.114 0.051 0.034 0.008 0.099 0° MAX 0.043 0.004 0.020 0.010 0.122 0.067 0.041 0.024 0.118 10° STYLE 1: PIN 1. DRAIN 2. DRAIN 3. GATE 4. SOURCE 5. DRAIN 6. DRAIN SOLDERING FOOTPRINT* 2.4 0.094 1.9 0.075 0.95 0.037 0.95 0.037 0.7 0.028 1.0 0.039 SCALE 10:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 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