NTGS5120PT1G

DATA SHEET www.onsemi.com MOSFET – Power, Single, P-Channel, TSOP-6 V(BR)DSS -60 V, -2.9 A RDS(ON) MAX ID MAX 111 mW @ −10 V −60 V −2.9 A 142 mW @ −4.5 V NTGS5120P, NVGS5120P P−Channel Features 1 2 5 6 • 60 V BVds, Low RDS(on) in TSOP−6 Package • 4.5 V Gate Rating • NVGS Prefix for Automotive and Other Applications Requiring • Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant 3 4 MARKING DIAGRAM Applications • High Side Load Switch • Power Switch for Printers, Communication Equipment MAXIMUM RATINGS (TJ = 25°C unless otherwise stated) Parameter 1 TSOP−6 CASE 318G STYLE 1 XX MG G 1 Symbol Value Unit Drain−to−Source Voltage VDSS −60 V Gate−to−Source Voltage VGS $20 V ID −2.5 XX = Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) A PIN ASSIGNMENT Continuous Drain Current (Note 1) Power Dissipation (Note 1) Steady State TA = 25°C TA = 85°C −2.0 tv5s TA = 25°C −2.9 Steady State PD W Power Dissipation (Note 2) Pulsed Drain Current 1.4 TA = 25°C Steady State 1.1 TA = 25°C tv5s Continuous Drain Current (Note 2) Drain Drain Source 6 5 4 ID TA = 85°C TA = 25°C tp = 10 ms Operating Junction and Storage Temperature Lead Temperature for Soldering Purposes (1/8” from case for 10 s) −1.8 A −1.3 1 2 3 Drain Drain Gate PD 0.6 W IDM −20 A TJ, TSTG −55 to 150 °C TL 260 °C ORDERING INFORMATION See detailed ordering and shipping information ion page 5 of this data sheet. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Surface−mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces) 2. Surface−mounted on FR4 board using the minimum recommended pad size. © Semiconductor Components Industries, LLC, 2014 September, 2021 − Rev. 2 1 Publication Order Number: NTGS5120P/D NTGS5120P, NVGS5120P THERMAL RESISTANCE MAXIMUM RATINGS Symbol Value Junction−to−Ambient – Steady State (Note 3) Parameter RqJA 102 Junction−to−Ambient – t = 5 s (Note 3) RqJA 77.6 Junction−to−Ambient – Steady State (Note 4) RqJA 200 Unit °C/W 3. Surface−mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces) 4. Surface−mounted on FR4 board using the minimum recommended pad size. ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Min V(BR)DSS VGS = 0 V, ID = −250 mA −60 Typ Max Unit OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage Zero Gate Voltage Drain Current Gate−to−Source Leakage Current IDSS VGS = 0 V, VDS = −48 V IGSS V TJ = 25°C −1.0 TJ = 125°C −5.0 mA VDS = 0 V, VGS = ±12 V $100 nA VDS = 0 V, VGS = ±20 V $200 nA −3.0 V 72 111 mW VGS = −4.5 V, ID = −2.5 A 88 142 VDS = −5.0 V, ID = −6.0 A 10.1 S 942 pF ON CHARACTERISTICS (Note 5) Gate Threshold Voltage VGS(TH) VGS = VDS, ID = −250 mA Drain−to−Source On Resistance RDS(on) VGS = −10 V, ID = −2.9 A Forward Transconductance gFS −1.0 CHARGES, CAPACITANCES AND GATE RESISTANCE Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS 48 Total Gate Charge QG(TOT) 18.1 Threshold Gate Charge QG(TH) 1.2 Gate−to−Source Charge QGS Gate−to−Drain Charge QGD 3.6 td(ON) 8.7 VGS = 0 V, f = 1 MHz, VDS = −30 V VGS = −10 V, VDS = −30 V; ID = −2.9 A 72 nC 2.7 SWITCHING CHARACTERISTICS (Note 6) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time tr VGS = −10 V, VDS = −30 V, ID = −1.0 A, RG = 6.0 W td(OFF) tf ns 4.9 38 12.8 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage VSD Reverse Recovery Time tRR Charge Time Reverse Recovery Charge VGS = 0 V, IS = −0.9 A TJ = 25°C VGS = 0 V, dIS/dt = 100 A/ms, IS = −0.9 A ta QRR −0.75 −1.0 V 18.3 ns 15.5 ns 15.1 nC Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 5. Pulse Test: pulse width v 300 ms, duty cycle v 2% 6. Switching characteristics are independent of operating junction temperatures www.onsemi.com 2 NTGS5120P, NVGS5120P TYPICAL CHARACTERISTICS −2.8 V 2.5 −3.2 V −ID, DRAIN CURRENT (A) −10 V 5.0 TJ = 25°C 3.0 −4.5 V −2.6 V 2.0 1.5 1.0 −2.4 V 0.5 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) −3.0 V VGS = −2.2 V 0 0.5 1.0 1.5 2.0 2.5 3.0 3.0 2.0 TJ = 25°C 1.0 TJ = 125°C 0.4 0.9 1.4 TJ = −55°C 1.9 2.4 2.9 3.4 −VGS, GATE−TO−SOURCE VOLTAGE (V) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics ID = −2.9 A TJ = 25°C 0.18 0.16 0.14 0.12 0.10 0.08 0.06 2.0 4.0 −VDS, DRAIN−TO−SOURCE VOLTAGE (V) 0.20 0.04 VDS ≥ −10 V 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) −ID, DRAIN CURRENT (A) 3.5 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 −VGS, GATE−TO−SOURCE VOLTAGE (V) 0.10 3.9 TJ = 25°C VGS = −4.5 V 0.09 0.08 VGS = −10 V 0.07 0.06 0.05 0.04 1.0 2.0 3.0 4.0 5.0 6.0 7.0 −ID, DRAIN CURRENT (A) Figure 3. On−Resistance vs. Gate Voltage Figure 4. On−Resistance vs. Drain Current and Gate Voltage VGS = 0 V ID = −2.9 A VGS = −4.5 V 1.6 −IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 10,000 1.8 1.4 1.2 1.0 TJ = 150°C 1000 TJ = 125°C 100 0.8 0.6 −50 −25 0 25 50 75 100 125 150 10 10 TJ, JUNCTION TEMPERATURE (°C) 20 30 40 50 −VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage www.onsemi.com 3 60 NTGS5120P, NVGS5120P 1300 1200 1100 1000 900 800 700 600 500 400 300 Coss 200 100 0 Crss 0 VGS = 0 V TJ = 25°C Ciss 10 −VGS, GATE−TO−SOURCE VOLTAGE (V) C, CAPACITANCE (pF) TYPICAL CHARACTERISTICS 20 40 30 8.0 7.0 6.0 5.0 4.0 3.0 Qgd Qgs TJ = 25°C ID = −2.9 A Vds = −30 V 2.0 1.0 0 0 2.0 4.0 6.0 8.0 10 12 14 16 QG, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation Figure 8. Gate−to−Source Voltage vs. Total Charge 18 1.4 −IS, SOURCE CURRENT (A) VDD = −30 V ID = −1.0 A VGS = −10 V td(off) 100 tf td(on) 10 tr 1.0 10 1.0 0.8 0.6 0.4 0.2 0 100 VGS = 0 V TJ = 25°C 1.2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 RG, GATE RESISTANCE (W) −VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current 100 ID, DRAIN CURRENT (AMPS) t, TIME (ns) Qt −VDS, DRAIN−TO−SOURCE VOLTAGE (V) 1000 1.0 10 9.0 10 ms 10 100 ms 1 0.1 0.01 0.1 1 ms 0 V ≤ VGS ≤ 20 V SINGLE PULSE TC = 25°C 10 ms RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT dc 10 1 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 11. Maximum Rated Forward Biased Safe Operating Area www.onsemi.com 4 100 NTGS5120P, NVGS5120P Rthja(t), TRANSIENT THERMAL RESPONSE (°C/W) TYPICAL CHARACTERISTICS 1000 100 D = 0.5 10 1 0.2 0.1 0.05 0.02 0.01 0.1 Single Pulse 0.01 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 t, PULSE TIME (s) Figure 12. Thermal Response Table 1. ORDERING INFORMATION Part Number Marking (XX) Package Shipping† NTGS5120PT1G P6 TSOP−6 (Pb−Free) 3000 / Tape & Reel NVGS5120PT1G VP6 TSOP−6 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 5 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSOP−6 CASE 318G−02 ISSUE V 1 SCALE 2:1 D H ÉÉ ÉÉ 6 E1 1 NOTE 5 5 2 L2 4 GAUGE PLANE E 3 L b SEATING PLANE C DETAIL Z e DIM A A1 b c D E E1 e L L2 M c A 0.05 M DATE 12 JUN 2012 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSIONS D AND E1 ARE DETERMINED AT DATUM H. 5. PIN ONE INDICATOR MUST BE LOCATED IN THE INDICATED ZONE. A1 DETAIL Z MIN 0.90 0.01 0.25 0.10 2.90 2.50 1.30 0.85 0.20 0° MILLIMETERS NOM MAX 1.00 1.10 0.06 0.10 0.38 0.50 0.18 0.26 3.00 3.10 2.75 3.00 1.50 1.70 0.95 1.05 0.40 0.60 0.25 BSC 10° − STYLE 1: PIN 1. DRAIN 2. DRAIN 3. GATE 4. SOURCE 5. DRAIN 6. DRAIN STYLE 2: PIN 1. EMITTER 2 2. BASE 1 3. COLLECTOR 1 4. EMITTER 1 5. BASE 2 6. COLLECTOR 2 STYLE 3: PIN 1. ENABLE 2. N/C 3. R BOOST 4. Vz 5. V in 6. V out STYLE 4: PIN 1. N/C 2. V in 3. NOT USED 4. GROUND 5. ENABLE 6. LOAD STYLE 5: PIN 1. EMITTER 2 2. BASE 2 3. COLLECTOR 1 4. EMITTER 1 5. BASE 1 6. COLLECTOR 2 STYLE 6: PIN 1. COLLECTOR 2. COLLECTOR 3. BASE 4. EMITTER 5. COLLECTOR 6. COLLECTOR STYLE 7: PIN 1. COLLECTOR 2. COLLECTOR 3. BASE 4. N/C 5. COLLECTOR 6. EMITTER STYLE 8: PIN 1. Vbus 2. D(in) 3. D(in)+ 4. D(out)+ 5. D(out) 6. GND STYLE 9: PIN 1. LOW VOLTAGE GATE 2. DRAIN 3. SOURCE 4. DRAIN 5. DRAIN 6. HIGH VOLTAGE GATE STYLE 10: PIN 1. D(OUT)+ 2. GND 3. D(OUT)− 4. D(IN)− 5. VBUS 6. D(IN)+ STYLE 11: PIN 1. SOURCE 1 2. DRAIN 2 3. DRAIN 2 4. SOURCE 2 5. GATE 1 6. DRAIN 1/GATE 2 STYLE 12: PIN 1. I/O 2. GROUND 3. I/O 4. I/O 5. VCC 6. I/O STYLE 13: PIN 1. GATE 1 2. SOURCE 2 3. GATE 2 4. DRAIN 2 5. SOURCE 1 6. DRAIN 1 STYLE 14: PIN 1. ANODE 2. SOURCE 3. GATE 4. CATHODE/DRAIN 5. CATHODE/DRAIN 6. CATHODE/DRAIN STYLE 15: PIN 1. ANODE 2. SOURCE 3. GATE 4. DRAIN 5. N/C 6. CATHODE STYLE 16: PIN 1. ANODE/CATHODE 2. BASE 3. EMITTER 4. COLLECTOR 5. ANODE 6. CATHODE STYLE 17: PIN 1. EMITTER 2. BASE 3. ANODE/CATHODE 4. ANODE 5. CATHODE 6. COLLECTOR GENERIC MARKING DIAGRAM* RECOMMENDED SOLDERING FOOTPRINT* 6X 0.60 XXXAYWG G 1 6X 3.20 XXX A Y W G 0.95 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98ASB14888C TSOP−6 1 IC 0.95 XXX MG G = Specific Device Code =Assembly Location = Year = Work Week = Pb−Free Package STANDARD XXX = Specific Device Code M = Date Code G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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