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NTHD3100C

NTHD3100C

  • 厂商:

    ONSEMI(安森美)

  • 封装:

  • 描述:

    NTHD3100C - Power MOSFET 20 V, 3.9 A /−4.4 A, Complementary ChipFET - ON Semiconductor

  • 数据手册
  • 价格&库存
NTHD3100C 数据手册
NTHD3100C Power MOSFET 20 V, +3.9 A /−4.4 A, Complementary ChipFETt Features AND PIN A • • • • • • • • • • Complementary N−Channel and P−Channel MOSFET Small Size, 40% Smaller than TSOP−6 Package Leadless SMD Package Provides Great Thermal Characteristics Trench P−Channel for Low On Resistance Low Gate Charge N−Channel for Test Switching Pb−Free Packages are Available http://onsemi.com V(BR)DSS N−Channel 20 V P−Channel −20 V RDS(on) Typ 58 mW @ 4.5 V 77 mW @ 2.5 V 64 mW @ −4.5 V 85 mW @ −2.5 V S2 ID MAX 3.9 A −4.4 A Applications DC−DC Conversion Circuits Load Switch Applications Requiring Level Shift Drive Small Brushless DC Motors Ideal for Power Management Applications in Portable, Battery Powered Products D1 G1 S1 G2 D2 P−Channel MOSFET MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Parameter Drain−to−Source Voltage Gate−to−Source Voltage N−Ch P−Ch N−Channel Continuous Drain Current (Note 1) P−Channel Continuous Drain Current (Note 1) Power Dissipation (Note 1) Steady State t ≤ 10 s Steady State t ≤ 10 s Steady State t≤5s Pulsed Drain Current (Note 1) N−Ch P−Ch t = 10 ms t = 10 ms TJ, TSTG IS TL IDM TA = 25°C TA = 85°C TA = 25°C TA = 25°C TA = 85°C TA = 25°C PD TA = 25°C 3.1 12 −13 −55 to 150 2.5 260 °C A °C A ID ID Symbol VDSS VGS Value 20 "12 "8.0 2.9 2.1 3.9 −3.2 −2.3 −4.4 1.1 W D1 D1 D2 D2 8 7 6 5 Unit V V N−Channel MOSFET 8 A 1 ChipFET CASE 1206A STYLE 2 A PIN CONNECTIONS 1 2 3 4 MARKING DIAGRAM 1 2 3 4 C9 M G 8 7 6 5 S1 G1 S2 G2 Operating Junction and Storage Temperature Source Current (Body Diode) Lead Temperature for Soldering Purposes (1/8″ from case for 10 seconds) C9 M G = Specific Device Code = Month Code = Pb−Free Package Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface−mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces). ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. © Semiconductor Components Industries, LLC, 2006 March, 2006 − Rev. 3 1 Publication Order Number: NTHD3100C/D NTHD3100C THERMAL RESISTANCE RATINGS Parameter Junction−to−Ambient − Steady State (Note 2) Junction−to−Ambient − t ≤ 10 s (Note 2) Symbol RqJA RqJA Max 113 60 Unit °C/W °C/W 2. Surface−mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces). ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameter OFF CHARACTERISTICS (Note 3) Drain−to−Source Breakdown Voltage V(BR)DSS IDSS N P Zero Gate Voltage Drain Current N P N P Gate−to−Source Leakage Current IGSS N P ON CHARACTERISTICS (Note 3) Gate Threshold Voltage VGS(TH) RDS(on) N P Drain−to−Source On Resistance N P N P Forward Transconductance gFS N P CHARGES AND CAPACITANCES Input Capacitance CISS COSS CRSS QG(TOT) QG(TH) QGS QGD N P Output Capacitance N P Reverse Transfer Capacitance N P Total Gate Charge N P Threshold Gate Charge N P Gate−to−Source Gate Charge N P Gate−to−Drain “Miller” Charge N P 3. Pulse Test: pulse width v 250 ms, duty cycle v 2%. f = 1 MHz, VGS = 0 V VDS = 10 V VDS = −10 V VDS = 10 V VDS = −10 V VDS = 10 V VDS = −10 V VGS = 4.5 V, VDS = 10 V, ID = 2.9 A VGS = −4.5 V, VDS = −10 V, ID = −3.2 A VGS = 4.5 V, VDS = 10 V, ID = 2.9 A VGS = −4.5 V, VDS = −10 V, ID = −3.2 A VGS = 4.5 V, VDS = 10 V, ID = 2.9 A VGS = −4.5 V, VDS = −10 V, ID = −3.2 A VGS = 4.5 V, VDS = 10 V, ID = 2.9 A VGS = −4.5 V, VDS = −10 V, ID = −3.2 A 165 680 80 100 25 70 2.3 7.4 0.2 0.6 0.4 1.4 0.7 2.5 nC pF VGS = VDS ID = 250 mA ID = −250 mA 0.6 −.45 58 64 77 85 6.0 8.0 1.2 −1.5 80 80 115 110 S mW V VGS = 0 V VGS = 0 V, VDS = 16 V VGS = 0 V, VDS = −16 V VGS = 0 V, VDS = 16 V VGS = 0 V, VDS = −16 V ID = 250 mA ID = −250 mA TJ = 25 °C TJ = 125 °C 20 −20 1.0 −1.0 5.0 −5.0 ±100 ±100 nA mA V Symbol N/P Test Conditions Min Typ Max Unit VDS = 0 V, VGS = ±12 V VDS = 0 V, VGS = ±8.0 V VGS = 4.5 V , ID = 2.9 A VGS = −4.5 V , ID = −3.2 A VGS = 2.5 V , ID = 2.3 A VGS = −2.5 V, ID = −2.2 A VDS = 10 V, ID = 2.9 A VDS = −10 V , ID = −3.2 A http://onsemi.com 2 NTHD3100C ELECTRICAL CHARACTERISTICS (continued) (TJ = 25°C unless otherwise noted) Parameter SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(ON) tr td(OFF) tf td(ON) tr td(OFF) tf VSD tRR ta tb QRR N P Reverse Recovery Time N P Charge Time N P Discharge Time N P Reverse Recovery Charge N P 4. Switching characteristics are independent of operating junction temperatures. VGS = 0 V, dIS / dt = 100 A/ms IS = 2.5 A IS = −2.5 A IS = 1.5 A IS = −1.5 A IS = 1.5 A IS = −1.5 A IS = 1.5 A IS = −1.5 A IS = 1.5 A IS = −1.5 A P VGS = −4.5 V, VDD = −10 V, ID = −3.2 A, RG = 2.5 W N VGS = 4.5 V, VDD = 10 V, ID = 2.9 A, RG = 2.5 W 6.3 10.7 9.6 1.5 5.8 11.7 16 12.4 ns Symbol N/P Test Conditions Min Typ Max Unit DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage VGS = 0 V, TJ = 25 °C 0.8 −0.8 12.5 13.5 9.0 9.5 3.5 4.0 6.0 6.5 nC 1.15 −1.2 ns V http://onsemi.com 3 NTHD3100C TYPICAL N−CHANNEL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) 8 ID, DRAIN CURRENT (AMPS) VGS = 5 V to 3 V VGS = 2.4 V 6 2.2 V 2V 8 ID, DRAIN CURRENT (AMPS) TJ = 25°C VDS ≥ 10 V 6 4 1.8 V 4 2 1.6 V 1.4 V 2 TC = −55°C 25°C 100°C 3 0 0 1 2 3 4 5 6 7 8 9 10 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 0 0 0.5 1 1.5 2 2.5 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0.15 ID = 2.9 A TJ = 25°C 0.1 0.1 Figure 2. Transfer Characteristics TJ = 25°C VGS = 2.5 V 0.07 VGS = 4.5 V 0.05 0 0 3 5 2 4 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 1 6 0.04 1 3 5 7 ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance vs. Gate−to−Source Voltage 1.7 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 1.5 1.3 1.1 0.9 0.7 −50 100 Figure 4. On−Resistance vs. Drain Current and Gate Voltage ID = 2.9 A VGS = 4.5 V IDSS, LEAKAGE (nA) VGS = 0 V TJ = 100°C 10 −25 0 25 50 75 100 125 150 1 2 4 6 8 10 12 14 16 18 20 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage http://onsemi.com 4 NTHD3100C TYPICAL N−CHANNEL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 400 CISS C, CAPACITANCE (pF) 300 CRSS 200 5 4 VDS 3 2 1 0 QGS QGD VGS 9 6 3 0 3 15 12 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VDS = 0 V VGS = 0 V TJ = 25°C QG 100 COSS ID = 2.9 A TJ = 25°C 0 0.5 1 1.5 2 2.5 0 10 5 VGS 0 VDS 5 10 15 20 Qg, TOTAL GATE CHARGE (nC) GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation 100 IS, SOURCE CURRENT (AMPS) VDS = 10 V ID = 2.9 A VGS = 4.5 V t, TIME (ns) 5 4 3 2 1 Figure 8. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge VGS = 0 V TJ = 25°C 10 td(off) td(on) tr 1 1 tf 10 RG, GATE RESISTANCE (OHMS) 100 0 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current http://onsemi.com 5 NTHD3100C TYPICAL P−CHANNEL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) 9 −ID, DRAIN CURRENT (AMPS) 8 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 −1.8 V −1.6 V −1.4 V 7 8 9 10 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS = −5 V to −3.6 V VGS = −3 V −2.6 V TJ = 25°C −2.4 V −ID, DRAIN CURRENT (AMPS) 9 8 7 6 5 4 3 2 1 0 0 TC = −55°C 25°C 100°C VDS ≥ −10 V −2.2 V −2 V 3.5 0.5 1 1.5 2 2.5 3 −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 11. On−Region Characteristics RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0.2 0.2 Figure 12. Transfer Characteristics 0.175 0.15 ID = −3.2 A TJ = 25°C TJ = 25°C 0.175 0.15 VGS = −2.5 V 0.125 0.1 0.125 0.1 VGS = −4.5 V 0.075 0.05 1 3 5 2 4 −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 6 0.075 0.05 2 3 4 5 6 7 8 −ID, DRAIN CURRENT (AMPS) Figure 13. On−Resistance vs. Gate−to−Source Voltage 1.4 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 1.3 1.2 1.1 1 0.9 0.8 0.7 −50 −25 0 25 50 75 100 125 150 10 2 ID = −3.2 A VGS = −4.5 V −IDSS, LEAKAGE (A) 1000 Figure 14. On−Resistance vs. Drain Current and Gate Voltage VGS = 0 V TJ = 100°C 100 4 6 8 10 12 14 16 18 20 −TJ, JUNCTION TEMPERATURE (°C) −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 15. On−Resistance Variation with Temperature Figure 16. Drain−to−Source Leakage Current vs. Voltage http://onsemi.com 6 NTHD3100C TYPICAL P−CHANNEL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) VGS = 0 V Ciss TJ = 25°C −VGS, GATE−TO−SOURCE VOLTAGE (V) 1500 1200 900 VDS = 0 V 600 300 Coss 0 5 −VGS 0 −VDS 5 10 15 20 Crss QT 4 −V DS 3 2 1 0 ID = −3.2 A TJ = 25°C 0 2 4 6 8 Qgs Qgd −VGS 8 6 4 2 0 −VDS, DRAIN−TO−SOURCE VOLTAGE (V) 5 10 C, CAPACITANCE (pF) Qg, TOTAL GATE CHARGE (nC) GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 17. Capacitance Variation 1000 −IS, SOURCE CURRENT (AMPS) VDS = −10 V ID = −3.2 A VGS = −4.5 V 100 t, TIME (ns) td(off) tf tr 10 td(on) 5 Figure 18. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge VGS = 0 V TJ = 25°C 4 3 2 1 0 0.3 1 1 10 RG, GATE RESISTANCE (OHMS) 100 0.6 0.9 1.2 −VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 19. Resistive Switching Time Variation vs. Gate Resistance Figure 20. Diode Forward Voltage vs. Current DEVICE ORDERING INFORMATION Device NTHD3100CT1 NTHD3100CT1G NTHD3100CT3 NTHD3100CT3G Package ChipFET ChipFET (Pb−Free) ChipFET ChipFET (Pb−Free) Shipping † 3000 / Tape & Reel 3000 / Tape & Reel 10000 / Tape & Reel 10000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 7 NTHD3100C PACKAGE DIMENSIONS ChipFET] CASE 1206A−03 ISSUE G D 8 7 6 5 q L 5 6 3 7 2 8 1 HE 1 2 3 4 E 4 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE. 4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL AND VERTICAL SHALL NOT EXCEED 0.08 MM. 5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS. 6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD SURFACE. DIM A b c D E e e1 L HE q MILLIMETERS NOM MAX 1.05 1.10 0.30 0.35 0.15 0.20 3.05 3.10 1.65 1.70 0.65 BSC 0.55 BSC 0.28 0.35 0.42 1.80 1.90 2.00 5° NOM MIN 1.00 0.25 0.10 2.95 1.55 INCHES NOM 0.041 0.012 0.006 0.120 0.065 0.025 BSC 0.022 BSC 0.011 0.014 0.071 0.075 5° NOM MIN 0.039 0.010 0.004 0.116 0.061 MAX 0.043 0.014 0.008 0.122 0.067 0.017 0.079 e1 e b c A 0.05 (0.002) STYLE 2: PIN 1. 2. 3. 4. 5. 6. 7. 8. SOURCE 1 GATE 1 SOURCE 2 GATE 2 DRAIN 2 DRAIN 2 DRAIN 1 DRAIN 1 SOLDERING FOOTPRINT* 2.032 0.08 0.635 0.025 1.092 0.043 0.178 0.007 0.457 0.018 0.254 0.010 0.66 0.026 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ChipFET is a trademark of Vishay Siliconix. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Japan : ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Phone: 81−3−5773−3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. http://onsemi.com 8 NTHD3100C/D
NTHD3100C 价格&库存

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