AND PIN A
NTHD3100C
MOSFET – Power,
Complementary, ChipFET
20 V, +3.9 A /-4.4 A
Features
•
•
•
•
•
•
http://onsemi.com
Complementary N−Channel and P−Channel MOSFET
Small Size, 40% Smaller than TSOP−6 Package
Leadless SMD Package Provides Great Thermal Characteristics
Trench P−Channel for Low On Resistance
Low Gate Charge N−Channel for Test Switching
Pb−Free Packages are Available
RDS(on) Typ
N−Channel
20 V
58 mW @ 4.5 V
P−Channel
−20 V
64 mW @ −4.5 V
Applications
•
•
•
•
Symbol
Drain−to−Source Voltage
Gate−to−Source Voltage
N−Ch
N−Channel
Continuous Drain
Current (Note 1)
P−Channel
Continuous Drain
Current (Note 1)
Power Dissipation
(Note 1)
Unit
VDSS
20
V
VGS
"12
V
G2
TA = 25°C
ID
TA = 85°C
2.1
t ≤ 10 s
TA = 25°C
3.9
Steady
State
TA = 25°C
TA = 85°C
−2.3
t ≤ 10 s
TA = 25°C
−4.4
ID
PD
A
−3.2
W
1.1
t = 10 ms
P−Ch
t = 10 ms
Operating Junction and Storage Temperature
IDM
A
12
−13
TJ,
TSTG
−55 to
150
°C
Source Current (Body Diode)
IS
2.5
A
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 seconds)
TL
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface−mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq
[1 oz] including traces).
© Semiconductor Components Industries, LLC, 2006
May, 2019 − Rev. 3
P−Channel MOSFET
8
ChipFET
CASE 1206A
STYLE 2
1
1
PIN
CONNECTIONS
MARKING
DIAGRAM
D1
8
1
S1
1
8
D1
7
2
G1
2
7
D2
6
3
S2
3
D2
5
4
G2
4
C9
M
G
C9 M
G
3.1
N−Ch
N−Channel MOSFET
A
2.9
TA = 25°C
t≤5s
Pulsed Drain Current
(Note 1)
D2
"8.0
Steady
State
Steady
State
S2
S1
Value
P−Ch
−4.4 A
85 mW @ −2.5 V
G1
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter
3.9 A
77 mW @ 2.5 V
D1
DC−DC Conversion Circuits
Load Switch Applications Requiring Level Shift
Drive Small Brushless DC Motors
Ideal for Power Management Applications in Portable, Battery
Powered Products
ID MAX
V(BR)DSS
6
5
= Specific Device Code
= Month Code
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
Publication Order Number:
NTHD3100C/D
NTHD3100C
THERMAL RESISTANCE RATINGS
Symbol
Max
Unit
Junction−to−Ambient − Steady State (Note 2)
Parameter
RqJA
113
°C/W
Junction−to−Ambient − t ≤ 10 s (Note 2)
RqJA
60
°C/W
2. Surface−mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces).
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Parameter
Symbol
N/P
V(BR)DSS
N
Test Conditions
Min
Typ
Max
Unit
OFF CHARACTERISTICS (Note 3)
Drain−to−Source Breakdown Voltage
VGS = 0 V
P
Zero Gate Voltage Drain Current
Gate−to−Source Leakage Current
IDSS
IGSS
N
VGS = 0 V, VDS = 16 V
P
VGS = 0 V, VDS = −16 V
N
VGS = 0 V, VDS = 16 V
P
VGS = 0 V, VDS = −16 V
ID = 250 mA
20
ID = −250 mA
−20
V
1.0
TJ = 25 °C
mA
−1.0
5.0
TJ = 125 °C
−5.0
N
VDS = 0 V, VGS = ±12 V
±100
P
VDS = 0 V, VGS = ±8.0 V
±100
nA
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
VGS(TH)
N
VGS = VDS
P
Drain−to−Source On Resistance
Forward Transconductance
RDS(on)
gFS
ID = 250 mA
0.6
1.2
ID = −250 mA
−.45
−1.5
N
VGS = 4.5 V , ID = 2.9 A
58
80
P
VGS = −4.5 V , ID = −3.2 A
64
80
N
VGS = 2.5 V , ID = 2.3 A
77
115
P
VGS = −2.5 V, ID = −2.2 A
85
110
N
VDS = 10 V, ID = 2.9 A
6.0
P
VDS = −10 V , ID = −3.2 A
8.0
V
mW
S
CHARGES AND CAPACITANCES
Input Capacitance
CISS
N
VDS = 10 V
165
P
VDS = −10 V
680
VDS = 10 V
80
Output Capacitance
COSS
N
VDS = −10 V
100
Reverse Transfer Capacitance
CRSS
N
VDS = 10 V
25
P
VDS = −10 V
70
P
Total Gate Charge
Threshold Gate Charge
Gate−to−Source Gate Charge
Gate−to−Drain “Miller” Charge
QG(TOT)
f = 1 MHz, VGS = 0 V
N
VGS = 4.5 V, VDS = 10 V, ID = 2.9 A
2.3
P
VGS = −4.5 V, VDS = −10 V, ID = −3.2 A
7.4
QG(TH)
N
VGS = 4.5 V, VDS = 10 V, ID = 2.9 A
0.2
P
VGS = −4.5 V, VDS = −10 V, ID = −3.2 A
0.6
QGS
N
VGS = 4.5 V, VDS = 10 V, ID = 2.9 A
0.4
P
VGS = −4.5 V, VDS = −10 V, ID = −3.2 A
1.4
N
VGS = 4.5 V, VDS = 10 V, ID = 2.9 A
0.7
P
VGS = −4.5 V, VDS = −10 V, ID = −3.2 A
2.5
QGD
3. Pulse Test: pulse width v 250 ms, duty cycle v 2%.
http://onsemi.com
2
pF
nC
NTHD3100C
ELECTRICAL CHARACTERISTICS (continued) (TJ = 25°C unless otherwise noted)
Parameter
Symbol
N/P
Test Conditions
Min
Typ
Max
Unit
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
td(ON)
tr
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
N
VGS = 4.5 V, VDD = 10 V,
ID = 2.9 A, RG = 2.5 W
td(OFF)
Fall Time
10.7
9.6
tf
1.5
td(ON)
5.8
tr
td(OFF)
Fall Time
ns
6.3
VGS = −4.5 V, VDD = −10 V,
ID = −3.2 A, RG = 2.5 W
P
tf
11.7
16
12.4
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
VSD
N
IS = 2.5 A
0.8
1.15
IS = −2.5 A
−0.8
−1.2
N
IS = 1.5 A
12.5
P
IS = −1.5 A
13.5
N
IS = 1.5 A
9.0
IS = −1.5 A
9.5
IS = 1.5 A
3.5
P
IS = −1.5 A
4.0
N
IS = 1.5 A
6.0
P
IS = −1.5 A
6.5
P
Reverse Recovery Time
Charge Time
tRR
ta
P
Discharge Time
Reverse Recovery Charge
tb
QRR
N
VGS = 0 V, TJ = 25 °C
VGS = 0 V,
dIS / dt = 100 A/ms
4. Switching characteristics are independent of operating junction temperatures.
http://onsemi.com
3
V
ns
nC
NTHD3100C
TYPICAL N−CHANNEL PERFORMANCE CURVES
(TJ = 25°C unless otherwise noted)
VGS = 5 V to 3 V
VGS = 2.4 V
2V
2.2 V
6
8
TJ = 25°C
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
8
4
1.8 V
2
1.6 V
1.4 V
1
3
4
5
6
7
4
2
8
9
10
0.5
1
1.5
2
2.5
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
ID = 2.9 A
TJ = 25°C
0.1
0.05
0
0
1
2
4
3
5
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
6
0
TJ = 25°C
VGS = 2.5 V
0.07
VGS = 4.5 V
0.04
3
1
5
7
ID, DRAIN CURRENT (AMPS)
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
100
ID = 2.9 A
VGS = 4.5 V
VGS = 0 V
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
3
0.1
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
1.5
100°C
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0.15
1.7
TC = −55°C
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
2
6
25°C
0
0
VDS ≥ 10 V
1.3
1.1
TJ = 100°C
10
0.9
0.7
−50
−25
0
25
50
75
100
125
150
1
2
4
6
8
10
12
14
16
18
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
http://onsemi.com
4
20
NTHD3100C
TYPICAL N−CHANNEL PERFORMANCE CURVES
C, CAPACITANCE (pF)
CISS
VDS = 0 V
VGS = 0 V
TJ = 25°C
300
CRSS
200
100
COSS
0
10
5
VGS
0
VDS
5
10
15
20
5
12
4
VDS
9
0
ID = 2.9 A
TJ = 25°C
0
0.5
t, TIME (ns)
IS, SOURCE CURRENT (AMPS)
tf
1
1
10
1.5
2
0
3
2.5
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
VGS = 0 V
TJ = 25°C
4
3
2
1
0
0.3
100
1
3
Qg, TOTAL GATE CHARGE (nC)
5
td(off)
td(on)
6
1
100
tr
QGD
QGS
2
Figure 7. Capacitance Variation
10
VGS
3
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VDS = 10 V
ID = 2.9 A
VGS = 4.5 V
15
QG
0.4
0.5
0.6
0.7
0.8
0.9
RG, GATE RESISTANCE (OHMS)
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
http://onsemi.com
5
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
400
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
(TJ = 25°C unless otherwise noted)
1.0
NTHD3100C
TYPICAL P−CHANNEL PERFORMANCE CURVES
(TJ = 25°C unless otherwise noted)
8
7
6
−2.4 V
−2.2 V
5
4
−2 V
3
2
−1.8 V
1
−1.6 V
−1.4 V
0
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
9
TJ = 25°C
−ID, DRAIN CURRENT (AMPS)
VGS = −5 V to −3.6 V
VGS = −3 V
−2.6 V
1
2
3
4
5
6
7
8
9
VDS ≥ −10 V
8
7
6
5
4
3
TC = −55°C
2
1
25°C
10
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
1
3
0.5
1.5
2
2.5
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 11. On−Region Characteristics
Figure 12. Transfer Characteristics
0.2
0
ID = −3.2 A
TJ = 25°C
0.175
0.2
3.5
TJ = 25°C
0.175
0.15
0.15
VGS = −2.5 V
0.125
0.125
0.1
0.1
VGS = −4.5 V
0.075
0.075
0.05
1
2
3
4
5
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
6
0.05
2
4
6
5
7
8
Figure 14. On−Resistance vs. Drain Current
and Gate Voltage
1000
1.4
ID = −3.2 A
VGS = −4.5 V
VGS = 0 V
−IDSS, LEAKAGE (A)
1.3
3
−ID, DRAIN CURRENT (AMPS)
Figure 13. On−Resistance vs. Gate−to−Source
Voltage
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
100°C
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
−ID, DRAIN CURRENT (AMPS)
9
1.2
1.1
1
0.9
TJ = 100°C
100
0.8
0.7
−50
−25
0
25
50
75
100
125
150
10
2
4
6
8
10
12
14
16
18
20
−TJ, JUNCTION TEMPERATURE (°C)
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 15. On−Resistance Variation with
Temperature
Figure 16. Drain−to−Source Leakage Current
vs. Voltage
http://onsemi.com
6
NTHD3100C
TYPICAL P−CHANNEL PERFORMANCE CURVES
VGS = 0 V
Ciss
1200
C, CAPACITANCE (pF)
TJ = 25°C
900
VDS = 0 V
600
Crss
300
Coss
0
5
−VGS
0
−VDS
5
10
20
15
10
5
QT
4 −V
DS
6
3
Qgs
2
4
2
0
ID = −3.2 A
TJ = 25°C
0
2
4
6
8
0
Qg, TOTAL GATE CHARGE (nC)
Figure 18. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
Figure 17. Capacitance Variation
1000
5
−IS, SOURCE CURRENT (AMPS)
VDS = −10 V
ID = −3.2 A
VGS = −4.5 V
td(off)
100
t, TIME (ns)
Qgd
1
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
tf
tr
td(on)
10
1
1
8
−VGS
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
1500
−VGS, GATE−TO−SOURCE VOLTAGE (V)
(TJ = 25°C unless otherwise noted)
10
100
VGS = 0 V
TJ = 25°C
4
3
2
1
0
0.3
0.6
0.9
RG, GATE RESISTANCE (OHMS)
−VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 19. Resistive Switching Time Variation
vs. Gate Resistance
Figure 20. Diode Forward Voltage vs. Current
1.2
DEVICE ORDERING INFORMATION
Package
Shipping†
NTHD3100CT1
ChipFET
3000 / Tape & Reel
NTHD3100CT1G
ChipFET
(Pb−Free)
3000 / Tape & Reel
NTHD3100CT3
ChipFET
10000 / Tape & Reel
NTHD3100CT3G
ChipFET
(Pb−Free)
10000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
ChipFET is a trademark of Vishay Siliconix.
http://onsemi.com
7
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ChipFETt
CASE1206A−03
ISSUE K
8
DATE 19 MAY 2009
1
SCALE 1:1
D
8
7
q
6
L
5
HE
5
6
7
8
4
3
2
1
E
1
2
3
e1
4
b
e
DIM
A
b
c
D
E
e
e1
L
HE
q
c
RESET
A
0.05 (0.002)
STYLE 1:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. GATE
5. SOURCE
6. DRAIN
7. DRAIN
8. DRAIN
STYLE 2:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
STYLE 3:
PIN 1. ANODE
2. ANODE
3. SOURCE
4. GATE
5. DRAIN
6. DRAIN
7. CATHODE
8. CATHODE
STYLE 4:
PIN 1. COLLECTOR
2. COLLECTOR
3. COLLECTOR
4. BASE
5. EMITTER
6. COLLECTOR
7. COLLECTOR
8. COLLECTOR
MILLIMETERS
NOM
MAX
1.05
1.10
0.30
0.35
0.15
0.20
3.05
3.10
1.65
1.70
0.65 BSC
0.55 BSC
0.28
0.35
0.42
1.80
1.90
2.00
5° NOM
MIN
1.00
0.25
0.10
2.95
1.55
INCHES
NOM
0.041
0.012
0.006
0.120
0.065
0.025 BSC
0.022 BSC
0.014
0.011
0.071
0.075
5° NOM
MIN
0.039
0.010
0.004
0.116
0.061
MAX
0.043
0.014
0.008
0.122
0.067
0.017
0.079
STYLE 6:
STYLE 5:
PIN 1. ANODE
PIN 1. ANODE
2. DRAIN
2. ANODE
3. DRAIN
3. DRAIN
4. DRAIN
4. GATE
5. SOURCE
5. SOURCE
6. DRAIN
6. GATE
7. CATHODE
7. DRAIN
8. CATHODE
8. CATHODE / DRAIN
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT
1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE.
4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL
AND VERTICAL SHALL NOT EXCEED 0.08 MM.
5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS.
6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD
SURFACE.
2.032
0.08
xxx MG
G
2.362
0.093
0.65
0.025
PITCH
xxx
= Specific Device Code
M
= Month Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
8X
8X
0.66
0.026
0.457
0.018
mm Ǔ
ǒinches
Basic Style
OPTIONAL SOLDERING FOOTPRINTS ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98AON03078D
ChipFET
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
ChipFETt
CASE 1206A−03
ISSUE K
DATE 19 MAY 2009
ADDITIONAL SOLDERING FOOTPRINTS*
1
2.032
0.08
2.032
0.08
1
4X
0.457
0.018
2X
1.092
0.043
1.727
0.068
2.362
0.093
2.362
0.093
0.65
0.025
PITCH
4X
2X
2X
0.457
0.018
0.66
0.026
mm Ǔ
ǒinches
Styles 1 and 4
2.032
0.08
1.118
0.044
mm Ǔ
ǒinches
Style 2
2.032
0.08
2X
0.66
0.026
1
2X
0.66
0.026
1
1.092
0.043
2X
0.66
0.026
1.092
0.043
2.362
0.093
2.362
0.093
0.65
0.025
PITCH
2X
0.65
0.025
PITCH
1.118
0.044
0.457
0.018
1.118
0.044
ǒ
mm
inches
2X
Ǔ
0.457
0.018
mm Ǔ
ǒinches
Style 5
Style 3
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
DOCUMENT NUMBER:
DESCRIPTION:
98AON03078D
ChipFET
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
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