NTHD4508NT1G

NTHD4508N MOSFET – Power, Dual, N-Channel, ChipFET 20 V, 4.1 A Features • • • • Low RDS(on) and Fast Switching Speed Leadless ChipFET Package has 40% Smaller Footprint than TSOP−6 Excellent Thermal Capabilities Where Heat Transfer is Required Pb−Free Package is Available http://onsemi.com V(BR)DSS RDS(on) TYP ID MAX 60 mW @ 4.5 V 20 V 4.1 A 80 mW @ 2.5 V Applications • DC−DC Buck/Boost Converters • Battery and Low Side Switching in Portable Equipment Such as MP3 D1, D2 Players, Cell Phones, DSCs and PDAs • Level Shifting G1, G2 MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Parameter Symbol Value Unit Drain−to−Source Voltage VDSS 20 V Gate−to−Source Voltage VGS ±12 V 3.0 A Continuous Drain Current Power Dissipation ID Steady State TJ = 25 °C tv5s TJ = 25 °C Steady State TJ = 25 °C TJ = 85 °C 0.59 tv5s TJ = 25 °C 2.1 Pulsed Drain Current TJ = 85 °C tp = 10 μs Operating Junction and Storage Temperature ChipFET CASE 1206A STYLE 2 2.2 4.1 PD W 1.13 Junction−to−Ambient – Steady State (Note 1) PIN CONNECTIONS MARKING DIAGRAM IDM 12 A TJ, TSTG −55 to 150 °C D1 8 1 S1 1 8 TL 260 °C D1 7 2 G1 2 7 D2 6 3 S2 3 D2 5 4 G2 4 THERMAL RESISTANCE RATINGS Parameter N−Channel MOSFET Symbol Max Unit RθJA 110 °C/W Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.27 in sq [1 oz] including traces). C8 M Lead Temperature for Soldering Purposes (1/8” from case for 10 s) S1, S2 6 5 C8 = Specific Device Code M = Month Code ORDERING INFORMATION Package Shipping† NTHD4508NT1 ChipFET 3000/Tape & Reel NTHD4508NT1G ChipFET (Pb−Free) 3000/Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2004 May, 2019 − Rev. 3 1 Publication Order Number: NTHD4508N/D NTHD4508N ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameter Symbol Test Conditions Min V(BR)DSS VGS = 0 V 20 Typ Max Units mA OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage Zero Gate Voltage Drain Current IDSS V VGS = 0 V, VDS = 16 V 1.0 VGS = 0 V, VDS = 16 V, TJ = 125°C 10 IGSS VDS = 0 V, VGS = "12 V "100 nA Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250 mA 1.2 V Drain−to−Source On−Resistance RDS(on) mW Gate−to−Source Leakage Current ON CHARACTERISTICS (Note 2) Forward Transconductance gFS 0.6 VGS = 4.5, ID = 3.1 A 60 75 VGS = 2.5, ID = 2.3 A 80 115 VDS = 10 V, ID = 3.1 A 6.0 S 180 pF CHARGES AND CAPACITANCES Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS VGS = 0 V, f = 1.0 MHz, VDS = 10 V 80 25 4.0 nC 5.0 10 ns 15 30 10 20 3.0 6.0 0.75 1.15 Total Gate Charge QG(TOT) 2.6 Threshold Gate Charge QG(TH) Gate−to−Source Charge QGS Gate−to−Drain Charge QGD 0.7 td(ON) VGS = 4.5 V, VDS = 10 V, ID = 3.1 A 0.5 0.6 SWITCHING CHARACTERISTICS (Note 3) Turn−On Delay Time Rise Time Turn−Off Delay Time tr td(OFF) Fall Time VGS = 4.5 V, VDS = 16 V, ID = 3.1 A, RG = 2.5 W tf DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage VSD Reverse Recovery Time tRR Charge Time ta Discharge Time tb Reverse Recovery Charge VGS = 0 V, IS = 3.1 A 12.5 VGS = 0 V, IS = 1.5 A, dIS/dt = 100 A/ms QRR http://onsemi.com 2 ns 9.0 3.5 6.0 2. Pulse Test: Pulse Width v 300 ms, Duty Cycle v 2%. 3. Switching characteristics are independent of operating junction temperatures. V nC NTHD4508N TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) VGS = 5 V to 3 V VGS = 2.4 V 2V 2.2 V 6 8 TJ = 25°C ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) 8 4 1.8 V 2 1.6 V 1.4 V 2 3 5 4 6 7 4 2 8 9 10 1 0.5 1.5 2 2.5 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics ID = 3.1 A TJ = 25°C 0.10 0.05 0 0 1 2 4 3 5 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 6 0 TJ = 25°C VGS = 2.5 V 0.07 VGS = 4.5 V 0.04 3 1 5 7 ID, DRAIN CURRENT (AMPS) Figure 4. On−Resistance vs. Drain Current and Gate Voltage 100 ID = 3.1 A VGS = 4.5 V VGS = 0 V IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 3 0.1 Figure 3. On−Resistance vs. Gate−to−Source Voltage 1.5 100°C VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 0.15 1.7 TC = −55°C 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 1 6 25°C 0 0 VDS ≥ 10 V 1.3 1.1 TJ = 100°C 10 0.9 0.7 −50 −25 0 25 50 75 100 125 150 1 2 4 6 8 10 12 14 16 18 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage http://onsemi.com 3 20 NTHD4508N C, CAPACITANCE (pF) CISS VDS = 0 V VGS = 0 V TJ = 25°C 300 CRSS 200 100 COSS 0 10 5 VGS 0 VDS 5 10 15 20 5 QG 4 7.5 3 QGS 2 5.0 QGD 2.5 1 0 ID = 3.1 A TJ = 25°C 0 0.5 GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) 1 1.5 2 2.5 QG, TOTAL GATE CHARGE (nC) 0 3 Figure 8. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge Figure 7. Capacitance Variation 7 100 10 IS, SOURCE CURRENT (AMPS) VDD = 16 V ID = 2.3 A VGS = 4.5 V t, TIME (ns) 10 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 400 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) td(off) tr td(on) tf 1 1 10 VGS = 0 V TJ = 25°C 6 5 4 3 2 1 0 0.3 100 0.45 0.6 0.75 0.9 1.05 RG, GATE RESISTANCE (OHMS) VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current http://onsemi.com 4 1.2 NTHD4508N SOLDERING FOOTPRINTS* 2.032 0.08 0.457 0.018 2.032 0.08 0.635 0.025 1.032 0.043 0.635 0.025 0.178 0.007 0.457 0.018 0.711 0.028 0.66 0.026 0.66 0.026 Figure 11. Basic 0.254 0.010 SCALE 20:1 mm Ǔ ǒinches Figure 12. Style 2 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. BASIC PAD PATTERNS footprint. The drain copper area is 0.0019 sq. in. (or 1.22 sq. mm). This will assist the power dissipation path away from the device (through the copper lead−frame) and into the board and exterior chassis (if applicable) for the single device. The addition of a further copper area and/or the addition of vias to other board layers will enhance the performance still further. The basic pad layout with dimensions is shown in Figure 11. This is sufficient for low power dissipation MOSFET applications, but power semiconductor performance requires a greater copper pad area, particularly for the drain leads. The minimum recommended pad pattern shown in Figure 12 improves the thermal area of the drain connections (pins 5, 6, 7, 8) while remaining within the confines of the basic ChipFET is a trademark of Vishay Siliconix. http://onsemi.com 5 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS ChipFETt CASE1206A−03 ISSUE K 8 DATE 19 MAY 2009 1 SCALE 1:1 D 8 7 q 6 L 5 HE 5 6 7 8 4 3 2 1 E 1 2 3 e1 4 b e DIM A b c D E e e1 L HE q c RESET A 0.05 (0.002) STYLE 1: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. GATE 5. SOURCE 6. DRAIN 7. DRAIN 8. DRAIN STYLE 2: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 3: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 4: PIN 1. COLLECTOR 2. COLLECTOR 3. COLLECTOR 4. BASE 5. EMITTER 6. COLLECTOR 7. COLLECTOR 8. COLLECTOR MILLIMETERS NOM MAX 1.05 1.10 0.30 0.35 0.15 0.20 3.05 3.10 1.65 1.70 0.65 BSC 0.55 BSC 0.28 0.35 0.42 1.80 1.90 2.00 5° NOM MIN 1.00 0.25 0.10 2.95 1.55 INCHES NOM 0.041 0.012 0.006 0.120 0.065 0.025 BSC 0.022 BSC 0.014 0.011 0.071 0.075 5° NOM MIN 0.039 0.010 0.004 0.116 0.061 MAX 0.043 0.014 0.008 0.122 0.067 0.017 0.079 STYLE 6: STYLE 5: PIN 1. ANODE PIN 1. ANODE 2. DRAIN 2. ANODE 3. DRAIN 3. DRAIN 4. DRAIN 4. GATE 5. SOURCE 5. SOURCE 6. DRAIN 6. GATE 7. CATHODE 7. DRAIN 8. CATHODE 8. CATHODE / DRAIN GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT 1 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE. 4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL AND VERTICAL SHALL NOT EXCEED 0.08 MM. 5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS. 6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD SURFACE. 2.032 0.08 xxx MG G 2.362 0.093 0.65 0.025 PITCH xxx = Specific Device Code M = Month Code G = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. 8X 8X 0.66 0.026 0.457 0.018 mm Ǔ ǒinches Basic Style OPTIONAL SOLDERING FOOTPRINTS ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98AON03078D ChipFET Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com ChipFETt CASE 1206A−03 ISSUE K DATE 19 MAY 2009 ADDITIONAL SOLDERING FOOTPRINTS* 1 2.032 0.08 2.032 0.08 1 4X 0.457 0.018 2X 1.092 0.043 1.727 0.068 2.362 0.093 2.362 0.093 0.65 0.025 PITCH 4X 2X 2X 0.457 0.018 0.66 0.026 mm Ǔ ǒinches Styles 1 and 4 2.032 0.08 1.118 0.044 mm Ǔ ǒinches Style 2 2.032 0.08 2X 0.66 0.026 1 2X 0.66 0.026 1 1.092 0.043 2X 0.66 0.026 1.092 0.043 2.362 0.093 2.362 0.093 0.65 0.025 PITCH 2X 0.65 0.025 PITCH 1.118 0.044 0.457 0.018 1.118 0.044 ǒ mm inches 2X Ǔ 0.457 0.018 mm Ǔ ǒinches Style 5 Style 3 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON03078D ChipFET Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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