NTJD4105CT2G

NTJD4105CT2G

  • 厂商:

    ONSEMI(安森美)

  • 封装:

    TSSOP6,SC88,SOT363

  • 描述:

    此互补双器件使用小封装 (2 x 2 mm) 和低 RDS(on) MOSFET,可实现最小占位,提高电路能效。 低 RDS(on) 性能特别适用于单锂离子电池或双电池锂离子电池供电设备,例如手机、媒...

  • 数据手册
  • 价格&库存
NTJD4105CT2G 数据手册
NTJD4105C MOSFET – Small Signal, Complementary, SC-88 20 V / -8.0 V, +0.63 A / -0.775 A Features • • • • • Complementary N and P Channel Device Leading −8.0 V Trench for Low RDS(on) Performance ESD Protected Gate − ESD Rating: Class 1 SC−88 Package for Small Footprint (2 x 2 mm) Pb−Free Packages are Available http://onsemi.com V(BR)DSS RDS(on) TYP 0.29 W @ 4.5 V N−Ch 20 V 0.63 A 0.36 W @ 2.5 V Applications • • • • ID Max 0.22 W @ −4.5 V DC−DC Conversion Load/Power Switching Single or Dual Cell Li−Ion Battery Supplied Devices Cell Phones, MP3s, Digital Cameras, PDAs P−Ch −8.0 V 0.51 W @ −1.8 V MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Symbol Parameter N−Ch Drain−to−Source Voltage VDSS P−Ch N−Ch Gate−to−Source Voltage Continuous Drain Current − Steady State (Based on RqJL) N−Ch P−Ch N−Ch P−Ch TA = 25°C Value Unit 20 V −8.0 VGS ±12 ID 0.63 P−Ch Continuous Drain Current − Steady State (Based on RqJA) V 0.46 TA = 25°C −0.775 TA = 85°C −0.558 TA = 25°C 0.91 TA = 85°C 0.65 TA = 25°C −1.1 TA = 85°C A IDM ±1.2 A Power Dissipation − Steady State (Based on RqJA) TA = 25°C PD 0.27 W TA = 85°C 0.14 Power Dissipation − Steady State (Based on RqJL) TA = 25°C 0.55 TA = 85°C 0.29 Junction−to−Lead (Drain) – Steady State Typ Max °C IS 0.63 A May, 2019 − Rev. 2 2 5 G2 D2 3 4 S2 MARKING DIAGRAM & PIN ASSIGNMENT TL 260 RqJA 400 CASE 419B STYLE 28 1 S1 G1 D2 °C °C/W 460 RqJL TC M G G SC−88/SOT−363 −0.775 194 TC M G = Device Code = Date Code = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION 226 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface mounted on FR4 board using 1 oz Cu area = 0.9523 in sq. © Semiconductor Components Industries, LLC, 2006 G1 1 −55 to 150 Max Typ D1 D1 G2 S2 THERMAL RESISTANCE RATINGS (Note 1) Junction−to−Ambient – Steady State 6 6 TJ, TSTG P−Ch Lead Temperature for Soldering Purposes (1/8” from case for 10 s) 1 −0.8 tp ≤ 10 ms N−Ch S1 Top View Pulsed Drain Current Source Current (Body Diode) SOT−363 SC−88 (6−LEADS) ±8.0 TA = 85°C Operating Junction and Storage Temperature −0.775 A 0.32 W @ −2.5 V 1 See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. Publication Order Number: NTJD4105C/D NTJD4105C ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Symbol N/P Drain−to−Source Breakdown Voltage V(BR)DSS Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS / TJ N P N Parameter Test Condition Min Typ 20 −8.0 27 −10.5 22 Max Units OFF CHARACTERISTICS Zero Gate Voltage Drain Current IDSS Gate−to−Source Leakage Current IGSS VGS = 0 V ID = 250 mA ID = −250 mA P N P N P V mV/ °C −6.0 VGS = 0 V, VDS = 16 V VGS = 0 V, VDS = −6.4 V TJ = 25 °C VDS = 0 V VGS = ±12 V VGS = ±8.0 VGS = VDS ID = 250 mA ID = −250 mA 1.0 1.0 10 10 mA 1.5 −1.0 V mA ON CHARACTERISTICS (Note 2) Gate Threshold Voltage VGS(TH) Gate Threshold Temperature Coefficient VGS(TH) / TJ Drain−to−Source On Resistance RDS(on) Forward Transconductance gFS N P N P N P N P P N P 0.6 −0.45 VGS = 4.5 V ID = 0.63 A VGS = −4.5 V, ID = −0.57 A VGS = 2.5 V, ID = 0.40 A VGS = −2.5 V, ID = −0.48 A VGS = −1.8 V, ID = −0.20 A VDS = 4.0 V ID = 0.63 A VDS = −4.0 V, ID = −0.57 A 0.92 −0.83 −2.1 2.2 0.29 0.22 0.36 0.32 0.51 2.0 2.0 VDS = 20 V VDS = −8.0V VDS = 20 V f = 1 MHz, VGS = 0 V VDS = −8.0 V VDS = 20 V VDS = −8.0 V VGS = 4.5 V, VDS = 10 V, ID = 0.7 A VGS = −4.5 V, VDS = −5.0 V, ID = −0.6 A VGS = 4.5 V, VDS = 10 V, ID = 0.7 A VGS = −4.5 V, VDS = −5.0 V, ID = −0.6 A VGS = 4.5 V, VDS = 10 V, ID = 0.7 A VGS = −4.5 V, VDS = −5.0 V, ID = −0.6 A VGS = 4.5 V, VDS = 10 V, ID = 0.7 A VGS = −4.5 V, VDS = −5.0 V, ID = −0.6 A 33 160 13 38 2.8 28 1.3 2.2 0.1 0.1 0.2 0.5 0.4 0.5 −mV/ °C 0.375 0.30 0.445 0.46 0.90 W S CHARGES AND CAPACITANCES Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS Total Gate Charge QG(TOT) Threshold Gate Charge QG(TH) Gate−to−Source Charge QGS Gate−to−Drain Charge QGD N P N P N P N P N P N P N P 46 225 22 55 5.0 40 3.0 4.0 pF nC SWITCHING CHARACTERISTICS (Note 3) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(ON) tr td(OFF) tf td(ON) tr td(OFF) tf N VGS = 4.5 V, VDD = 10 V, ID = 0.5 A, RG = 20 W P VGS = −4.5 V, VDD = −4.0 V, ID = −0.5 A, RG = 8.0 W ms 0.083 0.227 0.786 0.506 0.013 0.023 0.050 0.036 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time VSD tRR N P N P N P VGS = 0 V, TJ = 25°C VGS = 0 V, TJ = 125°C VGS = 0 V, dIS/dt = 90 A/ms 2. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%. 3. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 IS = 0.23 A IS = −0.23 A IS = 0.23 A IS = −0.23 A IS = 0.23 A IS = −0.23 A 0.76 0.76 0.63 0.63 0.410 0.078 1.1 1.1 V ms NTJD4105C TYPICAL N−CHANNEL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) VGS = 4.5 V to 2.2 V 1.2 VDS ≥ 10 V ID, DRAIN CURRENT (AMPS) VGS = 2 V 1.8 V 1 0.8 1.6 V 0.6 0.4 1.4 V 0.2 0.7 1 0.8 0.6 0.4 TJ = 125°C 0.2 25°C 1.2 V 0 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 1.2 TJ = 25°C 2 4 6 8 10 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 0 0.4 0.8 1.2 2 1.6 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics VGS = 4.5 V 0.6 0.5 TJ = 125°C 0.4 TJ = 25°C 0.3 TJ = −55°C 0.2 0.1 0 0 TJ = −55°C 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) ID, DRAIN CURRENT (AMPS) 1.4 0.4 1 0.6 0.8 ID, DRAIN CURRENT (AMPS) 0.2 1.4 1.2 0.7 TJ = 125°C 0.5 0.4 TJ = 25°C 0.3 TJ = −55°C 0.2 0.1 0 0 0.2 0.6 0.4 1 0.8 ID, DRAIN CURRENT (AMPS) 1.4 80 ID = 0.63 A VGS = 4.5 V and 2.5 V TJ = 25°C C, CAPACITANCE (pF) VGS = 0 V 1.6 1.4 1.2 1 60 40 Ciss 20 Coss 0.8 0.6 −50 1.2 Figure 4. On−Resistance vs. Drain Current and Temperature 2 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) VGS = 2.5 V 0.6 Figure 3. On−Resistance vs. Drain Current and Temperature 1.8 2.4 Crss −25 0 25 50 75 100 125 150 0 0 5 10 15 TJ, JUNCTION TEMPERATURE (°C) DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Capacitance Variation http://onsemi.com 3 20 NTJD4105C 5 0.7 QG(TOT) 4 IS, SOURCE CURRENT (AMPS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) TYPICAL N−CHANNEL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) VGS 3 QGS 2 QGD 1 0 ID = 0.63 A TJ = 25°C 0 0.2 0.4 0.6 0.8 1 Qg, TOTAL GATE CHARGE (nC) 1.2 VGS = 0 V 0.6 0.5 0.4 0.3 0.2 TJ = 150°C 0.1 TJ = 25°C 0 1.4 0 0.2 0.4 0.6 0.8 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 7. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge Figure 8. Diode Forward Voltage vs. Current http://onsemi.com 4 1 NTJD4105C TYPICAL P−CHANNEL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) VGS = −4.5 V to −2.6 V VGS = −2.2 V −2 V −1.8 V 1 0.8 −1.6 V 0.6 0.4 −1.4 V 0.2 −1.2 V 0 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) −ID, DRAIN CURRENT (AMPS) 1.2 1.4 TJ = 25°C 0.5 2 4 6 VDS ≥ −10 V 1.2 1 0.8 0.6 TJ = 125°C 0.4 25°C 0.2 TJ = −55°C 0 8 −VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 1.6 0.4 0.8 1.2 2 −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 9. On−Region Characteristics Figure 10. Transfer Characteristics 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) −ID, DRAIN CURRENT (AMPS) 1.4 VGS = −4.5 V 0.4 0.3 TJ = 125°C TJ = 25°C 0.2 TJ = −55°C 0.1 0 0.2 0 0.6 0.8 0.4 1 −ID, DRAIN CURRENT (AMPS) 1.2 1.4 0.5 VGS = −2.5 V TJ = 125°C 0.4 TJ = 25°C 0.3 TJ = −55°C 0.2 0.1 0 0 0.6 0.4 0.8 1 −ID, DRAIN CURRENT (AMPS) 300 ID = −0.7 A VGS = −4.5 V and −2.5 V C, CAPACITANCE (pF) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 1.6 1.2 1 0.8 0.6 −50 0.2 −25 0 25 50 75 100 125 1.2 1.4 Figure 12. On−Resistance vs. Drain Current and Temperature Figure 11. On−Resistance vs. Drain Current and Temperature 1.4 2.4 150 TJ = 25°C VGS = 0 V 240 Ciss 180 120 Coss 60 0 −8 Crss −6 −4 −2 GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) TJ, JUNCTION TEMPERATURE (°C) Figure 13. On−Resistance Variation with Temperature Figure 14. Capacitance Variation http://onsemi.com 5 0 NTJD4105C 5 0.7 QG(TOT) 4 −IS, SOURCE CURRENT (AMPS) −VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) TYPICAL P−CHANNEL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted) VGS 3 QGS 2 1 0 QGD ID = −0.6 A TJ = 25°C 0 0.4 0.8 1.2 1.6 2 Qg, TOTAL GATE CHARGE (nC) VGS = 0 V 0.6 0.5 0.4 0.3 0.2 TJ = 150°C 0.1 TJ = 25°C 0 2.4 0 0.2 0.4 0.6 0.8 −VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 15. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge Figure 16. Diode Forward Voltage vs. Current http://onsemi.com 6 1 NTJD4105C ORDERING INFORMATION Package Shipping† NTJD4105CT1 SOT−363 3000 / Tape & Reel NTJD4105CT1G SOT−363 (Pb−Free) 3000 / Tape & Reel NTJD4105CT2 SOT−363 3000 / Tape & Reel NTJD4105CT2G SOT−363 (Pb−Free) 3000 / Tape & Reel NTJD4105CT4 SOT−363 10,000 / Tape & Reel NTJD4105CT4G SOT−363 (Pb−Free) 10,000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 7 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SC−88/SC70−6/SOT−363 CASE 419B−02 ISSUE Y 1 SCALE 2:1 DATE 11 DEC 2012 2X aaa H D D H A D 6 5 GAGE PLANE 4 1 2 L L2 E1 E DETAIL A 3 aaa C 2X bbb H D 2X 3 TIPS e B 6X b ddd TOP VIEW C A-B D M A2 DETAIL A A 6X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END. 4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY AND DATUM H. 5. DATUMS A AND B ARE DETERMINED AT DATUM H. 6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP. 7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OF THE FOOT. ccc C A1 SIDE VIEW C SEATING PLANE END VIEW c RECOMMENDED SOLDERING FOOTPRINT* 6X DIM A A1 A2 b C D E E1 e L L2 aaa bbb ccc ddd MILLIMETERS MIN NOM MAX −−− −−− 1.10 0.00 −−− 0.10 0.70 0.90 1.00 0.15 0.20 0.25 0.08 0.15 0.22 1.80 2.00 2.20 2.00 2.10 2.20 1.15 1.25 1.35 0.65 BSC 0.26 0.36 0.46 0.15 BSC 0.15 0.30 0.10 0.10 GENERIC MARKING DIAGRAM* 6 XXXMG G 6X 0.30 INCHES NOM MAX −−− 0.043 −−− 0.004 0.035 0.039 0.008 0.010 0.006 0.009 0.078 0.086 0.082 0.086 0.049 0.053 0.026 BSC 0.010 0.014 0.018 0.006 BSC 0.006 0.012 0.004 0.004 MIN −−− 0.000 0.027 0.006 0.003 0.070 0.078 0.045 0.66 1 2.50 0.65 PITCH XXX = Specific Device Code M = Date Code* G = Pb−Free Package (Note: Microdot may be in either location) DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. *Date Code orientation and/or position may vary depending upon manufacturing location. *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42985B SC−88/SC70−6/SOT−363 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SC−88/SC70−6/SOT−363 CASE 419B−02 ISSUE Y DATE 11 DEC 2012 STYLE 1: PIN 1. EMITTER 2 2. BASE 2 3. COLLECTOR 1 4. EMITTER 1 5. BASE 1 6. COLLECTOR 2 STYLE 2: CANCELLED STYLE 3: CANCELLED STYLE 4: PIN 1. CATHODE 2. CATHODE 3. COLLECTOR 4. EMITTER 5. BASE 6. ANODE STYLE 5: PIN 1. ANODE 2. ANODE 3. COLLECTOR 4. EMITTER 5. BASE 6. CATHODE STYLE 6: PIN 1. ANODE 2 2. N/C 3. CATHODE 1 4. ANODE 1 5. N/C 6. CATHODE 2 STYLE 7: PIN 1. SOURCE 2 2. DRAIN 2 3. GATE 1 4. SOURCE 1 5. DRAIN 1 6. GATE 2 STYLE 8: CANCELLED STYLE 9: PIN 1. EMITTER 2 2. EMITTER 1 3. COLLECTOR 1 4. BASE 1 5. BASE 2 6. COLLECTOR 2 STYLE 10: PIN 1. SOURCE 2 2. SOURCE 1 3. GATE 1 4. DRAIN 1 5. DRAIN 2 6. GATE 2 STYLE 11: PIN 1. CATHODE 2 2. CATHODE 2 3. ANODE 1 4. CATHODE 1 5. CATHODE 1 6. ANODE 2 STYLE 12: PIN 1. ANODE 2 2. ANODE 2 3. CATHODE 1 4. ANODE 1 5. ANODE 1 6. CATHODE 2 STYLE 13: PIN 1. ANODE 2. N/C 3. COLLECTOR 4. EMITTER 5. BASE 6. CATHODE STYLE 14: PIN 1. VREF 2. GND 3. GND 4. IOUT 5. VEN 6. VCC STYLE 15: PIN 1. ANODE 1 2. ANODE 2 3. ANODE 3 4. CATHODE 3 5. CATHODE 2 6. CATHODE 1 STYLE 16: PIN 1. BASE 1 2. EMITTER 2 3. COLLECTOR 2 4. BASE 2 5. EMITTER 1 6. COLLECTOR 1 STYLE 17: PIN 1. BASE 1 2. EMITTER 1 3. COLLECTOR 2 4. BASE 2 5. EMITTER 2 6. COLLECTOR 1 STYLE 18: PIN 1. VIN1 2. VCC 3. VOUT2 4. VIN2 5. GND 6. VOUT1 STYLE 19: PIN 1. I OUT 2. GND 3. GND 4. V CC 5. V EN 6. V REF STYLE 20: PIN 1. COLLECTOR 2. COLLECTOR 3. BASE 4. EMITTER 5. COLLECTOR 6. COLLECTOR STYLE 21: PIN 1. ANODE 1 2. N/C 3. ANODE 2 4. CATHODE 2 5. N/C 6. CATHODE 1 STYLE 22: PIN 1. D1 (i) 2. GND 3. D2 (i) 4. D2 (c) 5. VBUS 6. D1 (c) STYLE 23: PIN 1. Vn 2. CH1 3. Vp 4. N/C 5. CH2 6. N/C STYLE 24: PIN 1. CATHODE 2. ANODE 3. CATHODE 4. CATHODE 5. CATHODE 6. CATHODE STYLE 25: PIN 1. BASE 1 2. CATHODE 3. COLLECTOR 2 4. BASE 2 5. EMITTER 6. COLLECTOR 1 STYLE 26: PIN 1. SOURCE 1 2. GATE 1 3. DRAIN 2 4. SOURCE 2 5. GATE 2 6. DRAIN 1 STYLE 27: PIN 1. BASE 2 2. BASE 1 3. COLLECTOR 1 4. EMITTER 1 5. EMITTER 2 6. COLLECTOR 2 STYLE 28: PIN 1. DRAIN 2. DRAIN 3. GATE 4. SOURCE 5. DRAIN 6. DRAIN STYLE 29: PIN 1. ANODE 2. ANODE 3. COLLECTOR 4. EMITTER 5. BASE/ANODE 6. CATHODE STYLE 30: PIN 1. SOURCE 1 2. DRAIN 2 3. DRAIN 2 4. SOURCE 2 5. GATE 1 6. DRAIN 1 Note: Please refer to datasheet for style callout. If style type is not called out in the datasheet refer to the device datasheet pinout or pin assignment. DOCUMENT NUMBER: DESCRIPTION: 98ASB42985B SC−88/SC70−6/SOT−363 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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