NTLTD7900ZR2

NTLTD7900ZR2 Power MOSFET 9 A, 20 V, Logic Level, N−Channel Micro8] Leadless EZFETs™ are an advanced series of Power MOSFETs which contain monolithic back−to−back Zener diodes. These Zener diodes provide protection against ESD and unexpected transients. These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. EZFET devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are DC−DC converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. Features http://onsemi.com 9 AMPERES 20 VOLTS RDS(on) = 26 mW (VGS = 4.5 V, ID = 6.5 A) RDS(on) = 31 mW (VGS = 2.5 V, ID = 5.8 A) D D • Pb−Free Package is Available Applications • Zener Protected Gates Provide Electrostatic Discharge Protection • Designed to Withstand 4000 V Human Body Model • Ultra Low RDS(on) Provides Higher Efficiency and Extends • • • Battery Life Logic Level Gate Drive − Can be Driven by Logic ICs Micro8 Leadless Surface Mount Package − Saves Board Space IDSS Specified at Elevated Temperature 2.4 kW G1 G2 2.4 kW S1 N−Channel N−Channel S2 MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Drain−to−Source Voltage Gate−to−Source Voltage Continuous Drain Current (Note 1) TA = 25°C TA = 85°C Pulsed Drain Current (tp v 10 ms) Continuous Source−Diode Conduction (Note 1) Total Power Dissipation (Note 1) TA = 25°C TA = 85°C Operating Junction and Storage Temperature Range Thermal Resistance (Note 1) Junction−to−Ambient Symbol VDSS VGS ID 9.0 6.4 30 2.9 1.4 10 Sec 20 ±12 6.0 4.3 Steady State Unit V V A 1 Micro8 LEADLESS CASE 846C A Y WW G MARKING DIAGRAM 1 7900 AYWW G IDM Is PD A A W = Assembly Location = Year = Work Week = Pb−Free Package PIN ASSIGNMENT Drain Drain 8 7 6 5 1 3.2 1.7 1.5 0.79 Source 1 Gate 1 Source 2 Gate 2 TJ, Tstg RqJA −55 to 150 38 82 °C °C/W Drain Drain Drain 2 3 4 (Bottom View) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. When surface mounted to 1″ x 1″ FR−4 board. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. © Semiconductor Components Industries, LLC, 2006 March, 2006 − Rev. 6 1 Publication Order Number: NTLTD7900ZR2/D NTLTD7900ZR2 ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage (Note 2) (VGS = 0 Vdc, ID = 250 mAdc) Zero Gate Voltage Drain Current (VDS = 16 Vdc, VGS = 0 Vdc) (VDS = 16 Vdc, VGS = 0 Vdc, TJ = 85°C) Gate−Body Leakage Current (VGS = "4.5 Vdc, VDS = 0 Vdc) (VGS = "12 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 2) Gate Threshold Voltage (Note 2) (VDS = VGS, ID = 250 mAdc) Static Drain−to−Source On−Resistance (Note 2) (VGS = 4.5 Vdc, ID = 6.5 Adc) (VGS = 2.5 Vdc, ID = 5.8 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Gate Charge (VGS = 4.5 Vdc, ID = 6.5 Adc, VDS = 10 Vdc) (Note 2) (VGS = 4.5 Vdc, VDD = 10 Vdc, ID = 1.0 Adc, RG = 9.1 W) (Note 2) td(on) tr td(off) tf QT Q1 Q2 VSD − − − − − − − 0.55 1.17 1.87 4.8 12 0.7 3.7 1.0 2.0 3.0 7.0 18 − − nC ms nC ms (VDS = 16 Vdc, VGS = 0 V, f = 1.0 MHz) Ciss Coss Crss − − − 7.4 237 4.1 15 400 10 pF pF VGS(th) RDS(on) 0.4 − − 0.67 21 27 1.0 26 31 Vdc mW V(BR)DSS IDSS 20 − − − − 24 − − − − − 1.0 20 1.0 500 Vdc mAdc Symbol Min Typ Max Unit IGSS mAdc mAdc Gate Charge SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage (IS = 1.0 Adc, VGS = 0 Vdc) IS = 1.0 Adc, VGS = 0 Vdc, TJ = 85°C) (Note 2) − − 0.69 0.62 0.8 − Vdc 2. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 3. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 NTLTD7900ZR2 TYPICAL ELECTRICAL CHARACTERISTICS 8 IGSS, GATE−CURRENT (mA) 10,000 IGSS, GATE−CURRENT (mA) 1000 100 10 1 TJ = 25°C 0.1 0.01 TJ = 150°C 6 4 2 0 0 3 6 9 12 15 VGS, GATE−TO−SOURCE VOLTAGE (V) 18 0 3 6 9 12 VGS, GATE−TO−SOURCE VOLTAGE (V) 15 Figure 1. Gate−Current versus Gate−Source Voltage 30 24 18 12 6 0 2.4 V 2.8 V 3.5 V 4.5 V 10 V 30 2.2 V ID, DRAIN CURRENT (A) 24 18 12 Figure 2. Gate−Current versus Gate−Source Voltage ID, DRAIN CURRENT (A) 2.0 V 1.8 V 1.6 V 1.4 V VGS = 1.2 V TC = 25°C 6 TC = 125°C 0 TC = −55°C 1.2 1.6 2.0 2.4 0 2 4 6 8 10 0 0.4 0.8 VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V) Figure 3. On−Region Characteristics RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) Figure 4. Transfer Characteristics 0.06 0.05 0.04 0.03 0.02 0.01 0 VGS = 2.5 V VGS = 4.5 V 0 6 12 18 24 30 ID, DRAIN CURRENT (A) Figure 5. On−Resistance versus Drain Current http://onsemi.com 3 NTLTD7900ZR2 POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Dt) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain−gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG − VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn−on and turn−off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG − VGSP)] td(off) = RG Ciss In (VGG/VGSP) 1200 1000 C, CAPACITANCE (pF) 800 Coss 600 400 200 0 Ciss and Crss are below 10 pF 0 5 10 15 20 The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off−state condition when calculating td(on) and is read at a voltage corresponding to the on−state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 8) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. TJ = 25°C VGS = 0 V GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V) Figure 6. Capacitance Variation http://onsemi.com 4 NTLTD7900ZR2 VGS, GATE−TO−SOURCE VOLTAGE (V) 5 4 3 2 1 0 100 TJ = 25°C ID = 6.5 A 10,000 tf t, TIME (ns) td(off) tr td(on) VDS = 10 V ID = 6.5 A VGS = 4.5 V 1 10 RG, GATE RESISTANCE (W) 100 1000 0 2 4 6 8 10 Qg, TOTAL GATE CHARGE (nC) 12 14 Figure 7. Gate−to−Source Figure 8. Resistive Switching Time Variation versus Gate Resistance 1.8 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 10 IS, SOURCE CURRENT (A) TJ = 25°C VGS = 0 V 1.6 1.4 1.2 1.0 ID = 9 A VGS = 4.5 V 1 TJ = 150°C TJ = 25°C 0.1 0 0.2 0.4 0.6 0.8 1 −0.8 0.6 −50 −25 0 25 50 75 100 125 150 VSD, SOURCE−TO−DRAIN VOLTAGE (V) TJ, JUNCTION TEMPERATURE (°C) Figure 9. Diode Forward Voltage versus Current Figure 10. On−Resistance Variation with Temperature VGS(th), THRESHOLD VARIANCE (V) 0.2 ID = 250 mA 0.1 0 −0.1 −0.2 −0.3 −0.4 −50 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0.040 TJ = 125°C 0.035 0.030 0.025 0.020 0.015 TJ = 25°C TJ = −55°C 0.010 0.005 0 0 5 10 15 20 25 30 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (°C) ID, DRAIN CURRENT (A) Figure 11. Threshold Voltage Figure 12. On−Resistance versus Drain Current and Temperature http://onsemi.com 5 NTLTD7900ZR2 r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) 1 D = 0.5 0.2 0.1 0.1 0.05 0.02 SINGLE PULSE 10−4 10−3 10−2 10−1 t, TIME (seconds) P(pk) t2 DUTY CYCLE, D = t1/t2 1 10 t1 RqJC(t) = r(t) RqJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TC = P(pk) RqJC(t) 100 1000 0.01 Figure 13. Thermal Response ORDERING INFORMATION Device NTLTD7900ZR2 NTLTD7900ZR2G Package Micro8 LL Micro8 LL (Pb−Free) Shipping† 3000 / Tape & Reel 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 6 NTLTD7900ZR2 PACKAGE DIMENSIONS Micro8 LEADLESS CASE 846C−01 ISSUE C A W Y T J SEATING PLANE NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETER. 3. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95−1 SPP−012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 4. DIMENSION D APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 MM AND 0.30 MM FROM TERMINAL TIP. DIMENSION L1 IS THE TERMINAL PULL BACK FROM PACKAGE EDGE, UP TO 0.1 MM IS ACCEPTABLE. L1 IS OPTIONAL. 5. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 6. OPTIONAL SIDE VIEW CAN SHOW LEADS 5 AND 8 REMOVED. DIM A B C D E F G H J K L L1 P U MILLIMETERS MIN MAX 3.30 BSC 3.30 BSC 0.85 0.95 0.25 0.35 1.30 1.50 2.55 2.75 0.65 BSC 0.95 1.15 0.25 BSC 0.00 0.05 0.35 0.45 0.00 0.10 1.28 1.38 0.17 TYP AA 8 2X 0.15 T 2X 0.15 T NOTE 4 0.10 T W Y 0.05 T W D 8X 8 1 2 3 4 G 6X DETAIL Z U 4X ÉÉÉÉ ÉÉÉÉ ÉÉÉÉ TOP VIEW E 7 6 5 INDEX AREA B 7 6 5 NOTE 6 K AA C 0.10 T 8X 0.08 T L 8X SIDE VIEW L1 F P DETAIL Z NOTE 4 H VIEW AA−AA SOLDERING FOOTPRINT* 2.75 1.23 1.50 3.60 0.40 8X 0.58 0.65 PITCH DIMENSIONS: MILLIMETERS 8X 0.33 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 NTLTD7900ZR2 EZFET is a trademark of Semiconductor Components Industries, LLC (SCILLC). Micro8 is a trademark of International Rectifier Corporation. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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