NTLUS3A39PZCTBG

NTLUS3A39PZC Power MOSFET −20 V, −5.2 A, Single P−Channel, ESD, 1.6x1.6x0.55 mm UDFN mCoolt Package Features • UDFN Package with Exposed Drain Pads for Excellent Thermal • • • Conduction Low Profile UDFN 1.6 x 1.6 x 0.55 mm for Board Space Saving Ultra Low RDS(on) These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant http://onsemi.com MOSFET RDS(on) MAX V(BR)DSS 39 mW @ −4.5 V 50 mW @ −2.5 V −20 V Applications 147 mW @ −1.5 V Products, Such as Cell Phones, PMP, Media Tablets, DSC, GPS, and Others Battery Switch High Side Load Switch S MAXIMUM RATINGS (TJ = 25°C unless otherwise stated) Parameter Drain-to-Source Voltage Gate-to-Source Voltage Symbol Value Unit VDSS −20 V VGS ±8.0 V ID −5.2 A Continuous Drain Current (Note 1) Continuous Drain Current (Note 1) Steady State TA = 25°C TA = 85°C −3.7 t≤5s TA = 25°C −6.4 Power Dissipation (Note 1) Steady State TA = 25°C t≤5s TA = 25°C Steady State TA = 25°C Continuous Drain Current (Note 2) PD G D P−Channel MOSFET MARKING DIAGRAM W 1.5 6 2.3 ID TA = 85°C A −3.4 −2.4 Power Dissipation (Note 2) TA = 25°C PD 0.6 W Pulsed Drain Current tp = 10 ms IDM −17 A TJ, TSTG -55 to 150 °C Source Current (Body Diode) (Note 2) IS −1 A Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) TL 260 °C Operating Junction and Storage Temperature −5.2 A 81 mW @ −1.8 V • Optimized for Power Management Applications for Portable • • ID MAX Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces). 2. Surface-mounted on FR4 board using the minimum recommended pad size of 30 mm2, 2 oz. Cu. 1 UDFN6 (mCOOL]) CASE 517AU 1 AF MG G AF = Specific Device Code M = Date Code G = Pb−Free Package (*Note: Microdot may be in either location) PIN CONNECTIONS (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. © Semiconductor Components Industries, LLC, 2013 May, 2013 − Rev. 0 1 Publication Order Number: NTLUS3A39PZC/D NTLUS3A39PZC THERMAL RESISTANCE RATINGS Symbol Max Junction-to-Ambient – Steady State (Note 3) RθJA 85 Junction-to-Ambient – t ≤ 5 s (Note 3) RθJA 55 Junction-to-Ambient – Steady State min Pad (Note 4) RθJA 200 Parameter Unit °C/W 3. Surface-mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces). 4. Surface-mounted on FR4 board using the minimum recommended pad size of 30 mm2, 2 oz. Cu. ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Min Drain-to-Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = −250 mA −20 Drain-to-Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ ID = −250 mA, ref to 25°C Typ Max Units OFF CHARACTERISTICS Zero Gate Voltage Drain Current IDSS VGS = 0 V, VDS = −20 V Gate-to-Source Leakage Current IGSS VDS = 0 V, VGS = ±8.0 V VGS(TH) VGS = VDS, ID = −250 mA V 13 TJ = 25°C mV/°C −1.0 mA ±10 mA −1.0 V ON CHARACTERISTICS (Note 5) Gate Threshold Voltage Negative Threshold Temp. Coefficient Drain-to-Source On Resistance Forward Transconductance VGS(TH)/TJ −0.4 3.0 RDS(on) gFS mV/°C mW VGS = −4.5 V, ID = −4.0 A 30 39 VGS = −2.5 V, ID = −2.0 A 40 50 VGS = −1.8 V, ID = −1.2 A 55 81 VGS = −1.5 V, ID = −0.5 A 75 147 VDS = −5 V, ID = −3.0 A 25 S 920 pF CHARGES, CAPACITANCES & GATE RESISTANCE Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS Total Gate Charge QG(TOT) Threshold Gate Charge QG(TH) Gate-to-Source Charge QGS Gate-to-Drain Charge QGD VGS = 0 V, f = 1 MHz, VDS = −15 V 85 80 nC 10.4 VGS = −4.5 V, VDS = −15 V; ID = −3.0 A 0.5 1.2 3.0 SWITCHING CHARACTERISTICS, VGS = 4.5 V (Note 6) Turn-On Delay Time td(ON) Rise Time Turn-Off Delay Time tr td(OFF) Fall Time ns 7.2 VGS = −4.5 V, VDD = −15 V, ID = −3.0 A, RG = 1 W tf 12.2 34.7 34.8 DRAIN-SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Charge VSD VGS = 0 V, IS = −1.0 A TJ = 25°C 0.67 TJ = 125°C 0.56 tRR ta tb 11.1 VGS = 0 V, dis/dt = 100 A/ms, IS = −1.0 A QRR http://onsemi.com 2 V ns 5.8 5.3 4 5. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%. 6. Switching characteristics are independent of operating junction temperatures. 1.0 nC NTLUS3A39PZC TYPICAL CHARACTERISTICS 20 20 −4.5 to −3.5 V 18 −ID, DRAIN CURRENT (A) −1.8 V −3.0 V 14 −ID, DRAIN CURRENT (A) −2 V 16 12 10 VGS = −2.5 V 8 −1.5 V 6 4 2 16 14 12 TJ = 25°C 10 8 6 TJ = 125°C 4 TJ = −55°C 2 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0.5 1 1.5 2 2.5 −VDS, DRAIN−TO−SOURCE VOLTAGE (V) −VGS, GATE−TO−SOURCE VOLTAGE (V) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics 0.12 TJ = 25°C 0.11 ID = −4.0 A 0.10 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 1.0 0 4.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0 0.0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) VDS ≤ −10 V 18 0.120 TJ = 25°C −1.5 V 0.100 −1.8 V 0.080 0.060 −2.5 V 0.040 0.020 VGS = −4.5 V 1 3 5 7 9 11 13 15 17 19 −VGS, GATE VOLTAGE (V) −ID, DRAIN CURRENT (A) Figure 3. On−Resistance vs. Gate−to−Source Voltage Figure 4. On−Resistance vs. Drain Current and Gate Voltage 1.6 100000 RDS(on), NORMALIZED DRAIN−TO− SOURCE RESISTANCE (W) VGS = −4.5 V ID = −4.0 A 1.5 −IDSS, LEAKAGE (nA) 1.4 1.3 1.2 1.1 1.0 0.9 10000 TJ = 125°C 1000 TJ = 85°C 0.8 0.7 100 50 25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE (°C) 125 150 2 Figure 5. On−Resistance Variation with Temperature 4 6 8 10 12 14 16 18 −VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 6. Drain−to−Source Leakage Current vs. Voltage http://onsemi.com 3 20 NTLUS3A39PZC VGS = 0 V TJ = 25°C f = 1 MHz C, CAPACITANCE (pF) 1600 1400 1200 Ciss 1000 800 600 400 Coss 200 0 Crss 0 2 4 6 8 10 12 14 16 18 20 5 18 QT 15 4 VDS QGD 1 0 6 VDS = −15 V ID = −3.0 A TJ = 25°C 0 2 4 6 8 10 3 0 12 QG, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation Figure 8. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge 10.0 −IS, SOURCE CURRENT (A) 1000.0 td(off) 100.0 t, TIME (ns) 12 9 2 QGS −VDS, DRAIN−TO−SOURCE VOLTAGE (V) tf tr td(on) 10.0 VGS = −4.5 V VDD = −15 V ID = −3.0 A 1.0 1 10 1.0 TJ = 125°C TJ = 25°C TJ = −55°C 0.1 0.2 100 0.4 0.6 0.8 1.0 RG, GATE RESISTANCE (W) −VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current 1.2 100 0.85 ID = −250 mA 0.75 10 ms 10 −ID, DRAIN CURRENT (A) 0.65 −VGS(th) (V) VGS 3 −VDS, DRAIN−TO−SOURCE VOLTAGE (V) 1800 −VGS, GATE−TO−SOURCE VOLTAGE (V) TYPICAL CHARACTERISTICS 0.55 0.45 0.35 0.25 0.15 50 25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (°C) 150 Figure 11. Threshold Voltage 100 ms 1 0.1 1 ms 0 ≤ VGS ≤ −8 V Single Pulse TC = 25°C 10 ms RDS(on) Limit Thermal Limit Package Limit 0.01 0.1 dc 1 10 −VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 12. Maximum Rated Forward Biased Safe Operating Area http://onsemi.com 4 100 NTLUS3A39PZC R(t), EFFECTIVE TRANSIENT THERMAL RESPONSE (°C/W) TYPICAL CHARACTERISTICS 90 80 RqJA = 85°C/W 70 60 50 Duty Cycle = 0.5 40 30 20 10 0.2 0.05 0.02 0.01 0.1 0 1E−06 Single Pulse 1E−05 1E−04 1E−03 1E−02 1E−01 t, TIME (s) 1E+00 1E+01 1E+02 1E+03 Figure 13. FET Thermal Response DEVICE ORDERING INFORMATION Package Shipping† NTLUS3A39PZCTAG UDFN6 (Pb−Free) 3000 / Tape & Reel NTLUS3A39PZCTBG UDFN6 (Pb−Free) 3000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 5 NTLUS3A39PZC PACKAGE DIMENSIONS UDFN6 1.6x1.6, 0.5P CASE 517AU ISSUE O A B D 2X ÉÉ ÉÉ PIN ONE REFERENCE 2X E DETAIL A OPTIONAL CONSTRUCTION 0.10 C EXPOSED Cu TOP VIEW A DETAIL B 0.05 C 0.05 C A1 SIDE VIEW C ÉÉ ÉÉ F 3 1 DIM A A1 A3 b D E e D1 D2 E2 F G L L1 MOLD CMPD A3 DETAIL B OPTIONAL CONSTRUCTION SEATING PLANE MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.13 REF 0.20 0.30 1.60 BSC 1.60 BSC 0.50 BSC 0.62 0.72 0.15 0.25 0.57 0.67 0.55 BSC 0.25 BSC 0.20 0.30 −−− 0.15 SOLDERMASK DEFINED MOUNTING FOOTPRINT* e 0.10 C A B 6X (A3) A1 NOTE 4 L1 L 0.10 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. D2 E2 G L 0.82 0.16 0.43 0.10 C A B 6 DETAIL A 4 D1 BOTTOM VIEW 0.68 2X 6X 0.35 b 0.10 C A B 0.05 C 1.90 NOTE 3 0.28 1 6X 0.32 0.50 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. mCool is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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