NTLUS3A90PZCTAG

NTLUS3A90PZC Power MOSFET −20 V, −5.0 A, mCoolt Single P−Channel, ESD, 1.6x1.6x0.55 mm UDFN Package Features • UDFN Package with Exposed Drain Pads for Excellent Thermal • • • • Conduction Low Profile UDFN 1.6x1.6x0.55 mm for Board Space Saving Lowest RDS(on) in 1.6x1.6 Package ESD Protected These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant http://onsemi.com MOSFET RDS(on) MAX V(BR)DSS ID MAX 62 mW @ −4.5 V 95 mW @ −2.5 V −20 V −5.0 A 140 mW @ −1.8 V 230 mW @ −1.5 V Applications • High Side Load Switch • PA Switch and Battery Switch • Optimized for Power Management Applications for Portable S Products, such as Cell Phones, PMP, DSC, GPS, and others G MAXIMUM RATINGS (TJ = 25°C unless otherwise stated) Parameter Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current (Note 1) Power Dissipation (Note 1) Continuous Drain Current (Note 2) Symbol Value Units VDSS −20 V VGS ±8.0 V ID −4.0 A Steady State TA = 25°C TA = 85°C −2.9 t≤5s TA = 25°C −5.0 Steady State TA = 25°C t≤5s TA = 25°C Steady State TA = 25°C PD TA = 85°C W 1.5 A −2.6 −1.9 1 UDFN6 CASE 517AU mCOOLt 1 AG MG G AG= Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) Power Dissipation (Note 2) TA = 25°C PD Pulsed Drain Current tp = 10 ms IDM −17 A TJ, TSTG -55 to 150 °C Source Current (Body Diode) (Note 2) IS −0.84 A Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) TL 260 °C Operating Junction and Storage Temperature MARKING DIAGRAM 6 2.3 ID D P−Channel MOSFET 0.6 W Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces). 2. Surface-mounted on FR4 board using the minimum recommended pad size of 30 mm2, 2 oz. Cu. (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. © Semiconductor Components Industries, LLC, 2013 May, 2013 − Rev. 0 1 Publication Order Number: NTLUS3A90PZC/D NTLUS3A90PZC THERMAL RESISTANCE RATINGS Symbol Max Units Junction-to-Ambient – Steady State (Note 3) RθJA 84 °C/W Junction-to-Ambient – t ≤ 5 s (Note 3) RθJA 55 Junction-to-Ambient – Steady State min Pad (Note 4) RθJA 200 Parameter ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Min −20 Typ Max Units OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = −250 mA Drain-to-Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ ID = −250 mA, ref to 25°C Zero Gate Voltage Drain Current Gate-to-Source Leakage Current IDSS VGS = 0 V, VDS = −20 V V −8.0 mV/°C TJ = 25°C −1.0 TJ = 85°C −10 IGSS VDS = 0 V, VGS = ±8.0 V VGS(TH) VGS = VDS, ID = −250 mA ±10 mA mA ON CHARACTERISTICS (Note 5) Gate Threshold Voltage Negative Threshold Temp. Coefficient Drain-to-Source On Resistance Forward Transconductance −0.4 VGS(TH)/TJ −1.0 3.0 RDS(on) VGS = −4.5 V, ID = −4.0 A gFS 54 V mV/°C 62 mW VGS = −2.5 V, ID = −2.0 A 74 95 VGS = −1.8 V, ID = −1.2 A 104 140 VGS = −1.5 V, ID = −0.5 A 137 230 VDS = −10 V, ID = −3.0 A 10 S 950 pF CHARGES, CAPACITANCES & GATE RESISTANCE Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS Total Gate Charge QG(TOT) Threshold Gate Charge QG(TH) Gate-to-Source Charge QGS Gate-to-Drain Charge QGD VGS = 0 V, f = 1 MHz, VDS = −10 V 90 85 nC 12.3 VGS = −4.5 V, VDS = −10 V; ID = −3.0 A 0.9 1.6 3.3 SWITCHING CHARACTERISTICS, VGS = 4.5 V (Note 6) Turn-On Delay Time td(ON) 7.9 tr 15.7 Rise Time Turn-Off Delay Time td(OFF) Fall Time VGS = −4.5 V, VDD = −10 V, ID = −3.0 A, RG = 1 W tf ns 34.8 28.5 DRAIN-SOURCE DIODE CHARACTERISTICS Forward Diode Voltage VSD Reverse Recovery Time tRR Charge Time Discharge Time Reverse Recovery Charge 3. 4. 5. 6. ta tb VGS = 0 V, IS = −1.0 A TJ = 25°C 0.74 TJ = 125°C 0.62 11.8 VGS = 0 V, dis/dt = 100 A/ms, IS = −1.0 A QRR http://onsemi.com 2 V ns 8.5 3.3 6.0 Surface-mounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [2 oz] including traces). Surface-mounted on FR4 board using the minimum recommended pad size of 30 mm2, 2 oz. Cu. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%. Switching characteristics are independent of operating junction temperatures. 1.2 nC NTLUS3A90PZC TYPICAL CHARACTERISTICS 14 −2.0 V 10 −1.8 V 8 6 4 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 6 TJ = 25°C 4 TJ = 125°C 0 0.5 TJ = −55°C 1.0 1.5 2.0 2.5 −VGS, GATE−TO−SOURCE VOLTAGE (V) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics TJ = 25°C ID = −4.0 A 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 1.5 2.0 2.5 3.0 3.5 4.0 4.5 3.0 TJ = 25°C 0.180 −1.5 V −1.8 V 0.140 −2.5 V 0.100 0.060 0.020 VGS = −4.5 V 0 2 4 6 10 8 12 14 18 16 20 −VGS, GATE VOLTAGE (V) −ID, DRAIN CURRENT (A) Figure 3. On−Resistance vs. Gate−to−Source Voltage Figure 4. On−Resistance vs. Drain Current and Gate Voltage 10,000 1.6 1.5 1.4 VGS = −4.5 V ID = −4.0 A −IDSS, LEAKAGE (nA) RDS(on), NORMALIZED DRAIN−TO− SOURCE RESISTANCE (W) 8 −VDS, DRAIN−TO−SOURCE VOLTAGE (V) 0.18 1.0 10 0 4.5 0.20 0.00 12 2 −1.5 V 0 VDS ≤ −10 V 14 −3.0 V −2.5 V 12 2 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) −3.5 V 16 16 VGS = −4.5 V −4.0 V RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) −ID, DRAIN CURRENT (A) 18 −ID, DRAIN CURRENT (A) 20 1.3 1.2 1.1 1.0 0.9 TJ = 125°C 1000 TJ = 85°C 0.8 0.7 −50 −25 0 25 50 75 100 125 150 100 2 4 6 8 10 12 14 16 18 TJ, JUNCTION TEMPERATURE (°C) −VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage http://onsemi.com 3 20 NTLUS3A90PZC C, CAPACITANCE (pF) VGS = 0 V TJ = 25°C f = 1 MHz 1600 1200 Ciss 800 400 0 Coss Crss 0 2 4 6 8 10 12 14 18 16 20 5 10 4 VDS QGS 2 6 QGD VDS = −10 V ID = −3.0 A TJ = 25°C 1 0 0 2 4 8 6 10 12 2 0 14 QG, TOTAL GATE CHARGE (nC) Figure 8. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge VGS = −4.5 V VDD = −15 V ID = −3.0 A −IS, SOURCE CURRENT (A) 100 1000 t, TIME (ns) 8 4 Figure 7. Capacitance Variation td(off) 100 tf tr 10 td(on) 1 10 TJ = 125°C 10 TJ = 25°C 1 100 TJ = −55°C 0.2 0.4 0.6 0.8 1.0 1.2 RG, GATE RESISTANCE (W) −VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current 0.85 225 ID = −250 mA 0.75 200 175 POWER (W) 0.65 −VGS(th) (V) VGS 3 −VDS, DRAIN−TO−SOURCE VOLTAGE (V) 1 12 QT −VDS, DRAIN−TO−SOURCE VOLTAGE (V) 2000 −VGS, GATE−TO−SOURCE VOLTAGE (V) TYPICAL CHARACTERISTICS 0.55 0.45 0.35 150 125 100 75 50 0.25 0.15 −50 25 −25 0 25 50 75 100 125 0 1.E−05 150 1.E−03 1.E−01 1.E+01 1.E+03 TJ, JUNCTION TEMPERATURE (°C) SINGLE PULSE TIME (s) Figure 11. Threshold Voltage Figure 12. Single Pulse Maximum Power Dissipation http://onsemi.com 4 NTLUS3A90PZC TYPICAL CHARACTERISTICS −ID, DRAIN CURRENT (A) 100 10 ms 10 100 ms 1 0.1 0.01 1 ms VGS = −8 V Single Pulse TC = 25°C 10 ms dc RDS(on) Limit Thermal Limit Package Limit 0.1 1 10 100 R(t), EFFECTIVE TRANSIENT THERMAL RESPONSE −VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 13. Maximum Rated Forward Biased Safe Operating Area 90 RqJA = 84°C/W 80 70 60 50 Duty Cycle = 0.5 40 30 20 0.2 0.05 0.02 0.01 10 0.1 0 1E−06 Single Pulse 1E−05 1E−04 1E−03 1E−02 1E−01 1E+00 1E+01 1E+02 1E+03 t, TIME (s) Figure 14. FET Thermal Response DEVICE ORDERING INFORMATION Package Shipping† NTLUS3A90PZCTAG UDFN6 (Pb−Free) 3000 / Tape & Reel NTLUS3A90PZCTBG UDFN6 (Pb−Free) 3000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 5 NTLUS3A90PZC PACKAGE DIMENSIONS UDFN6 1.6x1.6, 0.5P CASE 517AU ISSUE O A B D 2X 0.10 C ÉÉ ÉÉ PIN ONE REFERENCE 2X DETAIL A OPTIONAL CONSTRUCTION 0.10 C EXPOSED Cu TOP VIEW A DETAIL B 0.05 C 0.05 C A1 SIDE VIEW C ÉÉ ÉÉ ÉÉ F 3 1 A3 DETAIL B OPTIONAL CONSTRUCTION SEATING PLANE D2 0.82 E2 G 0.10 C A B 6 4 D1 BOTTOM VIEW MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.13 REF 0.20 0.30 1.60 BSC 1.60 BSC 0.50 BSC 0.62 0.72 0.15 0.25 0.57 0.67 0.55 BSC 0.25 BSC 0.20 0.30 −−− 0.15 SOLDERMASK DEFINED MOUNTING FOOTPRINT* L DETAIL A DIM A A1 A3 b D E e D1 D2 E2 F G L L1 MOLD CMPD e 0.10 C A B 6X (A3) A1 NOTE 4 L1 L E NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 6X 0.16 0.43 0.68 2X 0.35 b 0.10 C A B 0.05 C 1.90 NOTE 3 0.28 1 6X 0.32 0.50 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. mCool is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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