NTMD6N03R2

NTMD6N03R2, NVMD6N03R2 MOSFET – Power, Dual, N-Channel, SOIC-8 30 V, 6 A http://onsemi.com Features • Designed for use in low voltage, high speed switching applications • Ultra Low On−Resistance Provides • • • • • Higher Efficiency and Extends Battery Life − RDS(on) = 0.024 W, VGS = 10 V (Typ) − RDS(on) = 0.030 W, VGS = 4.5 V (Typ) Miniature SOIC−8 Surface Mount Package Saves Board Space Diode is Characterized for Use in Bridge Circuits Diode Exhibits High Speed, with Soft Recovery AEC Q101 Qualified − NVMD6N03R2 These Devices are Pb−Free and are RoHS Compliant VDSS RDS(ON) Typ ID Max 30 V 24 mW @ VGS = 10 V 6.0 A N−Channel D G G S Applications • • • • • D DC−DC Converters Computers Printers Cellular and Cordless Phones Disk Drives and Tape Drives MARKING DIAGRAM & PIN ASSIGNMENT 1 Symbol Value Unit VDSS 30 Volts Gate−to−Source Voltage − Continuous VGS "20 Volts Drain Current − Continuous @ TA = 25°C − Single Pulse (tp ≤ 10 ms) ID IDM 6.0 30 Adc Apk Operating and Storage Temperature Range PD Watts 2.0 1.29 −55 to +150 °C Single Pulse Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 30 Vdc, VGS = 5.0 Vdc, VDS = 20 Vdc, Peak IL = 9.0 Apk, L = 10 mH, RG = 25 W) EAS 325 mJ Thermal Resistance − Junction−to−Ambient (Note 1) − Junction−to−Ambient (Note 2) RqJA TL °C/W 62.5 97 260 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. © Semiconductor Components Industries, LLC, 2011 May, 2019 − Rev. 3 E6N03 A Y WW G E6N03 AYWW G G 1 S1 G1 S2 G2 = Specific Device Code = Assembly Location = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) TJ, Tstg Maximum Lead Temperature for Soldering Purposes for 10 seconds 8 SOIC−8 CASE 751 STYLE 11 Drain−to−Source Voltage Total Power Dissipation @ TA = 25°C (Note 1) @ TA = 25°C (Note 2) D1 D1 D2 D2 8 MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating S 1 ORDERING INFORMATION Package Shipping† NTMD6N03R2G SOIC−8 (Pb−Free) 2500 / Tape & Reel NVMD6N03R2G SOIC−8 (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Publication Order Number: NTMD6N03R2/D NTMD6N03R2, NVMD6N03R2 1. When surface mounted to an FR4 board using 1″ pad size, t ≤ 10 s 2. When surface mounted to an FR4 board using 1″ pad size, t = steady state http://onsemi.com 2 NTMD6N03R2, NVMD6N03R2 ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) Symbol Characteristic Min Typ Max 30 − − 30 − − − − − − 1.0 20 − − 100 1.0 − 1.8 4.6 2.5 − − − 0.024 0.030 0.032 0.040 − 10 − Ciss − 680 950 Coss − 210 300 Crss − 70 135 td(on) − 9 18 tr − 22 40 td(off) − 45 80 Unit OFF CHARACTERISTICS V(BR)DSS Drain−to−Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 mA) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 24 Vdc, VGS = 0 Vdc, TJ = 25°C) (VDS = 24 Vdc, VGS = 0 Vdc, TJ = 125°C) IDSS Gate−Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/°C mAdc nAdc ON CHARACTERISTICS (Note 3) Gate Threshold Voltage (VDS = VGS, ID = 250 mAdc) Temperature Coefficient (Negative) VGS(th) Static Drain−to−Source On−State Resistance (VGS = 10 Vdc, ID = 6 Adc) (VGS = 4.5 Vdc, ID = 3.9 Adc) RDS(on) Forward Transconductance (VDS = 15 Vdc, ID = 5.0 Adc) gFS Vdc mV/°C W Mhos DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 24 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Output Capacitance Reverse Transfer Capacitance pF SWITCHING CHARACTERISTICS (Notes 3 & 4) Turn−On Delay Time (VDD = 15 Vdc, ID = 1 A, VGS = 10 V, RG = 6 W) Rise Time Turn−Off Delay Time Fall Time Turn−On Delay Time (VDD = 15 Vdc, ID = 1 A, VGS = 4.5 V, RG = 6 W) Rise Time Turn−Off Delay Time Fall Time Gate Charge (VDS = 15 Vdc, VGS = 10 Vdc, ID = 5 A) ns tf − 45 80 td(on) − 13 30 tr − 27 50 td(off) − 22 40 tf − 34 70 QT − 19 30 Q1 − 2.4 − Q2 − 5.0 − Q3 − 4.3 − VSD − − 0.75 0.62 1.0 − Vdc trr − 26 − ns ta − 11 − tb − 15 − QRR − 0.015 − ns nC BODY−DRAIN DIODE RATINGS (Note 3) Diode Forward On−Voltage (IS = 1.7 Adc, VGS = 0 V) (IS = 1.7 Adc, VGS = 0 V, TJ = 150°C) Reverse Recovery Time (IS = 5 A, VGS = 0 V, dIS/dt = 100 A/ms) Reverse Recovery Stored Charge (IS = 5 A, dIS/dt = 100 A/ms, VGS = 0 V) 3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 4. Switching characteristics are independent of operating junction temperature. http://onsemi.com 3 mC NTMD6N03R2, NVMD6N03R2 TYPICAL MOSFET ELECTRICAL CHARACTERISTICS 12 TJ = 25°C 3.6 V 4V 3.8 V ID, DRAIN CURRENT (AMPS) 10 3.2 V 8 6 3V 4 2.8 V 2 VGS = 2.6 V 0 0.2 0.05 0.4 0.6 0.8 1 1.2 1.4 2 1.8 1.6 2 TJ = 125°C TJ = −55°C 0 1 2 3 4 5 Figure 2. Transfer Characteristics T = 125°C 0.03 0.025 T = 25°C 0.02 T = −55°C 0.015 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) TJ = 25°C 4 Figure 1. On−Region Characteristics 0.035 1 6 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 0.04 0.01 8 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS = 10 0.045 VDS ≥ 10 V 10 0 2 3 4 5 6 7 8 9 10 11 12 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 3.4 V 10 V 6V 0.05 TJ = 25°C 0.045 0.04 0.035 VGS = 4.5 V 0.03 0.025 0.02 VGS = 10 V 0.015 0.01 1 2 4 3 5 7 6 8 9 10 11 12 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance versus Drain Current and Temperature Figure 4. On−Resistance versus Drain Current and Gate Voltage 10,000 1.8 1.6 VGS = 0 V ID = 3 A VGS = 10 V IDSS, LEAKAGE (nA) ID, DRAIN CURRENT (AMPS) 12 1.4 1.2 1 TJ = 150°C 1000 TJ = 125°C 100 0.8 0.6 −50 −25 0 25 50 75 100 125 10 150 0 5 10 15 20 25 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current versus Voltage http://onsemi.com 4 30 NTMD6N03R2, NVMD6N03R2 POWER MOSFET SWITCHING The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off−state condition when calculating td(on) and is read at a voltage corresponding to the on−state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Dt) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain−gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG − VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn−on and turn−off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG − VGSP)] td(off) = RG Ciss In (VGG/VGSP) 1600 Ciss C, CAPACITANCE (pF) 1400 TJ = 25°C 1200 1000 Crss 800 Ciss 600 400 Coss 200 0 VDS = 0 V 10 Crss VGS = 0 V 5 0 5 10 15 20 VGS VDS GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation http://onsemi.com 5 25 30 QT 8 VGS 6 VDS Q1 4 Q2 10 ID = 6 A TJ = 25°C 2 Q3 0 20 0 2 4 6 8 10 12 14 16 18 20 0 Qg, TOTAL GATE CHARGE (nC) 1000 t, TIME (ns) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 10 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) NTMD6N03R2, NVMD6N03R2 VDD = 15 V ID = 6 A VGS = 10 V td(off) 100 tf tr 10 1 td(on) 1 10 100 RG, GATE RESISTANCE (W) Figure 8. Gate−to−Source and Drain−to−Source Voltage versus Total Charge Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN−TO−SOURCE DIODE CHARACTERISTICS high di/dts. The diode’s negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to ON Semiconductor standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 14. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short trr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by IS, SOURCE CURRENT (AMPS) 6 5 VGS = 0 V TJ = 25°C 4 3 2 1 0 0.5 0.7 0.8 0.6 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) 0.9 Figure 10. Diode Forward Voltage versus Current http://onsemi.com 6 NTMD6N03R2, NVMD6N03R2 SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain−to−source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance − General Data and Its Use.” Switching between the off−state and the on−state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 ms. In addition the 10 VGS = 12 V SINGLE PULSE TA = 25°C 1.0 ms 10 ms 1 dc 0.1 0.01 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1.0 10 100 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) ID, DRAIN CURRENT (AMPS) 100 total power averaged over a complete switching cycle must not exceed (TJ(MAX) − TC)/(RmJC). A power MOSFET designated E−FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non−linearly with an increase of peak current in avalanche and peak junction temperature. Figure 11. Maximum Rated Forward Biased Safe Operating Area 325 300 275 250 225 200 175 150 125 100 75 50 25 0 ID = 6 A 25 50 75 100 125 150 TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature http://onsemi.com 7 NTMD6N03R2, NVMD6N03R2 TYPICAL ELECTRICAL CHARACTERISTICS Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE 1.0 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.0106 W 0.0431 W 0.1643 W 0.3507 W 0.4302 W 0.01 CHIP JUNCTION 0.01 0.0253 F 0.1406 F 0.5064 F 2.9468 F 177.14 F AMBIENT SINGLE PULSE 0.001 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 t, TIME (s) 1.0E+00 Figure 13. Thermal Response di/dt IS trr ta tb TIME 0.25 IS tp IS Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 8 1.0E+01 1.0E+02 1.0E+03 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK 8 1 SCALE 1:1 −X− DATE 16 FEB 2011 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S 8 8 1 1 IC 4.0 0.155 XXXXX A L Y W G IC (Pb−Free) = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package XXXXXX AYWW 1 1 Discrete XXXXXX AYWW G Discrete (Pb−Free) XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 8 8 XXXXX ALYWX G XXXXX ALYWX 1.52 0.060 0.6 0.024 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 7.0 0.275 DIM A B C D G H J K M N S mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. BASE 7. BASE 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. BASE, #1 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. GATE, #1 8. SOURCE, #1 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. ANODE 8. COMMON CATHODE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. GATE 6. GATE 7. SOURCE 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. GATE 7. GATE 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. SECOND STAGE Vd 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR, DIE #1 2. BASE, #1 3. BASE, #2 4. COLLECTOR, #2 5. COLLECTOR, #2 6. EMITTER, #2 7. EMITTER, #1 8. COLLECTOR, #1 STYLE 9: PIN 1. EMITTER, COMMON 2. COLLECTOR, DIE #1 3. COLLECTOR, DIE #2 4. EMITTER, COMMON 5. EMITTER, COMMON 6. BASE, DIE #2 7. BASE, DIE #1 8. EMITTER, COMMON STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. INPUT 8. GROUND STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 13: PIN 1. N.C. 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 14: PIN 1. N−SOURCE 2. N−GATE 3. P−SOURCE 4. P−GATE 5. P−DRAIN 6. P−DRAIN 7. N−DRAIN 8. N−DRAIN STYLE 15: PIN 1. ANODE 1 2. ANODE 1 3. ANODE 1 4. ANODE 1 5. CATHODE, COMMON 6. CATHODE, COMMON 7. CATHODE, COMMON 8. CATHODE, COMMON STYLE 16: PIN 1. EMITTER, DIE #1 2. BASE, DIE #1 3. EMITTER, DIE #2 4. BASE, DIE #2 5. COLLECTOR, DIE #2 6. COLLECTOR, DIE #2 7. COLLECTOR, DIE #1 8. COLLECTOR, DIE #1 STYLE 17: PIN 1. VCC 2. V2OUT 3. V1OUT 4. TXE 5. RXE 6. VEE 7. GND 8. ACC STYLE 18: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 19: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. MIRROR 2 7. DRAIN 1 8. MIRROR 1 STYLE 20: PIN 1. SOURCE (N) 2. GATE (N) 3. SOURCE (P) 4. GATE (P) 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 21: PIN 1. CATHODE 1 2. CATHODE 2 3. CATHODE 3 4. CATHODE 4 5. CATHODE 5 6. COMMON ANODE 7. COMMON ANODE 8. CATHODE 6 STYLE 22: PIN 1. I/O LINE 1 2. COMMON CATHODE/VCC 3. COMMON CATHODE/VCC 4. I/O LINE 3 5. COMMON ANODE/GND 6. I/O LINE 4 7. I/O LINE 5 8. COMMON ANODE/GND STYLE 23: PIN 1. LINE 1 IN 2. COMMON ANODE/GND 3. COMMON ANODE/GND 4. LINE 2 IN 5. LINE 2 OUT 6. COMMON ANODE/GND 7. COMMON ANODE/GND 8. LINE 1 OUT STYLE 24: PIN 1. BASE 2. EMITTER 3. COLLECTOR/ANODE 4. COLLECTOR/ANODE 5. CATHODE 6. CATHODE 7. COLLECTOR/ANODE 8. COLLECTOR/ANODE STYLE 25: PIN 1. VIN 2. N/C 3. REXT 4. GND 5. IOUT 6. IOUT 7. IOUT 8. IOUT STYLE 26: PIN 1. GND 2. dv/dt 3. ENABLE 4. ILIMIT 5. SOURCE 6. SOURCE 7. SOURCE 8. VCC STYLE 29: PIN 1. BASE, DIE #1 2. EMITTER, #1 3. BASE, #2 4. EMITTER, #2 5. COLLECTOR, #2 6. COLLECTOR, #2 7. COLLECTOR, #1 8. COLLECTOR, #1 STYLE 30: PIN 1. DRAIN 1 2. DRAIN 1 3. GATE 2 4. SOURCE 2 5. SOURCE 1/DRAIN 2 6. SOURCE 1/DRAIN 2 7. SOURCE 1/DRAIN 2 8. GATE 1 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB STYLE 27: PIN 1. ILIMIT 2. OVLO 3. UVLO 4. INPUT+ 5. SOURCE 6. SOURCE 7. SOURCE 8. DRAIN STYLE 28: PIN 1. SW_TO_GND 2. DASIC_OFF 3. DASIC_SW_DET 4. GND 5. V_MON 6. VBULK 7. VBULK 8. VIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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