NTMFS4825NFET3G

NTMFS4825NFE Power MOSFET 30 V, 171 A, Single N−Channel, SO−8 FL Features • • • • • • Low RDS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Includes Schottky Diode Optimized Gate Charge to Minimize Switching Losses Dual Sided Cooling Capability These are Pb−Free Device http://onsemi.com V(BR)DSS 30 V Applications • CPU Power Delivery • DC−DC Converters • Low Side Switching RDS(ON) MAX ID MAX 2.0 mW @ 10 V 171 A 3.0 mW @ 4.5 V 140 A N−CHANNEL MOSFET D MAXIMUM RATINGS (TJ = 25°C unless otherwise stated) Parameter Symbol Value Unit Drain−to−Source Voltage VDSS 30 V Gate−to−Source Voltage VGS ±20 V ID 29 A Continuous Drain Current RqJA (Note 1) TA = 25°C Power Dissipation RqJA (Note 1) TA = 25°C PD 2.74 W Continuous Drain Current RqJA v 10 sec TA = 25°C ID 47 A Power Dissipation RqJA, t v 10 sec Continuous Drain Current RqJA (Note 2) TA = 85°C S 21 TA = 85°C Steady State G MARKING DIAGRAM 34 D TA = 25°C PD 7.3 W TA = 25°C ID 17 A TA = 85°C 12 1 SO−8 FLAT LEAD CASE 488AA STYLE 1 S S S G 825NFE AYWZZ D D D Power Dissipation RqJA (Note 2) TA = 25°C PD 0.95 W Continuous Drain Current RqJC (Note 1) TC = 25°C ID 171 A Power Dissipation RqJC (Note 1) TC = 25°C PD 96.2 W TA = 25°C IDM 288 A TA = 25°C IDmaxpkg 100 A Device Package Shipping† TJ, TSTG −40 to +150 °C NTMFS4825NFET1G SO−8FL (Pb−Free) 1500 / Tape & Reel NTMFS4825NFET3G SO−8FL (Pb−Free) 5000 / Tape & Reel Pulsed Drain Current TC = 85°C tp=10ms Current limited by package Operating Junction and Storage Temperature Source Current (Body Diode) 123 IS 120 A Drain to Source dV/dt dV/dt 6 V/ns Single Pulse Drain−to−Source Avalanche Energy (VDD = 50 V, VGS = 10 V, IL = 50 Apk, L = 0.3 mH, RG = 25 W) EAS 375 mJ Lead Temperature for Soldering Purposes (1/8” from case for 10 s) TL 260 °C A Y W ZZ = Assembly Location = Year = Work Week = Lot Traceability ORDERING INFORMATION †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. © Semiconductor Components Industries, LLC, 2012 May, 2012 − Rev. 1 1 Publication Order Number: NTMFS4825NFE/D NTMFS4825NFE THERMAL RESISTANCE MAXIMUM RATINGS Symbol Value Junction−to−Case (Drain) Parameter RqJC 1.3 Junction−to−Ambient – Steady State (Note 1) RqJA 45.7 Junction−to−Ambient – Steady State (Note 2) RqJA 132.1 Junction−to−Ambient − t v 10 sec RqJA 17.2 Junction−to−Top RqJT 7.0 Unit °C/W 1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu. 2. Surface−mounted on FR4 board using the minimum recommended pad size. ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 1.0 mA 30 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/ TJ Typ Max Unit OFF CHARACTERISTICS V 28.5 Zero Gate Voltage Drain Current IDSS VGS = 0 V, VDS = 24 V TJ = 25 °C Gate−to−Source Leakage Current IGSS VDS = 0 V, VGS = ±20 V VGS(TH) VGS = VDS, ID = 1.0 mA 60 mV/°C 500 ±100 mA nA ON CHARACTERISTICS (Note 3) Gate Threshold Voltage Negative Threshold Temperature Coefficient Drain−to−Source On Resistance VGS(TH)/TJ RDS(on) 2.0 2.5 4 VGS = 10 V VGS = 4.5 V Forward Transconductance 1.5 gFS ID = 22 A 1.3 ID = 20 A 1.3 ID = 20 A 2.0 ID = 18 A 2.0 VDS = 15 V, ID = 15 A 90 V mV/°C 2.0 3.0 mW S CHARGES AND CAPACITANCES Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS 495 Total Gate Charge QG(TOT) 40.2 Threshold Gate Charge QG(TH) Gate−to−Source Charge QGS Gate−to−Drain Charge QGD Total Gate Charge 5660 VGS = 0 V, f = 1 MHz, VDS = 15 V VGS = 4.5 V, VDS = 15 V; ID = 23 A 1150 6.4 15.3 pF nC 13.4 QG(TOT) VGS = 10 V, VDS = 15 V, ID = 23 A 83.6 nC SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(ON) 26 tr td(OFF) VGS = 4.5 V, VDS = 15 V, ID = 15 A, RG = 3.0 W tf 24 36 13 3. Pulse Test: pulse width v 300 ms, duty cycle v 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 ns NTMFS4825NFE ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Min Typ Max Unit SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(ON) 15.7 tr td(OFF) VGS = 10 V, VDS = 15 V, ID = 15 A, RG = 3.0 W tf 21.2 ns 44.6 14.5 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time VSD TJ = 25°C 0.35 TJ = 125°C 0.26 tRR Charge Time ta Discharge Time tb Reverse Recovery Charge VGS = 0 V, IS = 2.0 A 0.70 V 39.1 VGS = 0 V, dIS/dt = 100 A/ms, IS = 23 A 20.1 ns 19 QRR 34 nC Source Inductance LS 0.66 nH Drain Inductance LD Gate Inductance LG Gate Resistance RG PACKAGE PARASITIC VALUES TA = 25°C 0.20 1.5 0.7 3. Pulse Test: pulse width v 300 ms, duty cycle v 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 3 2.0 W NTMFS4825NFE TJ = 25°C ID, DRAIN CURRENT (A) VGS = 4.0 V 4.2 V thru 10 V 3.8 V 3.6 V 3.4 V 3.2 V 3.0 V 2.8 V 0 1 2 4 3 5 300 280 260 240 220 200 180 160 140 120 100 80 60 40 20 0 VDS = 10 V TJ = 25°C TJ = 125°C TJ = −55°C 1 2.5 2 1.5 3.5 3 4.5 4 VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V) Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 300 280 260 240 220 200 180 160 140 120 100 80 60 40 20 0 5 0.0035 0.010 ID = 20 A TJ = 25°C 0.008 TJ = 25°C 0.0030 0.0025 0.006 VGS = 4.5 V 0.0020 0.0015 0.004 VGS = 10 V 0.0010 0.002 0 0.0005 2 3 4 5 6 7 8 9 10 1.6 1.5 1.4 10 30 70 90 110 130 150 170 190 210 Figure 3. On−Resistance vs. Gate−to−Source Voltage Figure 4. On−Resistance vs. Drain Current and Gate Voltage 1.0E−01 ID = 20 A VGS = 10 V VGS = 0 V TJ = 150°C 1.0E−02 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 −50 50 ID, DRAIN CURRENT (A) 1.8 1.7 0 VGS, GATE−TO−SOURCE VOLTAGE (V) IDSS, LEAKAGE (A) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) ID, DRAIN CURRENT (A) TYPICAL PERFORMANCE CURVES TJ = 125°C 1.0E−03 1.0E−04 TJ = 25°C 1.0E−05 1.0E−06 −25 0 25 50 75 100 125 150 5 TJ, JUNCTION TEMPERATURE (°C) 10 15 20 25 VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage http://onsemi.com 4 30 NTMFS4825NFE 8000 VGS = 0 V C, CAPACITANCE (pF) 7000 VGS, GATE−TO−SOURCE VOLTAGE (V) TYPICAL PERFORMANCE CURVES TJ = 25°C 6000 Ciss 5000 4000 3000 2000 0 Coss Crss 1000 0 8 4 12 16 20 24 28 11 QT 10 9 8 7 6 5 Qgs 4 ID = 30 A TJ = 25°C VDD = 15 V 3 2 1 0 0 VDS, DRAIN−TO−SOURCE VOLTAGE (V) t, TIME (ns) IS, SOURCE CURRENT (A) tf 100 tr td(on) 10 1 1 10 RG, GATE RESISTANCE (W) 20 15 10 5 0 100 VGS = 0 V TJ = 25°C 25 0.1 10 ms 100 ms 10 1 ms 10 ms 1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 0.01 0.1 0.3 0.4 0.5 0.6 0.7 0.8 Figure 10. Diode Forward Voltage vs. Current dc 10 1 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 100 EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) I D, DRAIN CURRENT (A) 100 VGS = 20 V Single Pulse TC = 25°C 0.2 VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation vs. Gate Resistance 1000 80 30 td(off) VDD = 15 V ID = 15 A VGS = 10 V 40 50 20 30 60 70 QG, TOTAL GATE CHARGE (nC) 10 Figure 8. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge Figure 7. Capacitance Variation 1000 Qgd 400 ID = 50 A 350 300 250 200 150 100 50 0 25 Figure 11. Maximum Rated Forward Biased Safe Operating Area 50 75 150 100 125 TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 5 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DFN5 5x6, 1.27P (SO−8FL) CASE 488AA ISSUE N 1 DATE 25 JUN 2018 SCALE 2:1 2X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH PROTRUSIONS OR GATE BURRS. 0.20 C D A 2 B D1 2X 0.20 C 4X E1 2 q E c 1 2 3 A1 4 TOP VIEW C DETAIL A 0.10 C SEATING PLANE A 0.10 C SIDE VIEW MILLIMETERS MIN NOM MAX 0.90 1.00 1.10 0.00 −−− 0.05 0.33 0.41 0.51 0.23 0.28 0.33 5.00 5.15 5.30 4.70 4.90 5.10 3.80 4.00 4.20 6.00 6.30 6.15 5.70 5.90 6.10 3.45 3.65 3.85 1.27 BSC 0.51 0.575 0.71 1.20 1.35 1.50 0.51 0.575 0.71 0.125 REF 3.00 3.40 3.80 0_ −−− 12 _ DIM A A1 b c D D1 D2 E E1 E2 e G K L L1 M q GENERIC MARKING DIAGRAM* DETAIL A 1 0.10 b C A B 0.05 c 8X XXXXXX AYWZZ e/2 e L 1 4 K RECOMMENDED SOLDERING FOOTPRINT* E2 PIN 5 (EXPOSED PAD) L1 M 2X 0.495 4.560 2X 1.530 G D2 2X BOTTOM VIEW XXXXXX = Specific Device Code A = Assembly Location Y = Year W = Work Week ZZ = Lot Traceability *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Some products may not follow the Generic Marking. 0.475 3.200 4.530 STYLE 1: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 1.330 STYLE 2: 2X PIN 1. ANODE 0.905 2. ANODE 3. ANODE 4. NO CONNECT 0.965 5. CATHODE 1 4X 1.000 4X 0.750 1.270 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: DESCRIPTION: 98AON14036D DFN5 5x6, 1.27P (SO−8FL) Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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