NTMKE4892N
Power MOSFET
30 V, 126 A, Single N−Channel, ICEPAK
Features
•
•
•
•
•
•
•
Low Package Inductance
Low RDS(on) to Minimize Conduction Losses
Low Capacitance to Minimize Driver Losses
Optimized Gate Charge to Minimize Switching Losses
Dual Sided Cooling Capability
Compatible with MX Footprint and Outline
This is a Pb−Free Device
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V(BR)DSS
Parameter
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
30
V
Gate−to−Source Voltage
VGS
±20
V
ID
26
A
Continuous Drain
Current RqJA (Note 1)
TA = 25°C
Power Dissipation RqJA
(Note 1)
TA = 25°C
PD
2.8
W
Continuous Drain
Current RqJ−PCB
(Note 2)
TA = 25°C
ID
126
A
TA = 70°C
PD
65
W
Continuous Drain
Current RqJC (Note 1)
TC = 25°C
ID
148
A
Power Dissipation
RqJC (Note 1)
TC = 25°C
TC = 70°C
TA = 25°C, tp = 10 ms
Current Limited by Package
TA = 25°C
Operating Junction and Storage Temperature
Source Current (Body Diode) (Note 1)
89
W
IDM
210
A
IDmax
50
A
TJ,
Tstg
−55 to
150
°C
IS
89
A
dV/dt
6.0
V/ns
Single Pulse Drain−to−Source Avalanche Energy
(TJ = 25°C, VDD = 50 V, VGS = 10 V,
IL = 44 Apk, L = 0.3 mH, RG = 25 W)
EAS
290
mJ
TL
270
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surfacemounted on FR4 board using 1 sq−in pad, 1 oz Cu.
2. Measured with a TJ of approximately 90°C using 1 oz Cu board.
3. Surfacemounted on FR4 board using 1 sq−in pad, 2 oz Cu.
© Semiconductor Components Industries, LLC, 2011
January, 2011 − Rev. 1
D
118
PD
Drain to Source DV/DT
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
E4892
AYWWG
G
70
TA = 25°C
Pulsed Drain Current
126 A
E4892= Specific Device Code
A
= Assembly Location
Y
= Year
WW = Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
21
TA = 70°C
ID MAX
MARKING
DIAGRAM
ICEPAK
E1 PAD
CASE 145AE
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Power Dissipation
RqJ−PCB (Note 2)
3.8 mW @ 4.5 V
ÍÍ
ÍÍ
• CPU Power Delivery
• DC−DC Converters
• Optimized for Synch FET
Steady
State
2.6 mW @ 10 V
30 V
Applications
RDS(ON) MAX
1
G
S
N−CHANNEL MOSFET
ORDERING INFORMATION
Device
Package
Shipping†
NTMKE4892NT1G
ICEPAK 1500/Tape & Reel
(Pb−Free)
NTMKE4892NT3G
ICEPAK 5000/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Publication Order Number:
NTMKE4892N/D
NTMKE4892N
THERMAL RESISTANCE MAXIMUM RATINGS
Symbol
Value
Unit
Junction−to−Case (Drain) (Note 1)
Parameter
RqJC
1.4
°C/W
Junction−to−Ambient – Steady State (Note 1)
RqJA
45
Junction−to−Ambient – Steady State (Notes 2 and 3)
RqJA
20
RqJ−PCB
1.0
Junction−to−PCB (Note 2)
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = 250 mA
30
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJ
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
IDSS
Gate−to−Source Leakage Current
V
22
VGS = 0 V, VDS = 24 V
mV/°C
TJ = 25°C
1.0
TJ = 125°C
10
IGSS
VDS = 0 V, VGS = ±20 V
VGS(TH)
VGS = VDS, ID = 250 mA
mA
±100
nA
2.4
V
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage
Negative Threshold Temperature
Coefficient
VGS(TH)/TJ
Drain−to−Source On Resistance
RDS(on)
Forward Transconductance
1.4
6.0
gFS
mV/°C
mW
VGS = 10 V, ID = 24 A
2.1
2.6
VGS = 4.5 V, ID = 19 A
3.1
3.8
VDS = 15 V, ID = 19 A
30
S
4270
pF
CHARGES, CAPACITANCES AND GATE RESISTANCE
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
VGS = 0 V, f = 1.0 MHz, VDS = 15 V
820
Crss
430
Total Gate Charge
QG(TOT)
31.9
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
Total Gate Charge
QG(TOT)
VGS = 4.5 V, VDS = 15 V, ID = 19 A
nC
3.2
11.5
11.5
VGS = 10 V, VDS = 15 V, ID = 23 A
61
nC
17.3
ns
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(on)
tr
td(off)
VGS = 4.5 V, VDS = 15 V,
ID = 19 A, RG = 2.0 W
tf
16.8
28.6
7.1
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
VSD
Reverse Recovery Time
tRR
Charge Time
Discharge Time
Reverse Recovery Charge
ta
tb
VGS = 0 V, IS = 19 A
TJ = 25°C
0.8
TJ = 125°C
0.65
1.1
ns
32.2
VGS = 0 V, dIS/dt = 200 A/ms,
IS = 23 A
QRR
V
16.1
16.1
22
nC
PACKAGE PARASITIC VALUES
Gate Resistance
RG
TA = 25°C
4. Pulse Test: pulse width = 300 ms, duty cycle v 2%.
5. Switching characteristics are independent of operating junction temperatures.
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2
0.5
1.5
W
NTMKE4892N
TYPICAL CHARACTERISTICS
10 V − 6.5 V
4.5 V − 4.2 V
160
TJ = 25°C
120
ID, DRAIN CURRENT (A)
3.6 V
3.8 V
100
80
3.4 V
60
3.2 V
40
20
0.5
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
0
1.5
1
2
2.5
3.5
3
4
120
100
80
60
TJ = 125°C
40
3.0 V
20
2.8 V
4.5
5
0
TJ = 25°C
TJ = −55°C
3.5
3
4.5
4
Figure 2. Transfer Characteristics
5
0.0050
ID = 24 A
TJ = 25°C
TJ = 25°C
0.0040
0.0070
0.0060
VGS = 4.5 V
0.0030
0.0050
0.0040
0.0020
0.0030
0.0020
3
2
4
5
6
7
8
9
VGS, GATE−TO−SOURCE VOLTAGE (V)
10
VGS = 10 V
0.0010
0
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
20
40
1.0E−5
ID = 24 A
VGS = 10 V
100
120
140
160
TJ = 150°C
IDSS, LEAKAGE (A)
TJ = 125°C
1.0E−7
1.2
1.1
1.0
1.0E−8
0.9
0.8
1.0E−9
TJ = 25°C
0.7
0.6
−50
80
VGS = 0 V
1.0E−6
1.3
60
ID, DRAIN CURRENT (A)
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
1.6
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
2.5
Figure 1. On−Region Characteristics
0.0080
1.4
2
VGS, GATE−TO−SOURCE VOLTAGE (V)
0.0090
1.5
1.5
1
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
0.0100
0.0010
VDS ≥ 10 V
140
RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW)
ID, DRAIN CURRENT (A)
140
−25
0
25
50
75
100
125
1.0E−10
150
5
TJ, JUNCTION TEMPERATURE (°C)
10
15
20
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
25
NTMKE4892N
TYPICAL CHARACTERISTICS
4500
C, CAPACITANCE (pF)
TJ = 25°C
VGS = 0 V
Ciss
4000
VGS, GATE−TO−SOURCE VOLTAGE (V)
5000
3500
3000
2500
2000
1500
Coss
1000
500
0
0
Crss
5
10
15
20
25
30
QT
10
8
6
4
Qgs
Qgd
TJ = 25°C
VDD = 15 V
VGS = 10 V
ID = 19 A
2
0
0
10
20
40
30
50
60
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V)
Qg, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
70
20
1000
VDD = 15 V
ID = 19 A
VGS = 4.5 V
IS, SOURCE CURRENT (A)
td(on)
td(off)
tr
10
VGS = 0 V
TJ = 25°C
18
100
t, TIME (ns)
12
tf
16
14
12
10
8
6
4
2
1
1
10
0
0.1
100
EAS, SINGLE PULSE DRAIN−TO−
SOURCE AVALANCHE ENERGY (mJ)
ID, DRAIN CURRENT (A)
0.5
0.6
0.7
0.8
0.9
Figure 10. Diode Forward Voltage vs. Current
10 ms
100 ms
10
0.01
0.1
0.4
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
100
0.1
0.3
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
1000
1
0.2
RG, GATE RESISTANCE (W)
1 ms
10 ms
0 ≤ VGS ≤ 20 V
Single Pulse
TC = 25°C
RDS(on) Limit
Thermal Limit
Package Limit
1
dc
10
100
300
280
260
240
220
200
180
160
140
120
100
80
60
40
20
0
25
ID = 44 A
50
75
100
125
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
TJ, STARTING JUNCTION TEMPERATURE(°C)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
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4
150
NTMKE4892N
PACKAGE DIMENSIONS
ICEPAK 6.3x4.9 − E1 PAD
CASE 145AE−01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO THE FLANGES
OF LEADFRAME ONLY.
D
GATE PAD
REFERENCE
ÍÍ
ÍÍ
E
DIM
A
A1
A2
D
D2
D3
D4
E
E2
E3
E4
F
G
H
TOP VIEW
A1
A
0.08 C
0.08 C
NOTE 3
A2
SIDE VIEW
C
SEATING
PLANE
MILLIMETERS
MIN
MAX
0.61
0.68
0.02
0.08
0.08
0.17
6.25
6.35
0.35
0.45
1.34
1.38
0.64
0.68
4.80
5.05
3.85
3.95
0.76
0.80
0.64
0.68
0.98 BSC
2.38 BSC
0.38
0.42
2X
D3
SOLDERING FOOTPRINT*
D4
2X
D2
1.75
2X
E3
0.75
4X
2X
0.90
0.87
E2
1.22
H
E4
2.35
0.12 C A F
A
4X
1.85
G
0.12 C A
0.75
BOTTOM VIEW
2X
1.75
1.45
2.90
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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NTMKE4892N/D
