NTMS4917NR2G

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Other names and brands may be claimed as the property of others. NTMS4917N Power MOSFET 30 V, 10.5 A, N−Channel, SO−8 Features • • • • • Low RDS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses Optimized for 5 V, 12 V Gate Drives These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant Applications http://onsemi.com V(BR)DSS RDS(ON) MAX 11 mW @ 10 V 30 V • DC−DC Converters • Printers Drain−to−Source Voltage Gate−to−Source Voltage N−Channel Symbol Value Unit VDSS 30 V VGS ±20 V ID 8.5 A Continuous Drain Current RqJA (Note 1) Steady State TA = 25°C Power Dissipation RqJA (Note 1) Steady State TA = 25°C PD 1.28 W Continuous Drain Current RqJA (Note 2) Steady State TA = 25°C ID 7.1 A TA = 70°C TA = 25°C Power Dissipation RqJA (Note 2) G S PD W TA = 25°C Power Dissipation RqJA, t v 10 s(Note 1) Steady State TA = 25°C PD 1.95 W Pulsed Drain Current TA = 25°C, tp = 10 ms IDM 127 A TJ, Tstg −55 to 150 °C TA = 70°C 10.5 A 8.4 Source Current (Body Diode) IS 2.4 A EAS 32 mJ TL 260 °C SO−8 CASE 751 STYLE 12 Source Source Source Gate 1 8 Drain Drain Drain Drain Top View 4917N = Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. THERMAL RESISTANCE MAXIMUM RATINGS Parameter 1 4917N AYWWG G ID 0.88 Steady State Single Pulse Drain−to−Source Avalanche Energy (TJ = 25°C, VDD = 30 V, VGS = 10 V, IL = 8 Apk, L = 1.0 mH, RG = 25 W) MARKING DIAGRAM/ PIN ASSIGNMENT 5.7 Continuous Drain Current RqJA, t v 10 s (Note 1) Operating Junction and Storage Temperature D 6.8 TA = 70°C 10.5 A 15 mW @ 4.5 V MAXIMUM RATINGS (TJ = 25°C unless otherwise stated) Parameter ID MAX Symbol Value Unit Junction−to−Ambient – Steady State (Note 1) RqJA 97.4 °C/W Junction−to−Ambient – t v 10 s (Note 1) RqJA 64 Junction−to−Foot (Drain) RqJF 25.9 Junction−to−Ambient – Steady State (Note 2) RqJA 142.4 Device NTMS4917NR2G Package Shipping† SO−8 (Pb−Free) 2500/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. 1. Surfacemounted on FR4 board using 1 in sq pad size, 1 oz Cu. 2. Surfacemounted on FR4 board using the minimum recommended pad size. © Semiconductor Components Industries, LLC, 2011 April, 2011 − Rev. 0 1 Publication Order Number: NTMS4917N/D NTMS4917N ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter Symbol Test Condition Min Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 30 Drain−to−Source Breakdown Voltage Temperature Coefficient V(BR)DSS/TJ Typ Max Unit OFF CHARACTERISTICS Zero Gate Voltage Drain Current IDSS Gate−to−Source Leakage Current V 16 VGS = 0 V, VDS = 30 V mV/°C TJ = 25°C 1.0 TJ = 125°C 10 IGSS VDS = 0 V, VGS = ±20 V VGS(TH) VGS = VDS, ID = 250 mA ±100 mA nA ON CHARACTERISTICS (Note 3) Gate Threshold Voltage 1.0 1.7 2.5 VGS(TH)/TJ Drain−to−Source On Resistance RDS(on) VGS = 10 V, ID = 11 A 8.25 11 VGS = 4.5 V, ID = 9 A 11.25 15 gFS VDS = 1.5 V, ID = 7.5 A 19 S 1054 pF Forward Transconductance 5 V Negative Threshold Temperature Coefficient mV/°C mW CHARGES, CAPACITANCES AND GATE RESISTANCE Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss 165 Total Gate Charge QG(TOT) 15.6 Threshold Gate Charge QG(TH) 2.6 Gate−to−Source Charge QGS Gate−to−Drain Charge QGD Total Gate Charge QG(TOT) VGS = 0 V, f = 1.0 MHz, VDS = 25 V VGS = 4.5 V, VDS = 15 V, ID = 7.5 A 325 nC 4.2 7 VGS = 10 V, VDS = 15 V, ID = 7.5 A 29 nC td(on) 8.5 ns tr 6.3 SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time td(off) VGS = 10 V, VDS = 15 V, ID = 1.0 A, RG = 6.0 W tf 27 12 DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time VSD VGS = 0 V, IS = 2.0 A TJ = 25°C 0.75 TJ = 125°C 0.58 tRR 28 Charge Time ta 12.2 Discharge Time tb Reverse Recovery Charge VGS = 0 V, dIS/dt = 100 A/ms, IS = 2.0 A 1.0 V ns 15.7 QRR 20 nC LS 0.66 nH PACKAGE PARASITIC VALUES Source Inductance Drain Inductance LD Gate Inductance LG Gate Resistance RG TA = 25°C 0.2 1.5 0.70 3. Pulse Test: pulse width = 300 ms, duty cycle v 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 W NTMS4917N TYPICAL CHARACTERISTICS VGS = 10 V 7V 5V 4V −ID, DRAIN CURRENT (A) 20 40 3V TJ = 25°C VDS ≥ 10 V ID, DRAIN CURRENT (A) 25 2.8 V 15 2.6 V 10 2.2 V 2.3 V 2.5 V 2.4 V 5 30 20 TJ = −55°C TJ = 125°C 10 TJ = 25°C 0 0.5 1.0 1.5 2.5 2.0 3.0 3.5 4.0 4.5 2.0 2.5 3.0 3.5 4.0 Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics 0.015 0.010 4 5 6 7 8 9 10 4.5 0.012 TJ = 25°C 0.011 VGS = 4.5 V 0.01 0.009 VGS = 10 V 0.008 0.007 2 4 6 8 10 12 14 16 18 20 VGS, GATE−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A) Figure 3. On−Resistance vs. Gate−to−Source Voltage Figure 4. On−Resistance vs. Drain Current and Gate Voltage 10,000 1.7 1.6 1.5 ID = 11 A VGS = 10 V VGS = 0 V IDSS, LEAKAGE (nA) RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 1.5 VGS, GATE−TO−SOURCE VOLTAGE (V) ID = 11 A TJ = 25°C 3 1.0 VDS, DRAIN−TO−SOURCE VOLTAGE (V) 0.020 0.005 0 5.0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0 1.4 TJ = 125°C 1000 1.3 1.2 1.1 1.0 0.9 TJ = 100°C 100 0.8 0.7 0.6 −50 −25 0 25 50 75 100 125 150 10 5 10 15 20 25 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (V) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage http://onsemi.com 3 30 NTMS4917N 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 VGS, GATE−TO−SOURCE VOLTAGE (V) C, CAPACITANCE (pF) TYPICAL CHARACTERISTICS VGS = 0 V TJ = 25°C Ciss Coss Crss 0 5 10 15 20 25 30 td(off) IS, SOURCE CURRENT (A) t, TIME (ns) Qgs Qgd Q1 Q2 VGS = 10 V ID = 7.5 A TJ = 25°C 2 0 0 5 10 15 20 25 30 2.0 tf td(on) 10 1 10 VGS = 0 V TJ = 25°C 1.5 1.0 0.5 0 100 0.50 0.55 0.60 0.65 0.70 0.75 0.80 RG, GATE RESISTANCE (W) VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current Single Pulse TC = 25°C 10 ms 100 ms 10 1 ms 10 ms 1 RDS(on) Limit Thermal Limit Package Limit 0.1 0.01 0.1 1 DC 10 EAS, SINGLE PULSE DRAIN−TO− SOURCE AVALANCHE ENERGY (mJ) ID, DRAIN CURRENT (A) 4 Figure 8. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge tr 0.01 VDS 6 Figure 7. Capacitance Variation 100 100 8 Qg, TOTAL GATE CHARGE (nC) VGS = 10 V ID = 1 A VDD = 15 V 1000 QT VDS, DRAIN−TO−SOURCE VOLTAGE (V) 1000 1 10 100 35 ID = 8 A 30 25 20 15 10 5 0 25 50 75 100 125 VDS, DRAIN−TO−SOURCE VOLTAGE (V) TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 4 150 NTMS4917N PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X S M J SOLDERING FOOTPRINT* INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN 1.52 0.060 7.0 0.275 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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