NTMS4937N

NTMS4937N Power MOSFET Features 30 V, 13.6 A, N−Channel, SO−8 • • • • • • • • Low RDS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant V(BR)DSS 30 V http://onsemi.com RDS(ON) MAX 6.5 mW @ 10 V 8.7 mW @ 4.5 V N−Channel ID MAX 13.6 A Applications DC−DC Converters Points of Loads Power Load Switch Motor Controls Parameter Symbol VDSS VGS Steady State Steady State Steady State TA = 25°C TA = 70°C TA = 25°C TA = 25°C TA = 70°C TA = 25°C Steady State Steady State TA = 25°C TA = 70°C TA = 25°C PD IDM TJ, Tstg IS EAS PD ID PD ID ID Value 30 ±20 11.2 9.0 1.36 8.6 6.9 0.81 13.6 11 2.0 112 −55 to 150 2.1 84.5 W A °C A mJ W A W A Unit V V A MAXIMUM RATINGS (TJ = 25°C unless otherwise stated) Drain−to−Source Voltage Gate−to−Source Voltage Continuous Drain Current RqJA (Note 1) Power Dissipation RqJA (Note 1) Continuous Drain Current RqJA (Note 2) Power Dissipation RqJA (Note 2) Continuous Drain Current RqJA, t v 10 s (Note 1) Power Dissipation RqJA, t v 10 s(Note 1) Pulsed Drain Current D G S MARKING DIAGRAM/ PIN ASSIGNMENT 1 SO−8 CASE 751 STYLE 12 Source Source Source Gate 1 4937N AYWWG G Top View 8 Drain Drain Drain Drain TA = 25°C, tp = 10 ms Operating Junction and Storage Temperature Source Current (Body Diode) Single Pulse Drain−to−Source Avalanche Energy (TJ = 25°C, VDD = 30 V, VGS = 10 V, IL = 13 Apk, L = 1.0 mH, RG = 25 W) Lead Temperature for Soldering Purposes (1/8″ from case for 10 s) 4937N = Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION 260 °C Device NTMS4937NR2G Package SO−8 (Pb−Free) Shipping† 2500/Tape & Reel TL THERMAL RESISTANCE MAXIMUM RATINGS Parameter Junction−to−Ambient – Steady State (Note 1) Junction−to−Ambient – t v 10 s (Note 1) Junction−to−Foot (Drain) Junction−to−Ambient – Steady State (Note 2) Symbol RqJA RqJA RqJF RqJA Value 91.9 61.1 22.6 154.7 Unit °C/W †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surfacemounted on FR4 board using 1 in sq pad size (Cu area = 1.127 in sq [1 oz] including traces). 2. Surfacemounted on FR4 board using the minimum recommended pad size. © Semiconductor Components Industries, LLC, 2009 September, 2009 − Rev. 0 1 Publication Order Number: NTMS4937N/D NTMS4937N ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified) Parameter OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage Drain−to−Source Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current V(BR)DSS V(BR)DSS/TJ IDSS IGSS VGS(TH) VGS(TH)/TJ RDS(on) gFS Ciss Coss Crss QG(TOT) QG(TH) QGS QGD QG(TOT) td(on) tr td(off) tf VSD tRR ta tb QRR LS LD LG RG TA = 25°C VGS = 0 V, dIS/dt = 100 A/ms, IS = 2.0 A TJ = 25°C TJ = 125°C VGS = 10 V, VDS = 15 V, ID = 1.0 A, RG = 6.0 W VGS = 10 V, VDS = 15 V, ID = 7.5 A VGS = 4.5 V, VDS = 15 V, ID = 7.5 A VGS = 0 V, f = 1.0 MHz, VDS = 25 V VGS = 10 V, ID = 7.5 A VGS = 4.5 V, ID = 6.5 A Forward Transconductance VDS = 1.5 V, ID = 7.5 A CHARGES, CAPACITANCES AND GATE RESISTANCE Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Threshold Gate Charge Gate−to−Source Charge Gate−to−Drain Charge Total Gate Charge 2563 715 25 17.4 4.1 6.6 3.3 38.5 nC nC pF TJ = 25°C TJ = 125°C VGS = 0 V, ID = 250 mA 30 13.1 1.0 10 ±100 nA V mV/°C mA Symbol Test Condition Min Typ Max Unit VGS = 0 V, VDS = 24 V Gate−to−Source Leakage Current ON CHARACTERISTICS (Note 3) Gate Threshold Voltage Negative Threshold Temperature Coefficient Drain−to−Source On Resistance VDS = 0 V, VGS = ±20 V VGS = VDS, ID = 250 mA 1.0 5.1 5.4 7.1 27.3 2.5 V mV/°C 6.5 8.7 mW S SWITCHING CHARACTERISTICS (Note 4) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time 12.3 3.6 33.8 38.9 ns DRAIN−SOURCE DIODE CHARACTERISTICS Forward Diode Voltage VGS = 0 V, IS = 2.0 A 0.72 0.56 40 18.8 21.2 38 nC ns 1.0 V Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Charge PACKAGE PARASITIC VALUES Source Inductance Drain Inductance Gate Inductance Gate Resistance 0.66 0.2 1.5 0.4 1.0 nH W 3. Pulse Test: pulse width = 300 ms, duty cycle v 2%. 4. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 NTMS4937N TYPICAL PERFORMANCE CURVES 27 ID, DRAIN CURRENT (AMPS) 24 21 18 15 12 9 6 3 0 0 1.0 2.0 3.0 4.0 2.6 V 2.4 V 2.2 V 5.0 10V 4.5 V 4V 3.6 V 3.2 V 3V TJ = 25°C 2.8 V ID, DRAIN CURRENT (AMPS) 52 48 VDS ≥ 10 V 44 40 36 32 28 24 20 16 TJ = 125°C 12 8 TJ = 25°C 4 0 2 1.5 2.5 TJ = −55°C 3 3.5 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0.050 0.040 0.030 0.020 0.010 TJ = 25°C ID = 7.5 A RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0.008 Figure 2. Transfer Characteristics TJ = 25°C 0.007 VGS = 4.5 V 0.006 0.005 VGS = 10 V 0.000 2 3 4 5 6 7 8 9 10 0.004 4 9 14 19 24 29 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance vs. Gate−to−Source Voltage 1.8 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 1.6 1.4 1.2 1.0 0.8 0.6 −50 100 ID = 7.5 A VGS = 10 V IDSS, LEAKAGE (nA) 10000 100000 Figure 4. On−Resistance vs. Drain Current and Gate Voltage VGS = 0 V TJ = 150°C 1000 TJ = 125°C −25 0 25 50 75 100 125 150 5 10 15 20 25 30 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage http://onsemi.com 3 NTMS4937N TYPICAL PERFORMANCE CURVES TJ = 25°C Ciss VGS = 0 V VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 3500 3000 C, CAPACITANCE (pF) 2500 2000 1500 1000 500 0 Crss 0 5 10 15 25 20 DRAIN−TO−SOURCE VOLTAGE (VOLTS) 30 Coss 10 9 8 7 6 5 4 3 2 1 0 0 5 QGS QGD VGS = 10 V ID = 7.5 A TJ = 25°C 10 30 15 25 20 QG, TOTAL GATE CHARGE (nC) 35 40 VGS QT Figure 7. Capacitance Variation Figure 8. Gate−To−Source and Drain−To−Source Voltage vs. Total Charge 1000 td(off) tf td(on) 10 tr IS, SOURCE CURRENT (AMPS) VDD = 15 V ID = 1 A VGS = 10 V 100 t, TIME (ns) 2 VGS = 0 V TJ = 25°C 1.5 1 0.5 1 1 10 RG, GATE RESISTANCE (OHMS) 100 0 0.5 0.55 0.6 0.65 0.7 0.75 0.8 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 9. Resistive Switching Time Variation vs. Gate Resistance 1000 ID, DRAIN CURRENT (AMPS) 100 10 ms 10 1 0.1 VGS = 20 V SINGLE PULSE TC = 25°C RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10 100 ms 1 ms 10 ms dc 100 EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) 90 80 70 60 50 40 30 20 10 Figure 10. Diode Forward Voltage vs. Current ID = 13 A 0.01 0.01 0 25 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (°C) 150 Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 4 NTMS4937N PACKAGE DIMENSIONS SOIC−8 CASE 751−07 ISSUE AJ A 8 5 −X− B 1 S 4 0.25 (0.010) M Y M −Y− G K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244 C −Z− H D 0.25 (0.010) M SEATING PLANE N X 45 _ 0.10 (0.004) M J ZY S X S DIM A B C D G H J K M N S SOLDERING FOOTPRINT* 1.52 0.060 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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