NTP45N06L

NTP45N06L, NTB45N06L Power MOSFET 45 Amps, 60 Volts, Logic Level, N−Channel TO−220 and D2PAK Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits. Features http://onsemi.com • • • • • • • • • • • • • Pb−Free Packages are Available Higher Current Rating Lower RDS(on) Lower VDS(on) Lower Capacitances Lower Total Gate Charge Tighter VSD Specification Lower Diode Reverse Recovery Time Lower Reverse Recovery Stored Charge 45 AMPERES, 60 VOLTS RDS(on) = 28 mW N−Channel D G S Typical Applications MARKING DIAGRAMS 4 Drain 4 Power Supplies Converters Power Motor Controls Bridge Circuits TO−220 CASE 221A STYLE 5 NTx45N06L AYWW 1 2 3 1 Gate 2 Drain 4 Drain 4 3 Source 2 1 3 D2PAK CASE 418B STYLE 2 NTx45N06L AYWW 2 1 3 Drain Gate Source NTx45N06L x A Y WW = Device Code = P or B = Assembly Location = Year = Work Week ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. © Semiconductor Components Industries, LLC, 2004 1 August, 2004 − Rev. 1 Publication Order Number: NTP45N06L/D NTP45N06L, NTB45N06L MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Drain−to−Source Voltage Drain−to−Gate Voltage (RGS = 10 MW) Gate−to−Source Voltage − Continuous − Non−Repetitive (tpv10 ms) Drain Current − Continuous @ TA = 25°C − Continuous @ TA = 100°C − Single Pulse (tpv10 ms) Total Power Dissipation @ TA = 25°C Derate above 25°C Total Power Dissipation @ TA = 25°C (Note 1) Total Power Dissipation @ TA = 25°C (Note 2) Operating and Storage Temperature Range Single Pulse Drain−to−Source Avalanche Energy − Starting T J = 25°C (VDD = 50 Vdc, VGS = 5.0 Vdc, L = 0.3 mH IL(pk) = 40 A, VDS = 60 Vdc, RG = 25 W) Thermal Resistance − Junction−to−Case − Junction−to−Ambient (Note 1) − Junction−to−Ambient (Note 2) Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds Symbol VDSS VDGR VGS VGS ID ID IDM PD Value 60 60 "15 "20 45 30 150 125 0.83 3.2 2.4 −55 to +175 240 Adc Apk W W/°C W W °C mJ Unit Vdc Vdc Vdc TJ, Tstg EAS °C/W RqJC RqJA RqJA TL 1.2 46.8 63.2 260 °C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. When surface mounted to an FR4 board using 1″ pad size, (Cu Area 1.127 in2). 2. When surface mounted to an FR4 board using the minimum recommended pad size, (Cu Area 0.412 in2). ORDERING INFORMATION Device NTP45N06L NTB45N06L NTB45N06LG NTB45N06LT4 NTB45N06LT4G Package TO−220 D2PAK D2PAK (Pb−Free) D2PAK D2PAK (Pb−Free) Shipping† 50 Units/Rail 50 Units/Rail 50 Units/Rail 800 Tape & Reel 800 Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 2 NTP45N06L, NTB45N06L ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage (Note 3) (VGS = 0 Vdc, ID = 250 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C) Gate−Body Leakage Current (VGS = ± 15 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS (Note 4) Gate Threshold Voltage (Note 4) (VDS = VGS, ID = 250 mAdc) Threshold Temperature Coefficient (Negative) Static Drain−to−Source On−Resistance (Note 4) (VGS = 5.0 Vdc, ID = 22.5 Adc) Static Drain−to−Source On−Voltage (Note 4) (VGS = 5.0 Vdc, ID = 45 Adc) (VGS = 5.0 Vdc, ID = 22.5 Adc, TJ = 150°C) Forward Transconductance (Note 4) (VDS = 8.0 Vdc, ID = 12 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 5) Turn−On Delay Time Rise Time Turn−Off Delay Time Fall Time Gate Charge (VDS = 48 Vdc, ID = 45 Adc, 48 Vd 45 Ad VGS = 5.0 Vdc) (Note 4) .0 Vdc) SOURCE−DRAIN DIODE CHARACTERISTICS Forward On−Voltage Reverse Recovery Time (IS = 45 Adc, VGS = 0 Vdc, 45 Ad Vd dIS/dt = 100 A/ms) (Note 4) 100 A/ s) Reverse Recovery Stored Charge (IS = 45 Adc, VGS = 0 Vdc) (Note 4) (IS = 45 Adc, VGS = 0 Vdc, TJ = 150°C) VSD trr ta tb QRR − − − − − − in2). 1.01 0.92 56 30 26 0.09 1.15 − − − − − mC Vdc ns (VDD = 30 Vdc, ID = 45 Adc, Vdc, Adc, VGS = 5.0 Vdc, RG = 9.1 W) (Note 4) td(on) tr td(off) tf QT Q1 Q2 − − − − − − − 13 341 36 158 23 4.6 14.1 30 680 75 320 32 − − nC ns (VDS = 25 Vdc, VGS = 0 Vdc, 25 Vd Vd 1.0 MHz) f = 1.0 MHz) Ciss Coss Crss − − − 1212 352 90 1700 480 180 pF VGS(th) 1.0 − RDS(on) − VDS(on) − − gFS − 1.03 0.93 22.8 1.51 − − mhos 23 28 Vdc 1.8 4.7 2.0 − Vdc mV/°C mW V(BR)DSS 60 − IDSS − − IGSS − − − − 1.0 10 ±100 nAdc 67 67.2 − − Vdc mV/°C mAdc Symbol Min Typ Max Unit 3. When surface mounted to an FR4 board using the minimum recommended pad size, (Cu Area 0.412 4. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%. 5. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 3 NTP45N06L, NTB45N06L 80 VGS = 10 V ID, DRAIN CURRENT (AMPS) 70 60 50 40 30 VGS = 8 V 20 10 0 0 1 VGS = 9 V 2 VGS = 5.5 V VGS = 5 V VGS = 6 V VGS = 7 V VGS = 4.5 V ID, DRAIN CURRENT (AMPS) 80 70 60 50 40 30 20 10 0 1.8 TJ = 100°C TJ = −55°C 2.6 3.4 4.2 5 5.8 TJ = 25°C VDS > = 10 V VGS = 4 V VGS = 3.5 V 3 4 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) Figure 1. On−Region Characteristics RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) Figure 2. Transfer Characteristics 0.046 VGS = 5 V 0.042 0.038 0.034 0.03 0.026 0.022 0.018 0.014 0 10 20 30 40 50 60 70 80 TJ = −55°C TJ = 25°C TJ = 100°C 0.046 0.042 0.038 0.034 VGS = 5 V 0.03 0.026 0.022 0.018 0 10 20 30 40 50 60 70 80 ID, DRAIN CURRENT (AMPS) VGS = 10 V ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance vs. Gate−to−Source Voltage RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) 2 1.8 1.6 1.4 1.2 1 0.8 0.6 −50 −25 10 0 25 50 75 100 125 150 175 10000 ID = 22.5 A VGS = 5 V IDSS, LEAKAGE (nA) 1000 Figure 4. On−Resistance vs. Drain Current and Gate Voltage VGS = 0 V TJ = 150°C TJ = 125°C 100 TJ = 100°C 0 10 20 30 40 50 60 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage http://onsemi.com 4 NTP45N06L, NTB45N06L VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 4000 3600 C, CAPACITANCE (pF) 3200 2800 2400 2000 1600 1200 800 400 0 10 VDS = 0 V Ciss Crss VGS = 0 V TJ = 25°C 6 5 Q1 4 3 2 1 0 0 ID = 45 A TJ = 25°C 4 8 12 16 20 24 QT VGS Q2 Ciss Coss Crss 5 VGS 0 VDS 5 10 15 20 25 GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Qg, TOTAL GATE CHARGE (nC) Figure 7. Capacitance Variation 1000 48 IS, SOURCE CURRENT (AMPS) tr tf 100 td(off) 40 32 24 16 8 0 0.6 Figure 8. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge VGS = 0 V TJ = 25°C VDS = 30 V ID = 45 A VGS = 5 V t, TIME (ns) td(on) 10 1 10 RG, GATE RESISTANCE (W) 100 0.64 0.68 0.72 0.76 0.8 0.84 0.88 0.92 0.96 1 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) Figure 9. Resistive Switching Time Variation vs. Gate Resistance 1000 ID, DRAIN CURRENT (AMPS) VGS = 15 V SINGLE PULSE TC = 25°C EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) 280 Figure 10. Diode Forward Voltage vs. Current ID = 45 A 240 200 160 120 80 40 0 25 50 75 100 125 150 175 100 dc 10 10 ms 1 ms 1 RDS(on) Limit Thermal Limit Package Limit 100 ms 0.1 0.10 1 10 100 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 5 NTP45N06L, NTB45N06L 1 EFFECTIVE TRANSIENT THERMAL RESPONSE (NORMALIZED) Normalized to RqJC at Steady State 0.1 r(t), 0.01 0.00001 0.0001 0.001 0.01 t, TIME (s) 0.1 1 10 Figure 13. Thermal Response 10 r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) Normalized to RqJA at Steady State, 1″ square Cu Pad, Cu Area 1.127 in2, 3 x 3 inch FR4 board 1 0.1 0.01 0.001 0.00001 0.0001 0.001 0.01 0.1 t, TIME (s) 1 10 100 1000 Figure 14. Thermal Response http://onsemi.com 6 NTP45N06L, NTB45N06L PACKAGE DIMENSIONS TO−220 CASE 221A−09 ISSUE AA −T− B 4 SEATING PLANE F T S C NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND LEAD IRREGULARITIES ARE ALLOWED. DIM A B C D F G H J K L N Q R S T U V Z INCHES MIN MAX 0.570 0.620 0.380 0.405 0.160 0.190 0.025 0.035 0.142 0.147 0.095 0.105 0.110 0.155 0.018 0.025 0.500 0.562 0.045 0.060 0.190 0.210 0.100 0.120 0.080 0.110 0.045 0.055 0.235 0.255 0.000 0.050 0.045 −−− −−− 0.080 GATE DRAIN SOURCE DRAIN MILLIMETERS MIN MAX 14.48 15.75 9.66 10.28 4.07 4.82 0.64 0.88 3.61 3.73 2.42 2.66 2.80 3.93 0.46 0.64 12.70 14.27 1.15 1.52 4.83 5.33 2.54 3.04 2.04 2.79 1.15 1.39 5.97 6.47 0.00 1.27 1.15 −−− −−− 2.04 Q 123 A U K H Z L V G D N R J STYLE 5: PIN 1. 2. 3. 4. http://onsemi.com 7 NTP45N06L, NTB45N06L PACKAGE DIMENSIONS D2PAK CASE 418B−04 ISSUE J C E −B− 4 DIM A B C D E F G H J K L M N P R S V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. 418B−01 THRU 418B−03 OBSOLETE, NEW STANDARD 418B−04. INCHES MIN MAX 0.340 0.380 0.380 0.405 0.160 0.190 0.020 0.035 0.045 0.055 0.310 0.350 0.100 BSC 0.080 0.110 0.018 0.025 0.090 0.110 0.052 0.072 0.280 0.320 0.197 REF 0.079 REF 0.039 REF 0.575 0.625 0.045 0.055 MILLIMETERS MIN MAX 8.64 9.65 9.65 10.29 4.06 4.83 0.51 0.89 1.14 1.40 7.87 8.89 2.54 BSC 2.03 2.79 0.46 0.64 2.29 2.79 1.32 1.83 7.11 8.13 5.00 REF 2.00 REF 0.99 REF 14.60 15.88 1.14 1.40 V W A 1 2 3 S −T− SEATING PLANE K G D 3 PL 0.13 (0.005) H M W J TB M STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN SOLDERING FOOTPRINT* 8.38 0.33 10.66 0.42 1.016 0.04 5.08 0.20 3.05 0.12 17.02 0.67 SCALE 3:1 mm inches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). 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