NTP52N10G

NTP52N10 Power MOSFET 60 Amps, 100 Volts N−Channel Enhancement Mode TO−220 http://onsemi.com Features • Source−to−Drain Diode Recovery Time comparable to a Discrete • • • 60 AMPERES 100 VOLTS 30 mW @ VGS = 10 V Fast Recovery Diode Avalanche Energy Specified IDSS and RDS(on) Specified at Elevated Temperature Pb−Free Package is Available* N−Channel D Applications • PWM Motor Controls • Power Supplies • Converters G MAXIMUM RATINGS (TC = 25°C unless otherwise noted) S Symbol Value Unit Drain−to−Source Voltage VDSS 100 Vdc Drain−to−Source Voltage (RGS = 1.0 MW) VDGR 100 Vdc Rating Gate−to−Source Voltage − Continuous − Non−Repetitive (tpv10 ms) "20 "40 ID ID 60 40 156 PD 214 1.43 Watts W/°C Operating and Storage Temperature Range TJ, Tstg −55 to +175 °C Single Drain−to−Source Avalanche Energy − Starting TJ = 25°C (VDD = 50 V, VGS = 10 Vdc, IL(pk) = 40 A, L = 1.0 mH, RG = 25 W) EAS 800 mJ Total Power Dissipation @ TA 25°C Derate above 25°C Thermal Resistance − Junction−to−Case − Junction−to−Ambient Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds IDM RqJC RqJA 0.7 62.5 TL 260 Adc NTP52N10G AYWW °C/W °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Pulse Test: Pulse Width = 10 ms, Duty Cycle = 2%. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 March, 2006 − Rev. 4 D Vdc VGS VGSM Drain − Continuous @ TA 25°C − Continuous @ TA 100°C − Pulsed (Note 1.) 4 MARKING DIAGRAM & PIN ASSIGNMENT 1 1 2 3 TO−220 CASE 221A STYLE 5 A Y WW G 1 G D S = Assembly Location = Year = Work Week = Pb−Free Package ORDERING INFORMATION Device Package Shipping NTP52N10 TO−220 50 Units / Rail TO−220 (Pb−Free) 50 Units / Rail NTP52N10G Publication Order Number: NTP52N10/D NTP52N10 ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) Symbol Characteristic Min Typ Max Unit 100 − − 160 − − − − − − 5.0 50 − − ±100 2.0 − 2.92 −8.75 4.0 − − − 0.023 0.050 0.030 0.060 − 1.25 1.45 gFS − 31 − Mhos Ciss − 2250 3150 pF Coss − 620 860 Crss − 135 265 td(on) − 15 25 tr − 95 180 td(off) − 74 150 tf − 100 190 Qtot − 72 135 Qgs − 13 − Qgd − 37 − VSD − − 1.06 0.95 1.5 − Vdc trr − 148 − ns ta − 106 − tb − 42 − QRR − 0.66 − OFF CHARACTERISTICS V(BR)DSS Drain−to−Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VGS = 0 Vdc, VDS = 100 Vdc, TJ =25°C) (VGS = 0 Vdc, VDS = 100 Vdc, TJ =125°C) IDSS Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/°C mAdc nAdc ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = 250 mAdc) Temperature Coefficient (Negative) VGS(th) Static Drain−to−Source On−State Resistance (VGS = 10 Vdc, ID = 26 Adc) (VGS = 10 Vdc, ID = 26 Adc, TJ = 125°C) RDS(on) Drain−to−Source On−Voltage (VGS = 10 Vdc, ID = 52 Adc) VDS(on) Forward Transconductance (VDS = 26 Vdc, ID = 10 Adc) Vdc mV/°C W Vdc DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Transfer Capacitance SWITCHING CHARACTERISTICS (Notes 2. & 3.) Turn−On Delay Time Rise Time Turn−Off Delay Time (VDD = 80 Vdc, ID = 52 Adc, VGS = 10 Vdc, RG = 9.1 W) Fall Time Gate Charge (VDS = 80 Vdc, ID = 52 Adc, VGS = 10 Vdc) ns nC BODY−DRAIN DIODE RATINGS (Note 2.) Diode Forward On−Voltage (IS = 52 Adc, VGS = 0 Vdc) (IS = 52 Adc, VGS = 0 Vdc, TJ = 125°C) Reverse Recovery Time (IS = 52 Adc, VGS = 0 Vdc, diS/dt = 100 A/ms) Reverse Recovery Stored Charge 2. Indicates Pulse Test: P.W. = 300 ms Max, Duty Cycle = 2%. 3. Switching characteristics are independent of operating junction temperature. http://onsemi.com 2 mC NTP52N10 ID, DRAIN CURRENT (AMPS) 8V 80 TJ = 25°C 9V 7V 6V 60 5.5 V 40 20 5V 4.5 V 4V 0 1 2 3 4 5 6 7 8 9 80 60 40 TJ = 25°C 20 TJ = 100°C 10 2 TJ = −55°C 7 6 5 Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics 8 0.05 0.04 TJ = 25°C 0.04 TJ = 100°C 0.03 0.03 0.02 TJ = 25°C 0.01 TJ = −55°C 10 20 30 40 50 60 VGS = 10 V 0.02 VGS = 15 V 0.01 70 80 90 100 0 0 20 40 60 80 100 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) Figure 3. On−Resistance versus Drain Current and Temperature Figure 4. On−Resistance versus Drain Current and Gate Voltage 10000 ID = 26 A VGS = 10 V VGS = 0 V TJ = 150°C IDSS, LEAKAGE (nA) 2.5 4 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) VGS = 10 V 0 3 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 0.05 RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) VDS ≥ 10 V 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 0 RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) 100 VGS = 10 V ID, DRAIN CURRENT (AMPS) 100 2 1.5 1 1000 100 TJ = 100°C 0.5 0 −50 −25 0 25 50 75 100 125 150 175 10 30 40 50 60 70 80 90 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 5. On−Resistance Variation with Temperature Figure 6. Drain−To−Source Leakage Current versus Voltage http://onsemi.com 3 100 NTP52N10 POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Dt) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain−gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off−state condition when calculating td(on) and is read at a voltage corresponding to the on−state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG − VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn−on and turn−off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG − VGSP)] td(off) = RG Ciss In (VGG/VGSP) 6000 C, CAPACITANCE (pF) 5000 VDS = 0 V VGS = 0 V TJ = 25°C Ciss 4000 3000 Crss Ciss 2000 Coss 1000 0 10 Crss 5 VGS 0 VDS 5 10 15 20 25 GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation http://onsemi.com 4 18 QT 16 80 14 12 60 10 VGS 8 Q1 6 40 Q2 4 ID = 52 A TJ = 25°C VDS 2 0 0 10 20 30 40 50 QG, TOTAL GATE CHARGE (nC) 60 20 0 70 1000 VDD = 80 V ID = 52 A VGS = 10 V tf td(off) tr 100 t, TIME (ns) 100 20 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) NTP52N10 td(on) 10 1 1 Figure 8. Gate−To−Source and Drain−To−Source Voltage versus Total Charge 10 RG, GATE RESISTANCE (OHMS) 100 Figure 9. Resistive Switching Time Variation versus Gate Resistance DRAIN−TO−SOURCE DIODE CHARACTERISTICS IS, SOURCE CURRENT (AMPS) 60 50 VGS = 0 V TJ = 25°C 40 30 20 10 0 0.25 0.35 0.45 0.55 0.65 0.75 0.85 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) 0.95 Figure 10. Diode Forward Voltage versus Current SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain−to−source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance−General Data and Its Use.” Switching between the off−state and the on−state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 ms. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) − TC)/(RqJC). A Power MOSFET designated E−FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non−linearly with an increase of peak current in avalanche and peak junction temperature. Although many E−FETs can withstand the stress of drain−to−source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown http://onsemi.com 5 NTP52N10 in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. ID, DRAIN CURRENT (AMPS) 1000 VGS = 20 V SINGLE PULSE TC = 25°C 100 10 ms 100 ms 10 1 ms 1 RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 0.1 10 ms dc 10 1 100 VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) 1000 EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ) SAFE OPERATING AREA 800 600 500 400 300 200 100 0 25 Figure 11. Maximum Rated Forward Biased Safe Operating Area r(t). EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) ID = 40 A 700 150 50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature 1.0 D = 0.5 0.2 0.1 0.1 P(pk) 0.05 0.02 t1 0.01 t2 DUTY CYCLE, D = t1/t2 SINGLE PULSE 0.01 0.00001 0.0001 0.001 0.01 t, TIME (ms) RqJC(t) = r(t) RqJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) − TC = P(pk) RqJC(t) 0.1 Figure 13. Thermal Response di/dt IS trr ta tb TIME 0.25 IS tp IS Figure 14. Diode Reverse Recovery Waveform http://onsemi.com 6 1.0 10 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TO−220 CASE 221A ISSUE AK DATE 13 JAN 2022 SCALE 1:1 STYLE 1: PIN 1. 2. 3. 4. BASE COLLECTOR EMITTER COLLECTOR STYLE 2: PIN 1. 2. 3. 4. BASE EMITTER COLLECTOR EMITTER STYLE 3: PIN 1. 2. 3. 4. CATHODE ANODE GATE ANODE STYLE 4: PIN 1. 2. 3. 4. MAIN TERMINAL 1 MAIN TERMINAL 2 GATE MAIN TERMINAL 2 STYLE 5: PIN 1. 2. 3. 4. GATE DRAIN SOURCE DRAIN STYLE 6: PIN 1. 2. 3. 4. ANODE CATHODE ANODE CATHODE STYLE 7: PIN 1. 2. 3. 4. CATHODE ANODE CATHODE ANODE STYLE 8: PIN 1. 2. 3. 4. CATHODE ANODE EXTERNAL TRIP/DELAY ANODE STYLE 9: PIN 1. 2. 3. 4. GATE COLLECTOR EMITTER COLLECTOR STYLE 10: PIN 1. 2. 3. 4. GATE SOURCE DRAIN SOURCE STYLE 11: PIN 1. 2. 3. 4. DRAIN SOURCE GATE SOURCE STYLE 12: PIN 1. 2. 3. 4. MAIN TERMINAL 1 MAIN TERMINAL 2 GATE NOT CONNECTED DOCUMENT NUMBER: DESCRIPTION: 98ASB42148B TO−220 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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